CN102142415A - 具有嵌入式元件的集成电路封装 - Google Patents

具有嵌入式元件的集成电路封装 Download PDF

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Publication number
CN102142415A
CN102142415A CN2010106038860A CN201010603886A CN102142415A CN 102142415 A CN102142415 A CN 102142415A CN 2010106038860 A CN2010106038860 A CN 2010106038860A CN 201010603886 A CN201010603886 A CN 201010603886A CN 102142415 A CN102142415 A CN 102142415A
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base plate
dielectric base
conductive layer
integrated circuit
patterned conductive
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CN102142415B (zh
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卢克·英格兰
道格拉斯·阿伦·霍克斯
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Fairchild Semiconductor Corp
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Fairchild Semiconductor Corp
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Abstract

本申请公开了半导体管芯封装，其中，该半导体管芯封装具有嵌入在电介质基板中的第一和第二分立元件。集成电路(IC)管芯表面安装在电介质基板的第一侧上。半导体管芯封装包括位于电介质基板的第二侧上的多个导电区，用于安装半导体管芯封装。多个贯通过孔将IC管芯耦接至第一和第二分立元件以及多个导电区。

Description

具有嵌入式元件的集成电路封装
技术领域
本申请文件涉及半导体管芯封装，其中，该半导体管芯封装具有嵌入在电介质基板中的第一和第二分立元件。
背景技术
例如蜂窝电话、个人数字助理、数字摄像机、膝上电脑等电子设备一般包括多个封装的半导体集成电路(IC)芯片以及组装在互连基板上的表面安装元件。对于将更多功能和特征结合到电子设备中并同时减小电子设备尺寸，存在着持续的市场需求。这进而带来了对互连基板的设计、尺寸和组装的不断提高的要求。随着组装的元件的数目增加，基板面积和成本增加，而对更小形状因子的需求在不断增加。
发明内容
本申请文件涉及半导体管芯封装，其中，该半导体管芯封装具有嵌入在电介质基板中的第一和第二分立元件。集成电路(IC)管芯表面安装或线键合在电介质基板的第一侧。半导体管芯封装包括位于电介质基板的第二侧上的多个导电区，用于安装半导体管芯封装。多个贯通过孔将IC管芯耦接至第一和第二分立元件以及多个导电区。
该概述希望提供对本专利申请的主题的简要回顾。不希望提供对本发明的排他性或穷尽性的说明。所包括的详细描述用于提供本专利申请的进一步有关信息。
附图说明
在不一定按照比例绘制的附图中，不同视图中类似的附图标记可以描述相似元件。具有不同字母后缀的类似附图标记可以表示相似元件的不同实例。附图通过示例方式而非限制性方式一般地说明本申请文件中讨论的多个实施例。
图1一般地说明IC封装示例的横截面视图，该IC封装具有在其上安装有IC管芯的基板中嵌入的多个元件；
图2一般地说明图1的IC封装的第一底视图，示出了图案化的导电层和多个暴露的导电区，用于将图1的IC封装耦接至外部互连基板。
图3一般地说明图1的IC封装的第二底视图，示出了图案化的导电层、多个贯通过孔以及嵌入式元件的定位。
图4一般地说明图1的IC封装的第一顶视图，示出了图案化的导电层、多个贯通过孔以及内嵌元件的定位。
图5一般地说明图1的IC封装的第二顶视图，示出了图案化的导电层的迹线、IC管芯、以及将IC管芯耦接至迹线的导线。
具体实施方式
本申请发明人已经认识到具有嵌入在电介质基板中的第一和第二分立元件的紧凑的IC封装。IC管芯安装至电介质基板并且耦接至第一和第二分立元件。多个贯通过孔设置在电介质基板内，用于将IC管芯以及第一和第二分立元件耦接至电介质基板的各侧。将电绝缘材料设置在IC和电介质基板上，以形成IC封装。电介质基板可以包括在IC管芯相对侧的多个键合焊盘。
图1一般地说明IC封装100的一个示例的横截面视图。IC封装100包括嵌入在电介质基板106中的第一分立元件102和第二分立元件104。在示例中，电介质基板106可以包括半固化片(prepreg)材料。电介质基板106包括第一侧108和第二侧110。在示例中，第一分立元件102和第二分立元件104在电介质基板106内彼此邻近。
在示例中，电介质基板106可以包括在电介质基板106的第一侧108上的第一图案化的导电层116。第一图案化导电层116可以包括多条导电迹线。导电迹线是从金属片(例如，铜)形成的，金属片被层压到电介质基板106的第一侧108上，然后被蚀刻以形成导电迹线图案。在示例中，随后采用焊料掩模覆盖第一图案化导电层116以及电介质基板106的第一侧108。焊料掩模选择性地暴露第一图案化导电层116的导电区(例如，键合焊盘或焊盘)，用于将IC管芯114电和物理地耦接在这些区域上。在示例中，暴露的导电区的一部分是用于物理上耦接IC管芯的假焊盘。假焊盘不与贯通过孔122电耦接，也不与第一和第二分立元件102、104电耦接。在示例中，电介质基板106、第一图案化导电层116和焊料掩模的组合可以形成印刷电路板。
IC管芯114安装在电介质基板106的第一侧108上，并且在多个暴露导电区电耦接至第一图案化导电层116。在示例中，利用多条互连导线118将IC管芯114以线键合方式连接至第一图案化导电层116。多条导线118从IC管芯114上的焊盘耦接至第一图案化导电层116的焊盘。在备选示例中，利用多个焊球或其他倒装芯片互连材料，将IC管芯114以倒装芯片方式安装至第一图案化导电层116。
在示例中，采用电绝缘材料120覆盖IC管芯114和电介质基板106的第一侧108。电绝缘材料120将IC管芯114与外部影响电绝缘。在示例中，电绝缘材料120可以包括模合成物(mold compound)，如环氧树脂、硅树脂(silicone)、聚酰亚胺、或者这些材料中一种或多种的组合。
在示例中，以针对第一侧108所述的相似方式，在电介质基板106的第二侧110上安装第二图案化导电层124。第二图案化导电层124可以包括多条导电迹线。导电迹线是从金属片(例如，铜)形成的，金属片被层压到电介质基板106的第二侧110上，然后被蚀刻以形成导电迹线图案。在示例中，随后采用焊料掩模覆盖第二图案化导电层124以及电介质基板106的第二侧110。焊料掩模选择性地暴露第二图案化导电层124的导电区(例如，输入-输出(IO)焊盘)，以将IC封装100电和物理地耦接至外部互连基板(例如，另一印刷电路板)。在示例中，暴露的导电区的一部分是用于物理上耦接IC封装100的假焊盘。假焊盘不与贯通过孔122电耦接，也不与第一和第二分立元件102、104电耦接。
在示例中，在电介质基板106内设置多个贯通过孔122，以将第一图案化导电层116电耦接至第二图案化导电层124。这多个贯通过孔122提供IC管芯114与电介质基板106的第二侧110的多个接触区之间的电耦接。在示例中，多个贯通过孔122也为第一图案化导电层116上的与第一和第二分立元件102、104耦接的区域提供与第二图案化导电层124之间的电耦接。
具有嵌入式分立元件102、104的电介质基板106与安装在其上的IC管芯114的组合封装形成了紧凑的IC封装100，IC封装100可以经由电介质基板106的第二侧110上暴露的导电区来表面安装至外部互连基板。
在电介质基板106内嵌入第一和第二分立元件102、104可以提供IC封装100的减小的尺寸，并可以提供分立元件102、104与IC管芯114之间的缩短的互连长度。在示例中，可以通过例如由芬兰的Imbera Electronics或者奥地利的AT&S开发的嵌入工艺，将第一和第二分立元件102、104嵌入在电介质基板106中。
简而言之，可以通过首先将管芯附着至导电层，将一个或多个管芯(例如，第一分立元件102)嵌入在电介质基板中。然后，在管芯周围设置半固化片材料，从而将管芯嵌入到半固化片材料中。半固化片材料可以包括针对管芯的预切(precut)孔，半固化片材料可以设置在管芯周围并且设置在导电层上。
然后，可以在半固化片材料上设置第二导电层，所得到的在任一侧具有导电层并且嵌有管芯的半固化片的构造可以层压在一起。一旦将管芯嵌入到电介质基板中，形成贯通过孔。可以穿过电介质基板以及其上层压的层，钻出用于贯通过孔的孔钻。在孔内沉积金属(例如，铜)。IC管芯(例如，IC管芯114)可以安装到电介质基板条带阵列的其中嵌入有管芯的合适的一侧。然后，可以添加将IC管芯耦接至电介质基板上暴露导电部分的互连导线，并且可以用电绝缘材料(例如，电绝缘材料120)覆盖IC管芯，在IC管芯上电绝缘材料固化，以形成IC封装100的阵列。然后，可以机械锯开IC封装阵列，以将各个IC封装100彼此隔离开来。
图2说明图1的电介质基板106的第二侧110的第一横截面视图的示例。图2示出了相对于图1所示取向，从底部仰视的电介质基板106的第二侧110。图2说明第二图案化导电层124和由焊料掩模暴露的多个导电区202。这多个导电区202一般地在电介质基板106的第二侧110上规则地分隔开，在图2中示出为圆圈。在示例中，第二图案化导电层可以包括大平面部分(一般地在204示出)以及多条迹线206。大平面部分204可以为耦接的元件(例如，第一分立元件102)提供良好的热传导和/或改进的电性能。多条迹线206将元件或贯通过孔122耦接至暴露的导电区124。
图3说明图1的电介质基板106的第二侧110的第二横截面视图的示例。图3示出了第二图案化导电层124以及多个贯通过孔122，并示出了嵌入在电介质基板106中的第一和第二分立元件102、104的设置。
如图所示，迹线206可以耦接至贯通过孔122，或者迹线206可以耦接至分立元件(例如，第二分立元件104)。在图3中，贯通过孔122示出为较小的圆圈。较大的圆圈是图案化导电层124的部分。在示例中，大多数贯通过孔122可以定位为朝着电介质基板106的外边缘。有利地，将贯通过孔122定位为朝着外边缘，可以提供嵌入在电介质基板106中的第一和第二分立元件102、104的高效布局。然而，在其他示例中，一些或者所有贯通过孔122可以定位在第一和第二分立元件102、104之间。
图3说明在第二图案化导电层124下面的第一和第二分立元件102、104的定位。在示例中，电介质基板106的第二侧110的多个开口302提供了第一和第二分立元件102、104与第二图案化导电层124的大平面的电和热耦接。虽然示出了电介质基板106中一定数目的开口302，但是在一些示例中，可以提供更多或更少的开口302。在示例中，可以增加图3所示的开口302的数目，以提供与第一和第二分立元件102、104的增强的电和热耦接。
图4说明图1的电介质基板106的第一侧108的第一横截面视图的示例。图4示出了第一图案化导电层116、多个贯通过孔122、以及嵌入在电介质基板106中的第一和第二分立元件102、104。图4说明在第一图案化导电层116下面的第一和第二分立元件102、104的定位。
第一图案化导电层116包括多条迹线402，用于将贯通过孔122电耦接至分立元件(例如，第一分立元件102)以及暴露的导电区404(例如，焊盘)，暴露的导电区404用于耦接来自IC管芯114的导线。在图4中，贯通过孔122示出为圆圈。第一图案化导电层116还可以包括用于耦接至第一和第二分立元件102、104的较大区域。这些较大区域利用电介质基板106第一侧108中的开口406来耦接至第一和第二分立元件102、104。虽然示出了电介质基板106中一定数目的开口302，但是在一些示例中，可以提供更多或更少的开口302。在示例中，可以增加图3所示的开口302的数目，以提供与第一和第二分立元件102、104的增强的电和热耦接。
图5说明图1的电介质基板106的第一侧108的顶视图的示例。为说明目的，图5说明第一侧108的顶视图，而未示出了电绝缘材料120。图5示出了具有焊盘502的IC管芯114，焊盘502利用互连导线405耦接至第一图案化导电层116的暴露导电部分404。
在示例中，第一和第二分立元件可以包括晶体管，IC管芯114可以包括晶体管的控制器。具体而言，第一和第二分立元件102、104可以包括高侧和低侧金属氧化物半导体场效应晶体管(MOSFET)，这些晶体管与IC管芯114一起形成功率转换器。在具体示例中，功率转换器可以是降压转换器(buck converter)，第一分立元件102可以包括高侧MOSFET，而第二分立元件104可以包括低侧MOSFET。
在示例中，两个晶体管的源极都耦接至电介质基板106的第二侧110上的第二图案化导电层124的大部分。该耦接至晶体管源极的大表面区域可以为外部键合焊盘设置(例如，多个导电区)提供良好的热性能，这是由于可获得大的热耗散面积。
有利地，在电介质基板106内嵌入第一和第二分立元件102、104可以减小IC封装100的尺寸。此外，在电介质基板内嵌入第一和第二分立元件102、104可以提高热性能，因为产生大部分热的元件(第一和第二分立元件102、104)定位在外部暴露导电部分202附近，有助于容易地消除来自第一和第二分立元件102、104的热。
其他说明
上述详细描述包括对附图的参照，附图形成了详细描述的一部分。附图通过示意方式示出了可以实施本发明的特定实施例。这些实施例在本文中也称为“示例”。这些示例可以包括除示出和描述的元件之外的其他元件。然而，本发明人还考虑到其中仅提供了示出和描述的那些元件的示例。
该申请文件中参照的所有公开、专利和专利文档的全部内容作为参考结合在此，就如分别作为参考结合在此。在该文件和如此参考结合的这些文档的使用不一致情况下，结合的参考的使用应当视为对该文件的补充；对于不可调和的不一致，该文件中的使用占主导。
在该文件中，如专利文档中通常使用的一样，使用用语“一”或“一个”来包括一个或多于一个，与任何其他实例或者“至少一个”或“一个或多个”的使用无关。在该文件中，使用用语“或”来指示非排他性的“或”，从而“A或B”包括“A而不是B”、“B而不是A”以及“A和B”，除非另有指示。在所附权利要求中，用语“包括”和“其中”用作相应用语“包含”和“在其中”的普通英语等同词。此外，在所附权利要求中，用语“包括”和“包含”是开放式的，即，权利要求中除了列举在这种用语之后的元件之外还包括其他元件的系统、设备、产品或方法仍被视为落入该权利要求的范围内。此外，在随附权利要求中，用语“第一”、“第二”、“第三”等仅仅用作标签，而不是要对它们的对象施加编号要求。
此外，在该文件中，当将例如材料或IC管芯等第一元件称为在第二元件“上”(例如，安装在第二元件上)时，第一元件可以是直接在第二元件上，或者也可以存在中间元件。在该文件中，当将例如层、区域或基板等第一元件称为“耦接至”第二元件时，第一元件可以直接耦接至第二元件，或者可以存在一个或多个中间元件。相反，当将第一元件称为“直接在另一元件上”或“直接耦接至另一元件”时，不存在中间元件。
本文描述的方法示例可以是至少部分地由机器或计算机实施的。一些示例可以包括计算机可读介质或机器可读介质，其上编码有将电子设备配置为执行如上示例所述的方法的指令。这些方法的一种实施方式包括代码，例如微代码、汇编语言代码、高级语言代码等。这种代码可以包括用于执行多种方法的计算机可读指令。代码可以形成计算机程序产品的部分。此外，代码可以在执行期间或在其他时候有形地存储一个或多个易失性或非易失性计算机可读介质上。这些计算机可读介质可以包括，但不限于，硬盘、可移除磁盘、可移除光盘(例如，光盘和数字视频盘)、盒式磁带、存储卡或棒、随机存储存储器(RAM)、只读存储器(ROM)等。
以上描述是示意性而非限制性的。例如，上述示例(或者示例的一个或多个方面)可以彼此组合使用。可以由例如阅读上述描述的本领域普通技术人员来使用其他实施例。按照37 C.F.R.§1.72(b)提供了摘要，以允许读者快速确定本技术公开的本质。可以理解的是，摘要不用于解释或限定权利要求的范围或含义。此外，在以上具体实施方式中，可以将多种特征分组以精简本公开。这不应理解为未要求保护的公开的特征对于任何权利要求是必不可少的。而是，发明主题可以存在于比具体公开的示例的所有特征更少的特征中。因此，所附权利要求在此结合到具体实施方式中，每一个权利要求自身作为独立实施例而存在。本发明的范围应该参照所附权利要求以及这些权利要求赋予的等同物的整个范围来确定。

Claims (20)

1.一种半导体管芯封装，包括：
电介质基板，具有第一侧和与第一侧相对的第二侧；
第一分立元件，嵌入在电介质基板中；
第二分立元件，嵌入在电介质基板中；
集成电路管芯，表面安装在电介质基板的第一侧并电耦接至第一和第二分立元件；
电绝缘材料，设置在集成电路管芯上以及电介质基板第一侧的至少一部分上；
多个导电区，位于电介质基板的第二侧上，用于安装电介质基板；以及
多个贯通过孔，设置在电介质基板内，所述多个贯通过孔中的至少一个将集成电路管芯电耦接至所述多个导电区中的至少一个。
2.根据权利要求1所述的半导体管芯封装，其中，所述多个导电区包括针对球栅阵列安装或触点栅格阵列安装之一的键合焊盘。
3.根据权利要求1所述的半导体管芯封装，包括：在电介质基板的第一侧的图案化导电层，位于集成电路管芯与电介质基板之间，
其中集成电路管芯、第一和第二分立元件以及所述多个贯通过孔电耦接至图案化导电层。
4.根据权利要求3所述的半导体管芯封装，其中，集成电路管芯以倒装芯片方式安装至图案化导电层。
5.根据权利要求3所述的半导体管芯封装，其中，集成电路管芯以线键合方式安装至图案化导电层。
6.根据权利要求3至5任一项所述的半导体管芯封装，其中，所述多个贯通过孔中的至少一个以及图案化导电层将第一分立元件电耦接至所述多个导电区中的至少一个。
7.根据权利要求1所述的半导体管芯封装，包括：位于电介质基板的第二侧的图案化导电层，
其中图案化导电层提供第一和第二分立元件与所述多个贯通过孔之间的电耦接。
8.根据权利要求1所述的半导体管芯封装，其中，电绝缘材料包括环氧树脂或硅树脂中的至少一种。
9.根据权利要求1所述的半导体管芯封装，其中，第一分立元件包括第一晶体管，第二分立元件包括第二晶体管，集成电路管芯包括控制器，所述控制器用于控制第一和第二晶体管的操作，以使半导体管芯封装操作为功率转换器。
10.根据权利要求1所述的半导体管芯封装，其中，电介质基板包括半固化片材料。
11.一种封装方法，包括：
在电介质基板中嵌入第一和第二分立元件，其中第一分立元件与第二分立元件邻近；
在电介质基板中形成多个贯通过孔；
在电介质基板的第一侧形成多个导电区，其中至少一个导电区电耦接至所述多个贯通过孔中的至少一个；
在电介质基板的第二侧安装集成电路管芯，第二侧与第一侧相对，其中集成电路管芯电耦接至第一和第二分立元件以及至少一个贯通过孔；以及
在集成电路管芯以及半导体基板第二侧的至少一部分上固化电绝缘材料。
12.根据权利要求11所述的封装方法，包括：
在电介质基板的第二侧上层压图案化导电层，以使图案化导电层设置在电介质基板和集成电路管芯之间，其中，集成电路管芯以及第一和第二分立元件电耦接至图案化导电层。
13.根据权利要求12所述的封装方法，其中，安装集成电路管芯包括：将集成电路管芯以倒装芯片方式安装至图案化导电层。
14.根据权利要求12所述的封装方法，其中，安装集成电路管芯包括：将集成电路管芯以线键合方式安装至图案化导电层。
15.根据权利要求11所述的封装方法，包括：
在电介质基板的第一侧上层压图案化导电层；以及
其中，形成多个导电区包括：采用焊料掩模涂布图案化导电层，以使多个导电区是未被焊料掩模覆盖的暴露区。
16.根据权利要求11至15任一项所述的封装方法，其中，所述多个导电区是针对球栅阵列安装或触点栅格阵列安装之一而配置的。
17.一种功率转换器系统，包括：
电介质基板，具有第一侧和第二侧；
高侧晶体管管芯，嵌入在电介质基板中；
低侧晶体管管芯，嵌入在电介质基板中，低侧晶体管与高侧晶体管邻近；
在电介质基板的第一侧上的第一图案化导电层，其中，高侧晶体管管芯和低侧晶体管管芯耦接至第一图案化导电层；
在电介质基板的第二侧上的第二图案化导电层，其中，高侧晶体管管芯和低侧晶体管管芯耦接至第二图案化导电层；
多个贯通过孔，至少一个贯通过孔耦接至第一图案化导电层，并且至少一个贯通过孔耦接至第二图案化导电层；
集成电路管芯，安装在电介质基板的第一侧上并耦接至第一图案化导电层，集成电路包括针对高侧晶体管管芯和低侧晶体管管芯的控制器；
电绝缘材料，设置在集成电路管芯以及电介质基板第一侧的至少一部分上；以及
在电介质基板的第二侧上的多个导电区，用于安装电介质基板。
18.根据权利要求17所述的功率转换器系统，其中，电介质基板包括半固化片材料。
19.根据权利要求17至18任一项所述的功率转换器系统，其中，利用多条导线将集成电路管芯安装至图案化导电层。
20.根据权利要求17至18任一项所述的功率转换器系统，其中，所述多个导电区是针对安装至印刷电路板的球栅阵列安装或触点栅格阵列安装之一而配置的。
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