CN102084488A - 纳米结构mos电容器 - Google Patents

纳米结构mos电容器 Download PDF

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CN102084488A
CN102084488A CN200980122331XA CN200980122331A CN102084488A CN 102084488 A CN102084488 A CN 102084488A CN 200980122331X A CN200980122331X A CN 200980122331XA CN 200980122331 A CN200980122331 A CN 200980122331A CN 102084488 A CN102084488 A CN 102084488A
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nano wire
nanostructure
mos capacitance
capacitance device
gate electrode
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L-E·沃纳森
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BTG International Ltd
QuNano AB
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Abstract

本发明提供纳米结构MOS电容器，其包括被介质层(5)至少部分包围的纳米线(2)以及包围该介质层(5)至少一部分的栅电极(4)。优选地，该纳米线(2)从基板(12)凸出。该栅电极(4)限定纳米线(2)的栅控部分(7)，在向栅电极(4)施加第一预定电压时允许该栅控部分(7)完全耗尽。还提供一种通过使用这种纳米结构MOS电容器在电子电路中提供可变电容的方法。归功于本发明，可以提供具有增加的电容调制范围的MOS电容器。本发明的另一优点是提供和现有技术MOS电容相比具有相对较低耗尽电容的MOS电容器。

Description

纳米结构MOS电容器
技术领域
本发明涉及MOS(金属-氧化物-半导体)电容器，并且尤其涉及具有可变电容的电容器。
背景技术
MOS电容器是集成电路的基本构造块之一，且它们例如常用于压控振荡器。大范围的调制通常是优选的。在压控振荡器中，这增加了振荡器的调谐范围。
图1示意性地说明现有技术MOS电容器，其包括布置在半导体基板(S)上的栅电极(E)，以及中间的介质层(D)。半导体本体电连接到基板(S)相对一侧上的体电极(B)。当向栅电极(E)施加合适的电压时，在半导体基板(S)中形成耗尽区(A)。
在MOS电容器中，常称为积累电容(accumulation capacitance)的最大电容由中间介质层的厚度和介电常数设置，而常称为耗尽电容的最小电容由半导体基板的掺杂设置且依赖于耗尽区的长度。通过改变用于电容器的偏置，电容可以在最大值和最小值之间变化。常规MOS电容器在电容调制范围中具有固有限制且耗尽电容相当高。
发明内容
鉴于上述内容，本发明的一个目的是提供一种具有宽电容调制范围和低耗尽电容的MOS电容器。这通过根据所附权利要求的纳米结构MOS电容器和用于通过使用该根据所附权利要求的纳米结构MOS电容器来改变电子电路中的电容的方法实现。
根据本发明的纳米结构MOS电容器包括电连接到第一电极的纳米线、可选地覆盖该纳米线的至少一部分的介质层以及覆盖介质层的至少一部分的栅电极。纳米线的至少一部分和第一电极分别用作上述半导体本体和体电极。栅电极是布置在介质层的至少一部分周围的至少第一径向层，以形成长度为L的纳米线的栅控部分，且介质层是沿着纳米线的至少一部分布置在该纳米线周围的至少第二径向层。
在根据本发明的纳米结构MOS电容器的一个实施例中，栅控部分的整个纳米线剖面适于在向栅电极施加预定电压时完全耗尽。
优选地，纳米线2的宽度小于4L，优选地小于0.4L，且更优选地小于0.1L。
优选地，纳米线2的宽度小于100μm，优选地小于60μm，且更优选地小于20μm。
在本发明的其他实施例中，纳米结构MOS电容器在用于改变电容的电子电路、压控振荡器装置以及采样和保持电路装置中使用。
归功于本发明，可以提供具有增加的电容调制范围的MOS电容器。
本发明的另一优点是提供与现有技术MOS电容相比具有相对较低耗尽电容的MOS电容器。
本发明的实施例在从属权利要求中限定。当结合附图和权利要求考虑时，本发明的其他目的、优点和新颖特征从下面本发明的详细描述中显现。
附图说明
现在将参考附图描述本发明的优选实施例，其中：
图1是根据现有技术的MOS电容器的示意性剖面图；
图2是根据本发明的一个实施例的纳米结构MOS电容器的示意性剖面图；
图3是根据本发明的另一实施例具有金字塔形状的纳米结构MOS电容器的示意性剖面图；
图4a-d示意性地说明本发明的一种实施方式和对其的C(V)测量的实验结果；
图5示意性地说明(a)：图4d的C(V)数据集的理论拟合，以及(b-d)：三个不同偏置下的能带弯曲(band bending)和电子密度；
图6是根据本发明的压控振荡器装置的一个实施例的电路图；
图7是根据本发明的采样和保持电路的一个实施例的电路图；
图8示意性地说明根据本发明的一个实施例用于改变电子电路中的电容的方法；以及
图9示意性地说明根据本发明的纳米结构肖特基二极管。
具体实施方式
本发明基于使用纳米线来形成纳米结构MOS电容器。
纳米线通常被解释为其直径是纳米维度(dimonsion)的一维纳米结构。术语纳米线暗示着横向尺寸是纳米级的而纵向尺寸没有限制。这种一维纳米结构还常被称为纳米晶须、一维纳米元件、纳米棒、纳米管等。一般地，认为纳米线具有每一个都不大于300nm的至少两个维度。然而，纳米线可以具有高达约1μm的直径或宽度。纳米线的一维性质提供独特的物理、光学和电子属性。这些属性例如可用于形成利用量子机械效应的器件或者形成成分不同的材料的异质结构，这些成分不同的材料通常由于大晶格失配而不能组合。一个示例是集成具有减小的晶格蚀刻限制的半导体材料且允许在诸如Si基板的很多半导体基板上生长III-V族结构。术语纳米线暗示着一维性质常常与细长形状相关联。然而，纳米线还可以从一些所述独特属性受益而无需具有细长形状。举例而言，可以在具有相对较大缺陷密度的基板材料上形成非细长纳米线以便提供用于进一步加工的无缺陷模板，或者以便形成基板材料和其他材料之间的链接。因此，本发明不限于细长形状的纳米线。因为纳米线可以具有各种剖面形状，直径旨在表示有效直径。
图2示意性地说明根据本发明的纳米MOS电容器的一个实施例，其包括电连接到第一电极21的半导体纳米线2、介质层5以及栅电极4。纳米线2优选地从基板12凸出。栅电极4由布置在介质层5的至少一部分周围(即，以缠绕栅极配置)的至少第一径向层形成，以形成纳米线2的栅控部分7。介质层5由沿着纳米线2的至少一部分布置在纳米线2周围的至少第二径向层形成，且应当意识到，该栅控部分7和栅电极在原理上分别对应于上述半导体本体和体电极。举例而言，如图2所说明的那样，介质层5完全包围纳米线2且栅电极4完全覆盖介质层5。可选地，绝缘层14包围纳米线2的基底部分以将栅电极4与基板12电学分离。
参考图2，在根据本发明的纳米结构MOS电容器的一个实施例中，栅控部分7的整个纳米线2剖面适于在向栅电极4施加预定电压时完全耗尽。举例而言，本实施例的纳米结构MOS电容器包括具有半径为R或宽度为W(W＝2R)且栅控部分7的长度为L的圆柱形形状的纳米线2。在积累模式，这种圆柱形纳米结构MOS电容器的电容由纳米线2的栅控部分的总表面积2πRL(πWL)决定，而在耗尽模式，电容由纳米线截面积πR2(πR2/4)决定。本发明不限于圆柱形纳米线几何形状，且因此电容决定面积可以以不同于上述等式的方式限定。然而，不管特定几何形状如何，本发明基于由于纳米线技术而具有不同电容决定面积的可能，所述电容决定面积取决于电容器是工作在耗尽模式还是积累模式。
积累模式和耗尽模式由施加到栅电极4的电压的阈值电平决定。如果纳米线2由p型材料制成，则纳米线2的栅控部分7适于在向栅电极4施加高于第一预定阈值电平的电压时完全耗尽。另一方面，如果纳米线2由n型材料制成，则纳米线2的栅控部分7适于在向栅电极4施加低于第二预定阈值电平的电压时完全耗尽。
当从积累模式变化为耗尽模式时，根据本发明的器件面积的改变改善了MOS电容器的调制能力。基本上耗尽电容可以接近零，这是纳米线2几何形状的独特特征，且在如参考图1所述的常规MOS电容器中是不可能的，在图1的常规MOS电容器中，积累电容和耗尽电容二者基本由相同的面积决定，即，有效器件面积基本恒定。
对于根据包括圆柱形纳米线2的本发明的一个实施例的纳米结构MOS电容器，当改变电容决定面积时，如果纳米线2的宽度小于纳米线2的栅控部分7的长度的4倍，则电容减小。优选地，纳米线2的宽度小于0.4L，且甚至更优选地纳米线的宽度小于0.1L。当从积累模式变化为耗尽模式时，宽长比(W/L)的减小引起增加的电容变化。为了实现纳米线2的完全耗尽且提供低耗尽电容，纳米线的宽度或半径应该是小的。优选地纳米线2的半径R小于50μm，优选地小于30μm，且更优选地小于10μm，即，宽度小于100μm，优选地小于60μm，且更优选地小于20μm。
如本领域技术人员所理解的那样，纳米线容易被并行处理且因而可以在公共基板上制作纳米结构MOS电容器阵列。例如，通过并联连接或串联连接阵列的至少一组纳米线组，可以获得纳米结构MOS电容器器件的预定电容。改变电容的另一可能是改变维度，即，纳米线2的长度和厚度，或者改变介质层的成分或厚度。
参考图3，在本发明的一个实施例中，纳米结构MOS电容器包括通过绝缘生长掩膜14中的孔从基板12凸出的半导体纳米线2。在纳米线2的生长期间，生长条件适于在生长掩膜14上提供具有金字塔形状的纳米线2的上部。栅电极4和中间介质层5包围纳米线2的所述上部(即栅控部分)以允许在向栅电极4施加合适电压时形成耗尽区7。
图4a-c说明本发明的纳米结构MOS电容器的一种实施方式。如图4a中的SEM显微照片那样，通过在化学束外延(CBE)系统中的自组装生长获得纳米线阵列，然而，本发明不限于该生长技术。本领域技术人员应当意识到，可以使用(金属-有机化学气相沉积)MOCVD、气液固工艺(VLS)、分子束外延(MBE)等制作纳米线。纳米线的形成通过沉积在掺杂的InAs(111)B基板上的金纳米颗粒引导。为了针对纳米维度研究纳米结构MOS电容器的CV性能，使用各种纳米颗粒尺寸并行建立多个阵列。制作平均纳米线半径为23.0nm、25.0nm、26.5nm、28.5nm和30.0nm的15个标称相同的纳米线阵列的5个不同组。纳米线2首先被共形(conformal)HfO2绝缘，所述共形HfO2通过原子层沉积(在250℃处125个循环)以约10nm的厚度涂敷，以形成至少沿纳米线2的圆周表面的一部分进行包围的介质层5。栅电极4通过溅射具有约20nm的标称厚度的Cr/Au双层形成。厚度约1μm的来自Shipley的S1813的聚合物膜被作为提升(lifting)层15沉积以便增加纳米线的电容与源于例如接触焊盘和基板之间的并联电容的器件的杂散电容的比例。栅控纳米线长度L是平均680nm。单个器件通过UV光刻和30-45μm2的栅极焊盘的金属蚀刻限定。如图4d中所说明的那样，实验已证明：该MOS电容器器件的电容达到背景电容，即没有任何纳米线的裸焊盘的电容，且基本没有耗尽电容。通过在20MHz的频率处对26.5nm纳米线进行-3V至+3V的C(V)扫描获得图4d中的图表的实验结果。
介质层5和栅电极4可以仅包围纳米线2的一部分或者包围其全长。在根据本发明的纳米结构电容器的一个实施例中，纳米线通过绝缘生长掩膜14中的孔凸出。介质层5和栅电极4沿着纳米线2的长度延伸且包围其圆周表面，而保持其端部不被包围以用于电连接。
图5a示意性地说明在图4a-c的纳米结构MOS电容器的纳米线中，使用三个不同载流子密度Nd＝1.0×1018cm-3、Nd＝2.0×1018cm-3和Nd＝4.0×1018cm-3，图4d的C(V)数据集的理论拟合。图5b-d示意性地说明沿着如图5a中所指示的Nd＝2.0×1018cm-3的线的三个不同点B、C、D处的能带弯曲和电子密度。不同点B、C、D分别对应于积累、平带和耗尽条件。理论拟合基于电容的计算，该电容计算基于泊松-薛定谔码，其类似于E.Gnani等人在Solid State Electronics 50，709(2006)和L.Wang等人在Solid-State Electronics 50，1732(2006)中描述的代码。
本发明的一个实施例提供一种包括用于提供可变电容的纳米结构MOS晶体管的电路。
参考图6，根据本发明的压控振荡器装置包括根据本发明的纳米结构MOS电容器。纳米结构MOS电容器包括至少部分被介质层5包围的纳米线2以及包围介质层5的至少一部分的栅电极4。优选地，纳米线2从基板12凸出。压控振荡器装置可以被设计为如图6中的电路图所说明的那样，然而，其他实施方式也是可行的。压控振荡器装置的一个优点在于它包括具有很低耗尽电容的电容器。因而，可以获得增强的频率调制。
参考图7，根据本发明的采样和保持电路装置包括根据本发明的纳米结构MOS电容器。纳米结构MOS电容器包括至少部分被介质层5包围的纳米线2以及包围介质层5的至少一部分的栅电极4。优选地，纳米线2从基板12凸出。该采样和保持电路装置可以以图6的电路图的设计，然而，其他实施方式也是可行的。该采样和保持电路装置的一个优点在于它包括具有很低耗尽电容的电容器。因而，可以增加这种装置的分辨率。
参考图8，一种通过使用根据本发明的纳米结构MOS电容器在电子电路中提供可变电容的方法，该纳米结构MOS电容器包括从基板12凸出的纳米线2、由沿着纳米线2的至少一部分布置在纳米线2周围的至少第二径向层形成的介质层5以及由布置在介质层5的至少一部分周围以形成纳米线2的栅控部分7的第一径向层形成的栅电极4，该方法的特征在于以下步骤：
-101向栅电极4施加第一预定电压以完全耗尽纳米线2的栅控部分7。
该方法优选地还包括向栅电极4施加第二预定电压以建立积累模式的步骤102。通过改变施加于栅电极4的电压，电容可以改变，且在一个实施例中，该方法包括在积累模式和耗尽模式之间变更的步骤103。如上所述，通过适当地确定纳米结构MOS电容器的维度，根据电容器以耗尽模式工作还是以积累模式工作，电容可以由不同电容决定面积限定。
尽管已针对单个纳米线描述了本发明，但应当理解，大量(几个至百万个)纳米线可以共同地以相同的方式用作电容器。
用于纳米结构MOS电容器的基板的合适的材料包括但不限于：Si、GaAs、GaP、GaP:Zn、GaAs、InAs、InP、GaN、Al2O3、SiC、Ge、GaSb、ZnO、InSb、SOI(绝缘体上硅)、GdS、ZnSe、CdTe。用于纳米线的合适材料包括但不限于：IV、III-V、II-VI族半导体，诸如：GaAs、InAs、Ge、ZnO、InN、GaInN、GaN、AlGaInN、BN、InP、InAsP、GaInP、InGaP:Si、InGaP:Zn、GaInAs、AlInP、GaAlInP、GaAlInAsP、GaInSb、InSb以及Si。可能的施主掺杂剂是但不限于Si、Sn、Te、Se、S等，且受主掺杂剂是Zn、Fe、Mg、Be、Cd等。
尽管已在纳米结构MOS电容器方面描述了本发明，但应当意识到，在不同电容决定面积之间切换的上述效果可用于诸如肖特基二极管之类的其他半导体器件。原理上，肖特基二极管起MOS电容器的作用。根据本发明的一个实施例的纳米结构肖特基二极管包括半导体纳米线2或从半导体基板12凸出的半导体纳米线阵列，或者可选地半导体基板12上的缓冲层。纳米线的至少一部分被限定纳米线的栅控部分7的金属接触24包围，由此金属接触24和半导体纳米线2之间的结形成肖特基势垒。金属接触和第一电极21形成两端器件，其中所述第一电极21经由缓冲层和/或基板或者经由包围不被金属接触包围的纳米线的一部分的缠绕接触连接到纳米线。纳米线几何结构使得能够在器件中形成几乎无缺陷的材料和高封装密度。尤其是，可以使用对于肖特基二极管是优选材料的诸如GaN、InGaN、AlGaN、SiC的宽带隙半导体。当与Si二极管相比时，这些材料在击穿电压、较低泄露电流、较高温度稳定性、较快反向恢复时间以及正电阻温度系数方面提供更高的性能。用于金属接触的合适材料是包括以下材料中的一种或更多种：Mg、Hf、Ag、Al、W、Au、Pd或Pt的金属材料。对于如上所述的其他实施例，也可以使用可以是包括GaN、InN、InGaN、InP、GaAs或GaP的III-V族材料的缓冲层。
本领域技术人员应当意识到，介质层5可以包括不同于氧化物的其他材料，尽管术语MOS(金属-氧化物-半导体)指示介质材料应当是氧化物。介质层可以由上文公开的HfO2制成，但是也可以使用诸如Al2O3、ZrO2、Si3N4和Ga2O3之类的其他介质材料。
尽管结合了当前被认为是最实际和优选的实施例描述了本发明，但应当理解，本发明不限于所公开的实施例，相反，它旨在涵盖所附权利要求内的各种修改和等价布置。

Claims (14)

1.一种纳米结构MOS电容器，其特征在于，该MOS电容器包括从基板(12)凸出的纳米线(2)，以及由第一径向层形成的栅电极(4)，该第一径向层布置在该纳米线(2)的至少一部分周围以形成该纳米线(2)的栅控部分(7)。
2.根据权利要求1所述的纳米结构MOS电容器，还包括由沿该纳米线(2)的至少一部分布置在该纳米线(2)周围的至少第二径向层形成的介质层(5)。
3.根据权利要求1或2所述的纳米结构MOS电容器，其中该纳米线(2)的栅控部分(7)适于在向该栅电极(4)施加第一预定电压时完全耗尽。
4.根据权利要求3所述的纳米结构MOS电容器，其中该纳米线(2)的栅控部分(7)具有长度L和宽度W，且宽度W小于4L，优选地小于0.4L，且更优选地小于0.1L。
5.根据权利要求3或4所述的纳米结构MOS电容器，其中处于积累模式和耗尽模式的MOS电容器分别具有与WL和W2成比例的电容。
6.根据权利要求4或5所述的纳米结构MOS电容器，其中W小于100μm，优选地小于60μm，且更优选地小于20μm。
7.根据权利要求1所述的纳米结构MOS电容器，其中该栅电极是金属接触(24)且该金属接触和该纳米线(2)形成肖特基势垒。
8.一种用于提供可变电容的电路，其包括根据权利要求1至6中任一项所述的纳米结构MOS电容器。
9.一种压控振荡器装置，其特征在于其包括根据权利要求1至6中任一项所述的纳米结构MOS电容器。
10.一种采样和保持电路装置，其特征在于其包括根据权利要求1至6中任一项所述的纳米结构MOS电容器。
11.一种通过使用纳米结构MOS电容器在电子电路中提供可变电容的方法，该纳米结构MOS电容器包括：
纳米线(2)，其从基板(12)凸出；
介质层(5)，其由沿该纳米线(2)的至少一部分布置在该纳米线(2)周围的至少第二径向层形成；以及
栅电极(4)，其由布置在该介质层(5)的至少一部分周围的第一径向层形成，从而限定该纳米线(2)的栅控部分(7)；该方法的特征在于向该栅电极(4)施加第一预定电压以完全耗尽该纳米线(2)的栅控部分(7)的步骤(101)。
12.根据权利要求11所述的方法，还包括向该栅电极(4)施加第二预定电压以建立积累模式的步骤(102)。
13.根据权利要求12所述的方法，还包括在积累模式和耗尽模式之间变更的步骤(103)，其中根据该电容器是工作在耗尽模式还是积累模式，电容由不同电容决定面积限定。
14.根据权利要求12所述的方法，其中，该纳米线(2)的栅控部分(7)具有长度L和宽度W，且积累模式和耗尽模式中的纳米结构MOS电容器分别具有与WL和W2成比例的电容。
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US20110089477A1 (en) 2011-04-21
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