CN102074545A - 集成电路元件、半导体元件以及半导体工艺 - Google Patents
集成电路元件、半导体元件以及半导体工艺 Download PDFInfo
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Abstract
本发明一实施例提供一种集成电路元件,包括一半导体基板,具有一正面与一背面,且一集成电路组件形成于正面上;一层间介电层,形成于半导体基板的正面上;一接触插塞,形成于层间介电层中并电性连接集成电路组件;以及一导孔结构,形成于层间介电层中并延伸穿过半导体基板,其中导孔结构包括一金属层、围绕金属层的一金属籽晶层、围绕金属籽晶层的一阻障层、以及位于金属层与金属籽晶层之间的一阻挡层,阻挡层包括镁、铁、钴、镍、钛、铬、钽、钨或镉的至少其中之一。本发明可大幅减少镀铜以及后续的研磨工艺所耗费的时间,进而减少三维堆叠的集成电路的制作成本。
Description
技术领域
本发明涉及堆叠式集成电路(stacked integrated circuit),且特别涉及应用在三维堆叠技术(three-dimensional stacking technology)的硅穿孔结构及其制作方法。
背景技术
三维的晶片对晶片、芯片对晶片、或是芯片对芯片的垂直堆叠技术的目标是垂直堆叠多层有源元件,例如处理器(processor)、可编程元件(programmable device)以及存储器元件,以缩短平均导线长度(average wire length),进而减少内连线的RC延迟(RC delay)以及增加系统效能。在单一晶片上或是在芯片对晶片的垂直堆叠结构中的三维内连线所面临的主要挑战是穿硅导孔(through-silicon via,TSV),其提供高阻抗信号(high impedance signal)一信号路径,以使其自晶片的一侧横越晶片而到达晶片的另一侧。穿硅导孔通常填满导电材料且完全贯穿层状结构以接触并连接接合层的其他的穿硅导孔以及导体。一般而言,因为铜的电阻低于大部分常用的金属的电阻且具有较高的载流量(current carrying capacity),因此,铜已成为作为穿硅导孔金属化的金属选项。这些特性对于在高度集成化且高元件速度的情况下提高电流密度是相当重要的。再者,铜的导热性佳且纯度高。制作穿硅导孔是用于三维堆叠技术的其中一种主要技术。因此,业界致力于形成无孔洞的结构(void-free feature)。以前会以铜电镀工艺填满具有高深宽比(aspect ratio)的穿硅导孔(深宽比大于3∶1),然后进行移除材料的工艺(例如化学机械研磨工艺),以平坦化并从晶片的顶面移除额外的金属或是过度沉积层(overburden),且仅留下在穿硅导孔中的导电材料。沉积在晶片的顶面或是晶片表面的场区(field region)上的某些过度沉积层将使化学机械研磨工艺的时间拉长。再者,铜电镀工艺常会制作出导电插塞(conductive plug)具有缺陷(例如孔洞或是裂缝)的穿硅导孔。在制作电子元件的过程中,孔洞或是裂缝可能会导致一连串的问题。
发明内容
为克服现有技术中的缺陷,本发明一实施例提供一种集成电路元件,包括一半导体基板,具有一正面与一背面,且一集成电路组件形成于正面上;一层间介电层,形成于半导体基板的正面上;一接触插塞,形成于层间介电层中并电性连接集成电路组件;以及一导孔结构,形成于层间介电层中并延伸穿过半导体基板,其中导孔结构包括一金属层、围绕金属层的一金属籽晶层、围绕金属籽晶层的一阻障层、以及位于金属层与金属籽晶层之间的一阻挡层,阻挡层包括镁、铁、钴、镍、钛、铬、钽、钨或镉的至少其中之一。
本发明一实施例提供一种半导体元件,包括一半导体基板,具有一正面与一背面,且一集成电路组件形成于正面上;一层间介电层,形成于半导体基板的正面上;一接触插塞,形成于层间介电层中并电性连接集成电路组件;以及一导孔结构,形成于层间介电层中并延伸穿过半导体基板,其中导孔结构包括一铜层、围绕铜层的一铜籽晶层、围绕铜籽晶层的一阻障层、以及位于铜层与铜籽晶层之间的一锰层,导孔结构包括一暴露于半导体基板的背面的端部。
本发明一实施例提供一种半导体工艺,包括提供一半导体基板,其具有一正面与一背面;形成一由半导体基板的正面延伸入至少部分半导体基板中的开口,其中开口的深宽比大于;于开口中形成一金属籽晶层,其中金属籽晶层包括相邻于开口的侧壁的一侧壁部分以及相邻于开口的底部的一底部部分;于至少部分的金属籽晶层的侧壁部分上形成一阻挡层;以及于阻挡层与金属籽晶层上镀一金属层,以填满开口,其中阻挡层包括镁、铁、钴、镍、钛、铬、钽、钨或镉的至少其中之一。
本发明可大幅减少镀铜以及后续的研磨工艺所耗费的时间,进而减少三维堆叠的集成电路的制作成本。
附图说明
图1至图7示出本发明一实施例的穿硅导孔工艺的剖面图。
图8至图10示出本发明一实施例的使用穿硅导孔结构的三维堆叠工艺的剖面图。
其中,附图标记说明如下:
10~基板、半导体基板;
10a~正面;
10b~背面;
10”~薄化基板;
10b”~背面;
12~介电层、层间介电层;
14~接触插塞;
16~硬掩模层;
18~开口、穿硅导孔开口;
18a~侧壁;
18b~底部;
20~保护层;
22~阻障层;
24~金属籽晶层、铜籽晶层;
24a~侧壁部分;
24b~底部、底部部分;
24c~表面部分;
26~阻挡层;
26a~电镀液;
32~金属层;
34~穿硅导孔结构;
34b~底端;
36~金属间介电层;
38~接合接点;
40~背侧介电层;
42~接垫;
44~外部接点;
46~连接元件
100~晶片;
200~集成电路组件;
300~外部芯片、外部晶片。
具体实施方式
为使本发明的上述目的、特征和优点能更明显易懂,下文特举一较佳实施例,并配合附图,作详细说明如下。
下述多个实施例将提供金属化工艺以填满高深宽比的开口以及使用前述工艺所制作出的结构。“深宽比”一词描述形成于材料层中的任一开口的高度对宽度的比例。在本说明书中,“高深宽比”一词是指开口的高度对宽度的比值大于5。金属化工艺的多个实施例亦可用于形成穿硅导孔结构。在本说明书中,“穿硅导孔”一词是指一填满导电材料且贯穿至少部分的半导体基板或是含硅基板的开口。多个实施例是用铜金属化工艺形成穿硅导孔,并且使用铜电镀技术来填满高深宽比的开口以避免产生裂缝或是孔洞缺陷。在本说明书中,铜包括铜元素以及实质上表现出铜的电性的铜基合金(Cu-based alloy)。
现在将详细描述本发明的多个实施例,且将伴随着图式介绍这些实施例。在本说明书中,用于图式与描述中的相同元件符号指相同或是相似的元件。在图式中,为了清楚与方便表示起见,可能会夸大实施例中的形状与厚度。本描述将特别针对形成本发明的装置的部分的元素。可以了解的是,并未被特别显示或是描述的这些元素可以本领域技术人员所知的多种形式呈现。再者,当描述一膜层是位于另一膜层或是一基板“上”时,可以是指该膜层直接位于另一膜层或是基板上,或者是指该膜层与另一膜层或是基板之间夹有中介膜层。
在此,图1至图7示出本发明一实施例的穿硅导孔工艺的剖面图,且图8至图10示出本发明一实施例的使用穿硅导孔结构的三维堆叠工艺的剖面图。
请参照图1,其示出一晶片100的剖面图,晶片100包括一半导体基板10、一由半导体基板10加工而成的集成电路组件200、一位于半导体基板10上的层间介电层(inter-layer dielectric,ILD)12以及一形成于层间介电层12中且与集成电路组件200电性连接的接触插塞(contact plug)14。详细而言,基板10为一般的硅,举例来说,基板10为一具有或没有外延层的硅基板,或是一含有内埋绝缘层的硅覆绝缘型基底(silicon-on-insulator substrate)。基板10具有一正面10a(例如电路侧)以及一背面10b(例如无电路侧)。形成于基板10的正面10a之内及/或之上的集成电路组件200可包括多种独立的电路元件,例如晶体管、二极管、电阻、电容、电感、以及可以集成电路制造领域中常见的工艺所制得的其他有源与无源半导体元件。将层间介电层12形成于基板10上,以隔离集成电路组件200与后续形成的内连线结构。层间介电层12可为一单层或是一多层结构。层间介电层12可为一掺杂了或是未掺杂硅氧化物的含硅氧化物层,且可以热化学气相沉积工艺或是高密度等离子体(high-density plasma,HDP)工艺形成,层间介电层12例如为未掺杂的硅酸盐玻璃(undoped silicate glass,USG)、掺杂磷的硅酸盐玻璃(phosphorous doped silicate glass,PSG)或是硼磷硅玻璃(borophosphosilicate glass,BPSG)。或者是,层间介电层12可以是由掺杂的或是P型掺杂的旋涂式玻璃(spin-on-glass,SOG)、掺磷四乙烯正硅酸(PTEOS)、或是掺硼磷四乙烯正硅酸(BPTEOS)所构成。在进行了干式蚀刻工艺之后,于层间介电层12中形成一接触孔,并在接触孔中沉积导电材料层,以填满接触孔并形成一接触插塞14。接触插塞14可包括钨、含钨合金、铜、含铜合金或前述的组合。
请参照图2,在基板10中形成一高深宽比(大于5)的开口18。在一形成穿硅导孔结构的实施例中,开口18为一穿硅导孔开口,且可于穿硅导孔开口中进行金属化工艺。为了定义出穿硅导孔开口18,可在层间介电层12上形成一硬掩模层(hard mask layer)16,之后,在硬掩模层16上形成一图案化光致抗蚀剂层。硬掩模层16可为氮化硅层、氮氧化硅层或其相似物。以曝光、烘烤、显影及/或其他本领域所知的光刻工艺来图案化光致抗蚀剂层(未示出)以形成一暴露出硬掩模层16的开口。然后,以图案化光致抗蚀剂层为掩模(以湿式或干式蚀刻工艺)蚀刻暴露出的硬掩模层16以形成一开口。利用硬掩模层16以及图案化光致抗蚀剂层为掩模,进行蚀刻工艺以蚀刻外露的基板10,从而形成具有侧壁18a与底部18b的穿硅导孔开口18。穿硅导孔开口18贯穿至少部分的半导体基板10。穿硅导孔开口18可以是以任何适合的蚀刻方法所蚀刻而成的,例如包括等离子体蚀刻、化学湿式蚀刻、激光钻孔、及/或其他本领域所知的制作方法。在一实施例中,蚀刻工艺包括深式反应离子蚀刻(deep reactive ion etching,RIE)工艺以蚀刻半导体基板10。可进行蚀刻工艺,以由正面10a蚀刻出穿硅导孔开口18,其蚀刻深度约达数十微米至数百微米且未贯穿背面10b。蚀刻工艺可形成一具有垂直的侧壁轮廓或是倾斜的侧壁轮廓的开口。在一实施例中,穿硅导孔开口18的深度约为20~100微米且其直径约为1.5~10微米。穿硅导孔开口18具有高深宽比,其约介于5与10之间。在某些实施例中,穿硅导孔开口18的深宽比大于10。
在图3中,在前述结构上共形地沉积一保护层(passivation layer)20,以覆盖硬掩模层16以及穿硅导孔开口18的侧壁18a与底部18b,以避免任何导电材料进入晶片100的电路的任一有源部分中。保护层20可以是由氧化硅、四乙烯正硅酸氧化物、氮化硅、前述的组合或其相似物所构成的。可利用多种技术,包括热氧化法(thermal oxidation)、低压化学气相沉积(low-pressure chemical vapor deposition,LPCVD)、大气压化学气相沉积(atmospheric-pressure chemical vapor deposition,APCVD)、等离子体辅助化学气相沉积(plasma-enhanced chemical vapor deposition,PECVD)以及将来研发出的沉积方法,中的任一技术来进行沉积工艺。举例来说,可利用使用四乙烯正硅酸以及臭氧(O3)的低压化学气相沉积工艺或等离子体辅助化学气相沉积工艺来形成四乙烯正硅酸氧化物薄膜。
在图4中,在保护层20上形成一阻障层22,其与穿硅导孔开口18共形。阻障层22是作为一防止金属扩散的扩散阻障层以及作为一金属与介电层之间的粘着层。通常可用耐火金属、耐火金属氮化物(metal-nitrides)、耐火金属-硅-氮化物(metal-silicon-nitrides)以及前述的组合来构成阻障层22。举例来说,可使用氮化钽(TaN)、钽(Ta)、钛(Ti)、氮化钛(TiN)、氮硅化钛(TiSiN)、氮化钨(WN)或前述的组合。在一实施例中,阻障层22包括氮化钽层以及钽层。在另一实施例中,阻障层22为氮化钛层。在另一实施例中,阻障层22为钛层。然后,在阻障层22上形成一金属籽晶层(metal seed layer)24。在一实施例中,金属籽晶层为一铜籽晶层24,其可以物理气相沉积的方式形成的。形成铜籽晶层24的其他方法,例如为本领域所知的化学气相沉积。
请参照图5,在金属籽晶层24的一部分上形成一阻挡层(block layer)26。阻挡层26为一金属层或是一合金层,其包括镁、铁、钴、镍、钛、铬、钽、钨、镉、或前述的组合,且其可以电镀工艺或是物理气相沉积工艺形成。举例来说,阻挡层26可为锰层、含锰层、或是锰基层(例如是由锰所构成的)、或是其他适合的成分。阻挡层26的厚度可以是小于10埃(Angstrom)。在一实施例中,沉积一铜籽晶层24,以形成相邻于穿硅导孔开口18的侧壁18a的多个侧壁部分24a、相邻于穿硅导孔开口18的底部18b的一底部部分24b以及位于穿硅导孔开口18外的一表面部分24c。在表面部分24c以及至少部分的侧壁部分24a上形成阻挡层26。通过控制操作条件,可选择性地将阻挡层26形成在金属籽晶层24的侧壁部分24a及/或表面部分24c上,而不形成在金属籽晶层24的底部部分24b上。图5A示出使用电镀工艺形成一阻挡层26的实施例,其翻覆晶片100以使基板10的正面10a朝向下并位于电镀液(electroplating bath)26a中,从而将空气滞留在底部部分24b。第5B图示出使用电镀工艺形成一阻挡层26的另一实施例,其电镀液26a中不含添加剂以使场沉积速度(field deposition rate)远高于底部沉积速度(bottom deposition rate)。当沉积阻挡层26时,电解质可流入导孔底部,但薄金属籽晶层的位于导孔底部的部分具有较高的电阻。通过控制操作条件,可使阻挡层26不形成在底部24b上。图5C示出使用物理气相沉积法形成一阻挡层26的另一实施例,其使等离子体具有30°的倾斜角(tilted pitch-angle),以使阻挡层26不形成在底部24b上。
请参照图6,将晶片100传送到一镀膜机台(例如电化学电镀的机台,electrochemical plating(ECP)tool),并且通过进行镀膜工艺以于晶片100上镀一金属层32从而填满穿硅导孔开口18。虽然在此是描述电化学电镀工艺,但本实施例并不限于以电化学电镀工艺来沉积金属。金属层32可包括低电阻的导体材料,其可选自于包括,但不限于,铜及铜基合金的多种导电材料所组成的群组。或者是,金属层可包括多种材料,例如钨、铝、金、银及其相似物。在一实施例中,金属层32为一形成于铜籽晶层24上的含铜层,且阻挡层26位于金属层32与铜籽晶层24之间。由于阻挡层26形成在侧壁部分24a上而不形成在底部部分24b上,因此,铜电镀工艺可加快沉积速度并从(穿硅导孔开口18的)底部向上填满穿硅导孔开口18,以形成一无孔洞的金属化结构(void-free metallization structure)。上述内容提供了一个可靠且高产量的方法以填满高深宽比的开口。因此,可大幅减少镀铜以及后续的研磨工艺所耗费的时间,进而减少三维堆叠的集成电路的制作成本。
接着,如图7所示,通过蚀刻、化学机械研磨或是类似的方法移除金属层32、阻挡层26、金属籽晶层24、阻障层22、保护层20及/或硬掩模层16的位于穿硅导孔开口18外的多余部分,以形成金属-场开口的上表面,其实质上共平面于介电层12的上表面。现在,晶片100包括一穿硅导孔结构34,穿硅导孔结构34形成于层间介电层12中并延伸入部分的基板10中。穿硅导孔结构34包括金属层32、围绕金属层32的金属籽晶层24、围绕金属籽晶层24的阻障层22、围绕阻障层22的保护层20以及位于部分的金属籽晶层24与金属层32之间的阻挡层26。
然后,如图8所示,以后段工艺(back-end-of-line,BEOL)内连线技术在晶片100上制作一内连线结构,其包括多层内连线层、多层重分布层(redistribution layer)、多层金属间介电层(inter-metal dielectric layer,IMD layer)36以及多个接合接点38。在一实施例中,在一金属间介电层中形成一第一层内连线层以分别电性连接接触插塞14以及穿硅导孔结构34,之后,在第一层内连线层上制作其他层的内连线层以及金属间介电层,且为清楚与方便说明起见,在图8中省略示出其他层的内连线层以及金属间介电层。在一顶层内连线层以及一顶层金属间介电层上形成多个接合接点38。以铜基导电材料形成内连线层以及接合接点38。铜基导电材料包括实质上纯的元素铜、含有无可避免的杂质的铜、以及含有少量元素的铜合金,前述少量元素例如为钽、铟、锡、锌、锰、铬、钛、锗、锶、铂、镁、铝或是锆。铜的后段内连线工艺可使用标准的镶嵌工艺(damascene process)。
之后,请参照图9,对晶片100进行晶片薄化工艺(wafer thinning process)以及背侧金属化工艺(backside metallization process)。在一实施例中,将晶片100贴附到一载体(carrier)上,然后,加工基板10的背面10b以使基板10具有要求的最终厚度,以暴露出穿硅导孔结构34的底端34b。可例如以研磨(grinding)、蚀刻及/或抛光(polishing)的方式形成薄化基板10”,其可视半导体封装的使用目的而具有适当的厚度。薄化基板10”的厚度可约为5微米至180微米。在一实施例中,在晶片薄化之后,穿硅导孔结构34的底部34b暴露于及/或突出于薄化基板10”的背面10b”。将包括电连接结构及/或其他的结构的背侧金属化结构形成于薄化基板10”的背面10b”上,背侧金属化结构包括背侧介电层40以及用以连接外部的芯片或是晶片的接垫42。在图10中,将一外部的芯片或晶片300接合到晶片100上,其中接合方法包括常用的方法,例如氧化物对氧化物接合(oxide-to-oxide bonding)、氧化物对硅接合(oxide-to-silicon bonding)、铜对铜接合(copper-to-copper bonding)、铜对焊料接合(copper-to-solder bonding)、粘着接合(adhesive bonding)或前述的组合。在一实施例中,个别的半导体芯片的外部接点44可分别形成在薄化基板10”的背面10b”上的接垫42上,以接合至电子端(electrical terminal)。外部接点44可为焊料凸块、含铜凸块或是前述的组合。可提供多个连接元件46,以将外部芯片300接合至晶片100上而形成一芯片对晶片的堆叠结构(dies-to-wafer stack)。连接元件可以是焊料凸块、含铜凸块或是前述的组合。在切割工艺(dicing)之后,使堆叠的芯片或是多个芯片经由例如各向异性的导电连接膜而安装在集成电路卡(IC card)上。
本发明虽以较佳实施例揭露如上,然其并非用以限定本发明的范围,任何所属技术领域中的技术人员,在不脱离本发明的精神和范围内,当可做些许的更动与润饰,因此本发明的保护范围当视随附的权利要求所界定的保护范围为准。
Claims (11)
1.一种集成电路元件,包括:
一半导体基板,具有一正面与一背面,且一集成电路组件形成于该正面上;
一层间介电层,形成于该半导体基板的该正面上;
一接触插塞,形成于该层间介电层中并电性连接该集成电路组件;以及
一导孔结构,形成于该层间介电层中并延伸穿过该半导体基板,其中该导孔结构包括一金属层、围绕该金属层的一金属籽晶层、围绕该金属籽晶层的一阻障层、以及位于该金属层与该金属籽晶层之间的一阻挡层,该阻挡层包括镁、铁、钴、镍、钛、铬、钽、钨或镉的至少其中之一。
2.如权利要求1所述的集成电路元件,其中该金属籽晶层包括一底部部分,该底部部分相邻于该半导体基板的该背面,且该金属籽晶层的该底部部分并未覆盖有该阻挡层。
3.如权利要求1所述的集成电路元件,其中该金属层包括铜,且该金属籽晶层包括铜,其中该阻障层包括氮化钽、钽、氮化钛或钛的至少其中之一。
4.如权利要求1所述的集成电路元件,其中该导孔结构还包括一围绕该阻障层的保护层。
5.如权利要求1所述的集成电路元件,其中该导孔结构包括一暴露于该半导体基板的该背面的端部。
6.如权利要求1所述的集成电路元件,还包括:
一半导体组件,堆叠于该半导体基板的该背面上,并电性连接该导孔结构。
7.一种半导体工艺,包括:
提供一半导体基板,其具有一正面与一背面;
形成一由该半导体基板的该正面延伸入至少部分该半导体基板中的开口,其中该开口的深宽比大于5;
于该开口中形成一金属籽晶层,其中该金属籽晶层包括相邻于该开口的侧壁的一侧壁部分以及相邻于该开口的底部的一底部部分;
于至少部分的该金属籽晶层的该侧壁部分上形成一阻挡层;以及
于该阻挡层与该金属籽晶层上镀一金属层,以填满该开口,其中该阻挡层包括镁、铁、钴、镍、钛、铬、钽、钨或镉的至少其中之一。
8.如权利要求7所述的半导体工艺,其中该阻挡层并未形成在该金属籽晶层的该底部部分上。
9.如权利要求7所述的半导体工艺,还包括:
在形成该金属籽晶层之前,形成一共形地覆盖该开口的阻障层。
10.如权利要求9所述的半导体工艺,还包括:
在形成该阻障层之前,形成一共形地覆盖该开口的保护层。
11.如权利要求7所述的半导体工艺,还包括:
于该半导体基板的该背面上进行一薄化工艺以暴露出该金属层。
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US8405201B2 (en) | 2013-03-26 |
US20110108986A1 (en) | 2011-05-12 |
TWI544597B (zh) | 2016-08-01 |
US8791011B2 (en) | 2014-07-29 |
TW201119001A (en) | 2011-06-01 |
US20130171772A1 (en) | 2013-07-04 |
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