CN102044622B - 发光二极管及其制作方法 - Google Patents

发光二极管及其制作方法 Download PDF

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CN102044622B
CN102044622B CN201010280571.7A CN201010280571A CN102044622B CN 102044622 B CN102044622 B CN 102044622B CN 201010280571 A CN201010280571 A CN 201010280571A CN 102044622 B CN102044622 B CN 102044622B
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emitting diode
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CN102044622A (zh
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郑子淇
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Epistar Corp
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Intematix Technology Center Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50Wavelength conversion elements
    • H01L33/505Wavelength conversion elements characterised by the shape, e.g. plate or foil
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64Heat extraction or cooling elements

Abstract

本发明揭露一种发光二极管及其制作方法,特别是提供一种具有透光性的围栏以增进荧光材料涂布均匀性的方法,进而达到提高白光发光二极管色温的均匀性及其发光效率。包括步骤:提供一支架;固置至少一发光二极管芯片于该支架之上;形成至少一具有透光性的围栏框住该发光二极管芯片;以及提供具有至少含有一荧光材料的混合树脂,形成于该围栏所包围的区域内。本发明的制作方法也具有广泛地应用于各型式的发光二极管芯片的封装及大量生产的功效。

Description

发光二极管及其制作方法
技术领域
本发明涉及一种发光二极管及其制作方法,特别涉及一种增进白光发光二极管装置的色温均匀性及其发光效率的发光二极管及其制造方法。
背景技术
请参阅图1,其是为美国专利第US5998925号所揭示的白光发光二极管的示意图。该白光发光二极管1至少包含一支架11、一发出第一波长光的氮化镓发光二极管芯片12以及一荧光材料13。该荧光材料13吸收部分该氮化镓系发光二极管芯片12所发出的能量而转换发出第二波长的光,因此获得由第一波长及第二波长所混合出的白光。图中,该荧光材料13是与第一树脂相混合后而形成一含有荧光材料13的混合树脂14,再将该混合树脂14充填于承载该氮化镓系发光二极管芯片12的支架11碗杯之内并完全地覆盖该氮化镓系发光二极管芯片12,接着,以第二树脂15将该支架11、氮化镓系发光二极管芯片12以及混合树脂14封盖而完成该白光发光二极管的制作。由于该混合树脂14的厚度是不经由刻意地控制而充填于该支架的碗杯之内,故荧光材料的分布极易造成不均匀的现象,故造成各方向的发光亮度及色温的特性不均匀,有其缺点存在。
针对上述美国专利第US5998925号的缺点,美国专利第US5959316号曾揭示一种白光发光二极管装置,该装置的结构示意图,请参阅图2。该结构是将一发光二极管芯片22放置于一支架21之上,接着,再以第一透明封装树脂23封盖于该发光二极管芯片22的上方,并提供一荧光材料与另一第二透明封装树脂相混合所产生的混合树脂24,再将该混合树脂24封盖于该第一透明封装树脂23之上,接续,再将另一第三透明封装树脂25封盖于该混合树脂24之上。由于该第一透明封装树脂23是经由烤干而形成圆顶状,故含有荧光材料的混合树脂24以特定的厚度涂布于该圆顶状之上,如此可解决发光装置色温的角分布不均匀的缺点。然而,该专利所揭示的技术内容,是分别制作第一透明封装树脂23、混合树脂24以及第三透明封装树脂25之后再分别进行封盖的步骤,由于封盖工艺过程中必须分别地将各树脂以高温烤干,由于此分段制作的过程极容易造成树脂表面污染以及各树脂之间附着力不足的缺点,因此无法提高工艺的良率,而且,增加工艺步骤的复杂性,故仍有其缺点。
又,请参阅图3,其是为美国专利第US6576488号的发光组件示意图。该专利揭示一种覆晶封装型式的方法且提供一种选择性电泳(electrophoresis)沉积荧光材料的技术以提高荧光材料包覆发光二极管芯片的均匀性进而解决色温角分布不均的缺点。首先,将制作完成的发光二极管芯片32以覆晶工艺方法将该发光二极管芯片32固定于一覆晶基板31之上,接着,提供一承载具有形成荧光材料33的电泳装置34,施以特定的电压使得该荧光材料33沉积于该发光二极管芯片32的暴露面,由于形成厚度均匀的荧光材料33,故能有效地提升色温角分布的均匀性。然而,该工艺虽然可以提高色温角分布的均匀性,但使用选择性电泳沉积法工艺,必须于发光二极管芯片32及覆晶基板31之上,制作多种遮蔽掩膜以防止荧光材料沉积于金属导电区域之上,故增加了芯片工艺的复杂性及其制作成本。
另,请参阅图4,其是为美国公开专利第US20050244993号曾揭示的另一种制作具有均匀涂布荧光材料的白光发光组件示意图。首先,提供一种具有垂直电极结构的发光二极管芯片42固定于一基板41之上,接着,提供一荧光材料与另一悬浮溶液(suspension)相混合,再将该混合溶液以喷洒(spray)的方法于该发光二极管芯片42的周围,如此可形成厚度均匀的荧光材料涂布层43以有效提升色温角分布的均匀性。
另,请参阅图5,其是为美国专利第US7217583号曾揭示的另一种制作具有均匀涂布荧光材料的白光发光组件示意图。首先,提供一发光二极管芯片52固定于一基板51之上,接着,提供一混合荧光材料与悬浮溶液(suspension)的混合溶液53于该发光二极管芯片52之上,接续,局限(confine)该混合溶液53及控制该混合溶液53的蒸发(evaporation)程序,如此可形成厚度均匀的荧光材料涂布层54于该发光二极管芯片52的周围,以有效提升色温角分布的均匀性。
发明内容
有鉴于上述现有技术的问题,本发明的其中一目的就是在于提供一种发光二极管及其制作方法,以解决荧光材料涂布不均匀所造成的色温角分布不均匀的缺点。
根据本发明的另一目的,提出一种发光二极管的制作方法,其步骤包含:提供一支架;固置至少一发光二极管芯片于该支架之上;连结该发光二极管芯片及该支架的电气;形成一具有透光性的围栏框住该发光二极管芯片;以及于该围栏所包围具有该发光二极管芯片的区域,涂布一具有荧光材料的封装树脂。
根据本发明的再一目的,提出一种白光发光二极管的制作方法,特别是一种具有透光性的围栏框住发光二极管芯片的封装方法以解决荧光材料涂布不均匀所造成的色温角分布不均匀的缺点并增加发光二极管装置的发光效率。
根据本发明的又一目的,提出一种白光发光二极管的制作方法,特别是一种具有透光性的围栏框住发光二极管芯片的封装方法以简化制作程序以及降低成本。
根据本发明的更一目的,提出一种白光发光二极管,其包含支架、发光二极管芯片、具有透光性围栏及具有至少含有荧光材料的混合树脂。发光二极管芯片固置于支架上。具有透光性的围栏框住发光二极管芯片。具有至少含有荧光材料的混合树脂形成于围栏所包围的区域内。
承上所述,依本发明的发光二极管及其制作方法,其可具有一或多个下述优点:
(1)此发光二极管及其制作方法,是以透光性的围栏框住发光二极管芯片,借此提高荧光材料涂布的均匀性以及提高发光二极管装置的发光效率。
(2)此发光二极管及其制作方法,是以透光性的围栏框住发光二极管芯片,简化均匀涂布荧光材料的程序以及降低制作成本。
以下结合附图和具体实施例对本发明进行详细描述,但不作为对本发明的限定。
附图说明
图1为现有的白光发光二极管结构示意图;
图2为现有的另一白光发光二极管结构示意图;
图3为现有的另一发光组件结构示意图;
图4为现有的另一白光发光二极管结构示意图;
图5为现有的另一白光发光二极管结构示意图;
图6为本发明的发光二极管结构示意图;
图7A~图7C为本发明的发光二极管的制作步骤示意图;以及
图8为本发明的另一发光二极管结构示意图。
其中,附图标记
1:白光发光二极管;
11:支架;
12:氮化镓系发光二极管芯片;
13:荧光材料;
14:混合树脂;
15:第二树脂;
21:支架;
22:发光二极管芯片;
23:第一透明封装树脂;
24:混合树脂;
25:第三透明封装树脂;
31:覆晶基板;
32:发光二极管芯片;
33:荧光材料;
34:电泳装置;
41:基板;
42:发光二极管芯片;
43:荧光材料涂布层;
51:基板;
52:发光二极管芯片;
53:混合溶液;
54:荧光材料涂布层;
61、81:支架;
62、82:发光二极管芯片;
64、84:混合树脂;
63、83:围栏;
65:固晶区域;
66:正电极;
67:负电极;
68:电气连结的线路;
69:衬垫;
70:电极端子;
71:金属导线;以及
100:空间。
具体实施方式
为了对本发明的制作流程及所达到的功效有进一步的了解与认识,仅以较佳的实施例及配合详细说明,说明如下:
首先,请参阅图5,其是为本发明的发光二极管的实施例结构的示意图。其制作过程为:提供一支架61,固置一发光二极管芯片62于该支架61之上,形成一围栏(enclosure)63包围该发光二极管芯片62以及提供至少一含有荧光材料的混合树脂64于该围栏(enclosure)63之内并覆盖于该发光二极管芯片62之上。其中,该支架61的组成材质可为陶瓷系列(Ceramic based)、氧化铝(AlO-based)、铜、铝、钼、钨、氮化铝(AlN-based)或上述所组成的复合材质其中之一。支架61还包含一固晶区域65及电气连结的线路68及衬垫69以及电极端子70。另外,该固晶区域65可以为一导体或非导体之一或其混合的材质。该发光二极管芯片62与该围栏(enclosure)63具一相对距离,并可依据该发光二极管芯片62及该支架61的尺寸大小调整其最佳距离。然而,该围栏(enclosure)63为具有透光性的材料,并且依据该发光二极管芯片62及该支架61的尺寸大小调整位于该发光二极管芯片62之上的该混合树脂64的特定厚度。其中,该混合树脂64的特定厚度不小于该发光二极管芯片62的边缘与该围栏(enclosure)63的相对距离,且是使用选自溅镀法、化学气相沉积法、喷印涂布法、网印涂布法、真空蒸镀法、溶胶-凝胶法以及点胶法其中之一方法或其组合方法将该混合树脂64形成于该围栏所包围的区域内。而该混合树脂64中的荧光材料材质可为Sr1-x-yBaxCaySiO4:Eu2+F、(Sr1-x-yEuxMny)P2+zO7:Eu2+F、(Ba,Sr,Ca)Al2O4:Eu、((Ba,Sr,Ca)(Mg,Zn))Si2O7:Eu、SrGa2S4:Eu、((Ba,Sr,Ca)1-xEux)(Mg,Zn)1-xMnx))Al10O17、Ca8Mg(SiO4)4Cl2:Eu,Mn、((Ba,Sr,Ca,Mg)1-xEux)2SiO4、Ca2MgSi2O7:Cl、SrSi3O8·2SrCl2:Eu、BAM:Eu、Sr-Aluminate:Eu、Thiogallate:Eu、Chlorosilicate:Eu、Borate:Ce,Tb、Sr4Al14O25:Eu、YBO3:Ce,Tb、BaMgAl10O17:Eu,Mn、(Sr,Ca,Ba)(Al,Ga)2S4:Eu、Ca2MgSi2O7:Cl,Eu,Mn、(Sr,Ca,Ba,Mg)10(PO4)6Cl2:Eu ZnS:Cu,Al、(Y,Gd,Tb,Lu,Yb)(AlyGa1-y)5O12:Ce、(Sr1-x-y-zBaxCayEuz)2SiO4、(Sr1-a-bCabBac)SixNyOz:Eua以及Sr5(PO4)3Cl:Eua的其中之一或上述所组成的混合材质。为了使本发明所欲达到的功效有更进一步的了解与认识,本发明的制作流程详述如下:请参阅图7A,首先,将发光二极管芯片62固置于该支架61的固晶区域65之上,接着,以金属导线71连接该发光二极管芯片62的正电极66与负电极67于该支架上的衬垫69。请参阅图7B,接续连接金属导线71步骤之后,提供一具有透光性的围栏(enclosure)63,将该发光二极管芯片62框住以形成一空间100。接着,将至少含有一荧光材料的混合树脂64注满该空间100而完成兼具色温及亮度角分布均匀的白光发光二极管。接续以上的步骤,请参阅图7C,也可加入平坦化该混合树脂64表面的步骤。除此之外,也可将上述表面平坦化的步骤改为表面织状化的步骤。上述图7B所揭示的程序也可以先提供一具有透光性的围栏(enclosure)63于该支架61之上,再将该发光二极管芯片62固置于该支架61的该固晶区域65之上。
请参阅图8,其是为本发明的另一发光二极管的结构的示意图,图中已省略导线线路的示意图。其制作过程如下:提供一支架81,固置多个发光二极管芯片82,形成多个透光性的围栏(enclosure)83各自框住发光二极管芯片82而形成多个空间,接着,将至少含有一荧光材料的混合树脂84注满该多个空间而完成兼具色温及亮度角分布均匀特性的白光发光二极管。接续以上的步骤,也可加入平坦化或织状化该混合树脂84表面的步骤。
据上所述,本发明借由透光性的围栏,用以框住发光二极管芯片,借此提高荧光材料涂布的均匀性,以及提高发光二极管装置的发光效率,此外,更简化均匀涂布荧光材料的程序以及降低制作成本。
当然,本发明还可有其它多种实施例,在不背离本发明精神及其实质的情况下,熟悉本领域的技术人员当可根据本发明作出各种相应的改变和变形,但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。

Claims (6)

1.一种发光二极管的制作方法,其特征在于,步骤包含:
提供一支架,该支架具有固晶区域、在该支架上表面且在该固晶区域旁边的衬垫、在该支架内部穿过的线路,及在该支架下侧的电极端子,该衬垫经由该线路而电连接到该电极端子;
固置至少一发光二极管芯片于该支架的该固晶区域上;
将该发光二极管芯片电连接到该衬垫;
于该发光二极管芯片固置及电连接到该衬垫之后,形成至少一具有透光性的围栏框住该发光二极管芯片且该围栏在该衬垫之内;以及
提供具有至少含有一荧光材料的混合树脂,形成于该围栏所包围的区域内;
该具有透光性的围栏与该发光二极管芯片边缘的相对距离小于或等于该具有至少含有该荧光材料的混合树脂的特定厚度。
2.根据权利要求1所述的发光二极管的制作方法,其特征在于,还包含平坦化该混合树脂表面的步骤。
3.根据权利要求1所述的发光二极管的制作方法,其特征在于,将该发光二极管芯片经由金属导线电连接到该衬垫。
4.一种发光二极管,其特征在于,包含:
一支架;
一发光二极管芯片,固置于该支架上;
一具有透光性的围栏,在该发光二极管芯片固置之后框住该发光二极管芯片;以及
一具有至少含有一荧光材料的混合树脂,形成于该围栏所包围的区域内;
其中该支架具有固晶区域以固置该发光二极管芯片,该支架具有在该支架上表面且在该固晶区域旁边的衬垫、在该支架内部穿过的线路,及在该支架下侧的电极端子,该衬垫经由该线路而电连接到该电极端子且该围栏在该衬垫之内;
该具有透光性的围栏与该发光二极管芯片边缘的相对距离小于或等于该具有至少含有该荧光材料的混合树脂的特定厚度。
5.根据权利要求4所述的发光二极管,其特征在于,该混合树脂的表面为平坦化的。
6.根据权利要求4所述的发光二极管,其特征在于,该发光二极管还包含一金属导线,该金属导线用以连接该发光二极管芯片于该衬垫上。
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