CN102034776B - 接合线与半导体芯片之间具有接合连接的功率半导体装置 - Google Patents

接合线与半导体芯片之间具有接合连接的功率半导体装置 Download PDF

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CN102034776B
CN102034776B CN201010501846.5A CN201010501846A CN102034776B CN 102034776 B CN102034776 B CN 102034776B CN 201010501846 A CN201010501846 A CN 201010501846A CN 102034776 B CN102034776 B CN 102034776B
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layer
power semiconductor
closing line
semiconductor arrangement
alloy
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CN102034776A (zh
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T·古特
R·罗特
D·西佩
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明涉及接合线与半导体芯片之间具有接合连接的功率半导体装置。本发明涉及在接合线(9)和功率半导体芯片(10)之间的接合连接。功率半导体芯片(10)具有半导体本体(1)，在该半导体本体(1)中布置带有在横向方向(r)上相继地布置并且电并联连接的多个单元(15)的有源单元区域(12)。半导体本体(1)具有在垂直于横向方向(r)的垂直方向(v)上布置在有源单元区域(12)之上的表面区段(11′)。金属化层(20)被涂敷到表面区段(11′)上，接合线(9)被接合到金属化层(20)上。接合线(9)由包含重量百分比为至少99的铝(91)以及至少一个其它的合金成分(92)的合金制成。铝(91)具有平均颗粒大小(<D91>)小于2μm的颗粒结构。

Description

接合线与半导体芯片之间具有接合连接的功率半导体装置
技术领域
本发明涉及一种具有在接合线与功率半导体芯片之间的接合连接的功率半导体装置。功率半导体芯片在上侧具有芯片金属化部(Chipmetallisierung)，一个或多个接合线被接合到所述芯片金属化部上，用于电接触功率半导体芯片。
背景技术
在接合过程期间，用预先给定的压紧力将接合线压向芯片金属化部，以便实现在接合线和芯片金属化部之间的紧密连接。然而，随着接合线的直径的增加，为此所需的压紧力增加，并且只要借助超声接合来进行接合，所需的超声功率也增加。然而，如果功率半导体芯片是具有带有多个电并联连接的单元的有源单元区域的器件(例如是MOSFET或者IGBT)，则在高的压紧力和高的超声功率的情况下存在以下危险：如果在有源单元区域之上进行直径例如大于100μm或者大于300μm的非常厚的接合线的接合，则单元结构被损坏并且随之而来功率半导体芯片被损坏。
因而，非常软的线材料(通常由纯度为99.99％或者99.999％的高纯度的铝构成的线材料)被用于在有源单元区域之上与厚的接合线接合，其构造的特征在于大的单颗粒和低硬度，因此在接合时需要比较小的压紧力和超声功率。由此，位于芯片金属化部之下的有源单元区域在接合期间比更硬的线材料被加上强度更小的负载。
然而，由于铝的热膨胀系数超过半导体材料(例如硅或者碳化硅)的热膨胀系数非常多，所以接合连接在频繁的具有大的温度偏移(Temperaturhub)的温度变化的情况下(如首先在切换工作时在(例如在牵引领域中的应用中)高的负载变化的情况下出现的那样)遭受极大的温度变化负载。由于这种温度变化负载，随着时间的推移，在接合线和功率半导体芯片的芯片金属化部之间的接触面减小，直至接合线最终从芯片金属化部脱落(“lift off”)。所阐述的问题在前 进发展的过程中上升，所述前进发展导致功率半导体芯片的允许的阻挡层温度越来越高并且由此导致温度变化负载更高。
为了降低接合线脱落的危险，迄今也容忍昂贵的措施。这种在DE 102005 028 951 A1中公知的措施是用聚酰亚胺密封接合部位，然而这在接合时要求附加的成本高的工艺步骤。
其它这种措施在于具有高的剪切面的接合工艺，如在Siepe、Bayerer在CIPS 2006，4th International Conference on IntegratedPower Electronics Systems(第四界关于集成功率电子系统的国际会议)(2006年6月7日至9日)上的报告：“Time and spatial resolveddetection of power device failures during wire bonding”(Neapel/Italien(意大利)，VDE出版社，柏林，法兰克福，ISBN978-3-8007-2972-2)的公开内容(CD-ROM)中所描述的那样。然而，该方法对芯片金属化部提出了高要求并且在有源单元区域之上进行接合时引起次品率的显著提高。此外，所使用的铝接合线由于高的温度和温度变化负载而再结晶并且由此改变了其机械特性。这样，例如在直径为350μm的铝接合线的情况下的四个半小时的190℃时的退火导致马氏硬度降低大约20％。此外，纯的铝接合线的断裂负载极大地降低。
发明内容
本发明的任务在于提供一种在接合线和功率半导体芯片之间的接合连接，该接合连接允许使用厚的接合线并且经受高的温度变化负载。
该任务通过根据权利要求1所述的接合连接来解决。本发明的扩展方案和改进方案是从属权利要求的主题。
在这种在接合线和功率半导体芯片之间建立的接合连接中，功率半导体芯片包括半导体本体，在该半导体本体中布置带有多个单元(例如IGBT单元或者MOSFET单元)的有源单元区域。这些单元在横向方向上相继地被布置并且电并联连接。半导体本体具有表面区段(Oberflaechenabschnitt)，该表面区段在垂直于横向方向的垂直方向上被布置在有源单元区域之上。
芯片金属化层被涂敷到表面区段上，在垂直方向上在有源单元区域之上，接合线被接合到该芯片金属化层上。该接合线由合金制成，所属合金包含重量百分比为至少99的铝。铝具有平均颗粒大小小于 2μm的颗粒结构。铝颗粒的非常小的颗粒大小通过在接合线的铝中混入至少一个合金成分来实现。在本上下文中，颗粒的最大尺寸被视为颗粒的颗粒大小。铝颗粒的平均颗粒大小通过接合线的所有铝颗粒的最大尺寸的算术平均来给出。
通过与高纯度的铝接合线相比降低铝颗粒的平均颗粒大小，接合连接的机械承载能力增加，使得接合部位的塑性变形降低或通常在颗粒边界上沿着走向的裂纹扩展明显减少并且由此提高了接合连接的使用寿命。通过铝颗粒的平均颗粒大小的改变可以使铝接合线被匹配来使得防止温度在150℃以下、在175℃以下、在200℃以下、在250℃以下或者在400℃以下时进行再结晶或者(在仅仅短时温度负载的情况下)至少明显延迟。
另一方面，通过降低铝颗粒的平均颗粒大小，接合线的硬度也升高。为了对抗在接合过程期间由此引起的对有源单元区域的可能的损害，设置了使用具有足够强度的芯片金属化部。通过将硬的线与稳健的(robust)芯片金属化部相组合，防止了差的接合产出的风险。稳健的芯片金属化部可以基于针对芯片金属化部使用硬金属。
芯片金属化部在此可以具有第一部分层以及第二部分层，该第二部分层在第一部分层和有源单元区域之间被布置在表面区段上。
根据一方面，第一部分层比接合线更硬。
根据本发明的另一方面，第一部分层由铜或者铜合金制成，铜合金比接合线更硬，而第二部分层可以是势垒层，该势垒层最大可能地防止铜从第二部分层扩散到半导体本体中。
根据本发明的又一方面，第一部分层由不含硅的铝制成，而第二部分层可以是势垒层，该势垒层最大可能地防止铝从第一部分层扩散到半导体本体中。
附图说明
以下借助实施例参照所附的附图示例性地阐述了本发明。其中：
图1示出了通过功率半导体芯片的垂直截面，该功率半导体芯片具有有源单元区域，在所述有源单元区域之上，厚的接合线被接合到芯片金属化部上；
图2示出了根据图1的接合部位的放大的区段，其中金属化层包 含两个部分层，所述两个部分层中的一个部分层具有比接合线更大的硬度，而另一部分层被布置在所述一个部分层与有源区域之间并且包括用硅掺杂的铝；
图3示出了根据图1的接合部位的放大的区段，其中金属化层包含两个部分层，所述两个部分层中的一个部分层具有铜或者铜合金，而另一部分层被布置在所述一个部分层与有源区域之间并且是针对铜的扩散势垒；
图4示出了根据图1的接合部位的放大的区段，其中金属化层包含两个部分层，所述两个部分层中的一个部分层由纯铝制成，而另一部分层被布置在所述一个部分层与有源区域之间并且是针对铝的扩散势垒；以及
图5示出了根据图2的接合部位的放大的区段，其中在第一部分层和接合线之间布置金属化层的另一部分层。
所示的附图除非另外提及都不是合乎比例的。在以下具体实施方式部分中所使用的与方向相关的术语(例如如“上”、“下”、“左”、“右”、“前”、“后”、“侧面”、“在...上”、“在...下”...之类的概念)涉及相应的附图。这些术语仅被用于使对具体实施方式部分的理解容易。基本上，所示的元件在空间上可以任意地布置，只要从本说明书中没有其它内容得出。此外，除非明确地另外提及，在不同的附图中，相同的附图标记表示具有相同的或者彼此相对应的功能的相同的或者彼此相对应的元件。
具体实施方式
图1示出了通过功率半导体芯片10的垂直截面，该功率半导体芯片10具有带有多个有源单元15的半导体本体1，这些有源单元15在横向方向r上相继地被布置并且电并联连接。有源单元15例如可以是MOSFET单元或者IGBT单元。有源单元仅仅示意性地被布置，因为其结构对于本领域技术人员而言基本上是公知的。
在垂直于横向方向r的垂直方向v上，半导体本体1具有带有表面区段11′的上侧11，该表面区段11′在垂直方向v上仅被布置在有源单元区域12之上。芯片金属化层20被涂敷到表面区段11′上，在垂直方向v上在有源单元区域之上，接合线9被接合到该芯片金属化层20 上。接合线9的直径基本上是任意的，该直径例如可以为大于100μm或者大于300μm。此外，接合线9由包含重量百分比为至少99的铝以及至少一个其它的合金成分的合金制成。铝具有平均颗粒大小小于2μm的颗粒结构。
图2示出了根据图1的布局的放大的区段。接合线9的区段就其而言还被放大地示出。由此清楚的是，接合线具有铝，颗粒91以颗粒大小D91形成。在本发明的意义上，所涉及的颗粒91的最大尺寸D91被视为颗粒大小。接合线9的所有铝颗粒91的算术平均<D91>小于2μm。该算术平均根据下式被确定：
< D 91 > = 1 N &CenterDot; &Sigma; i = 1 N D 91 ( i )
其中N是接合线9的铝颗粒91的数目，而D91(i)是第i个铝颗粒91的最大尺寸。
小的平均颗粒大小<D91>通过如下方式实现：接合线9包含至少一个合金成分92。例如，总合金比例为例如接合线9的0.2重量百分比至1重量百分比的各个或彼此任意组合的Mg、Si、Ti、Cu、Pd适合作为合金成分92。接合线9例如可以由如下材料之一形成：AlMg、AlSi、AlTi、AlCu、AlSiCu、AlMgPd。
芯片金属化部20包括由导电材料构成的第一部分层21，该第一部分层21的马氏硬度大于接合线9的硬度。第一部分层例如可以具有如下材料中的恰好一种或多种或者由如下材料中的恰好一种或多种制成：Ni、NiB、NiP、CoWB、CoWB、NiWP、NiWB、NiMoP、NiMoB、NiCoP、NiCoB、NiPd、Cu或者Cu合金。
在第一部分层21和有源单元区域12之间布置有第二部分层22，该第二部分层22例如可以由AlSi、AlSiCu或者AlSiTi制成或者可以具有这些成分中的至少一种，其具有比例为大于90重量百分比的铝并且包含重量百分比为0.2至5.0的Si的混合物并且由此也包含硅沉淀物25。
在根据图3的例子中，接合线9与按照图2所阐述的接合线9一样地被构造。在该例子中，第一部分层21由铜或者铜合金制成。第一部分层21又比接合线9更硬。替换于铜，例如也可以采用镍、金或者铂，或者可以采用具有这些金属中的至少一种的合金。
第二部分层22如在根据图2的布局中那样被布置在第一部分层21和有源单元区域12之间。第二部分层22是势垒层，所述势垒层最大可能地防止铜从第一部分层21扩散到半导体本体1中。例如TiN、Ta、TaN、TiW或者W、合金或者这些层加上可能的中间层(所述中间层例如可以承担粘附功能)与这些材料中的至少一种的组合适合作为势垒层22的材料。
提高接合时的产出的另一可能性按照图4来阐述。在这种情况下，使用了具有由Al、AlCu、AlTi或者带有这些物质(Stoffe)中的至少一种的合金构成的第一部分层21的芯片金属化部20，其不含硅沉淀物。硅和由此硅沉淀物通常被引入铝或者含有铝的合金中，以便避免在半导体本体中出现有害的“Al尖峰形成(Al-Spiking)”。当来自芯片金属化部的铝和来自半导体本体的S i相互交换并且因此可损坏Si中的pn结时，发生“Al尖峰形成”。通过硅沉淀物，铝被结合到金属化部中直至某一程度，由此降低了铝扩散到半导体本体中。但是，硅沉淀物是接合时的主要故障原因，使得接合连接的质量可以通过去除硅沉淀物来改进。但是接着有利的是：在不含硅沉淀物的第一部分层21和半导体本体之间设置可选的第二部分层22，该第二部分层22最大可能地防止铝扩散到半导体本体1中。
通常，对于势垒层22合适的是这种材料，这种材料中的物质到半导体本体1中的扩散应通过势垒层22来减少。为了能够越过势垒层22，该物质必须具有某一最小能量、即所谓的激活能量。激活能量一方面与物质本身有关，另一方面与势垒层22的材料有关，以及与其厚度有关。因此，有利的是：在预先给定的物质(例如铝)和预先给定的、势垒层22的材料的情况下选择势垒层的厚度，使得所需的激活能量大于在器件的使用寿命期间在物质中出现的粒子能的主要部分。在假定使用寿命为15年的情况下，对穿过势垒层22所需的激活能量可以为例如0.9eV。在图3或4中的布局的情况下作为势垒层22的材料合适的是例如TiN、Ta、TaN、TiW或者W或者具有这些材料中的至少一种的合金。
在根据本发明的所有变形方案中，接合线可以直接接触第一部分层21。对此可替换地，如在图5中所示的那样，芯片金属化部的另外的第三部分层23还被涂敷到第一部分层21上。这种布置在接合线9 和第一部分层21之间的第三部分层23例如可以是氧化保护层，利用该氧化保护层保护芯片金属化部21的紧接着位于下面的部分层(即在图5中为第一部分层21)免受氧化影响。由此，能够实现接合连接的更高的强度，因为在要与接合线连接的金属化部上的氧化物表面对于接合连接的质量有不利的影响。基本上，这种第三部分层也承担其它功能，例如用于保护免受在处理功率半导体芯片时采用的化学材料的影响。作为这种第三部分层23的材料合适的例如是Au、Pt、Pd、Ag或者Ni或者具有这些金属中的至少一种的合金。
利用本发明可以放弃使用如接合线密封之类的特别措施。同样，自然可以补充地设置接合线密封。本发明的优点在于与此相联系的附加费用远在用于接合线密封的附加费用之下。此外，与接合线密封过的模块相比实现了对负载疲劳强度的另一改进。本发明的另一优点在于，稳健的金属化部并未改变芯片的电参数，使得也可以以简单的方式转换生产的芯片。
本发明在1.2kV和6.5kV的截止电压的情况下结合由AlMg 0.5％(即Al的重量百分比为99.5而Mg的重量百分比为0.5)构成的并且直径为400μm的接合线针对IGBT进行测试。对此，选择根据图2的结构，其中稳健的第一部分层21是无电流沉积的镍层，而第二部分层22是AlSiCu芯片金属化部。第一部分层21和第二部分层22的层厚度被选择为大致相同。在与传统的接合连接并行的系列测试中出现了十五个栅极-发射极故障，七个IGBT在接合时完全被损坏。与此相对，在根据本发明的接合连接的系列测试中，未发生一个故障。所测试的件数在这两个系列测试中分别为100。

Claims (20)

1.一种在接合线和功率半导体芯片之间具有接合连接的功率半导体装置，其包括带有半导体本体(1)的功率半导体芯片(10)，在所述半导体本体(1)中布置带有多个单元(15)的有源单元区域(12)，所述单元(15)在横向方向(r)上相继地被布置并且电并联连接，其中
-所述半导体本体(1)具有表面区段(11′)，所述表面区段(11′)在垂直于横向方向(r)的垂直方向(v)上被布置在有源单元区域(12)之上；
-金属化层(20)被涂敷到所述表面区段(11′)上，接合线(9)被接合到所述金属化层(20)上；
-接合线(9)由合金制成，所述合金包含重量百分比为至少99的铝(91)以及至少一个其它的合金成分(92)；
-铝(91)具有平均颗粒大小(<D91>)小于2μm的颗粒结构。
2.根据权利要求1所述的功率半导体装置，其中，金属化层(20)具有第一部分层(21)以及第二部分层(22)，所述第二部分层(22)在第一部分层(21)和有源单元区域(12)之间被布置在表面区段(11′)上。
3.根据权利要求2所述的功率半导体装置，其中，第一部分层(21)直接接触第二部分层(22)。
4.根据权利要求2或3所述的功率半导体装置，其中，第一部分层(21)具有比接合线(9)的硬度更大的硬度。
5.根据权利要求4所述的功率半导体装置，其中，第一部分层(21)具有如下材料中的恰好一种或多种或者由如下材料中的恰好一种或多种制成或者由具有如下材料中的恰好一种或多种的合金制成：Ni、NiB、NiP、CoWB、CoWB、NiWP、NiWB、NiMoP、NiMoB、NiCoP、NiCoB、NiPd、Cu、Cu合金。
6.根据权利要求2或3所述的功率半导体装置，其中，第二部分层(22)由铝制成，在铝中附有重量百分比为0.2到5.0的硅沉淀物。
7.根据权利要求2或3所述的功率半导体装置，其中，第一部分层(21)由Al、AlCu、AlTi或者具有前述物质中的至少一种的合金制成并且不合硅沉淀物。
8.根据权利要求2或3所述的功率半导体装置，其中，第二部分层(22)被构造为势垒层。
9.根据权利要求8所述的功率半导体装置，其中，构造为势垒层的第二部分层(22)的厚度被选择为使得第一部分层(21)的粒子从其起能够扩散穿过第二部分层(22)的激活能量为至少0.9eV。
10.根据权利要求9所述的功率半导体装置，其中，构造为势垒层的第二部分层(22)的厚度被选择为使得铜和/或铝从其起能够扩散穿过第二部分层(22)的激活能量为至少0.9eV。
11.根据权利要求8所述的功率半导体装置，其中，第二部分层(22)由如下材料之一制成或者由具有如下材料之一的合金制成：TiN、Ta、TaN、TiW、W。
12.根据权利要求1至3之一所述的功率半导体装置，其中，所述其它的合金成分(92)包括如下物质中的一种或多种：Mg、Si、Ti、Cu、Si、Pd。
13.根据权利要求1至3之一所述的功率半导体装置，其中，接合线(9)直接接触第一部分层(21)。
14.根据权利要求1至3之一所述的功率半导体装置，其中，芯片金属化部(20)包括第三部分层(23)，所述第三部分层(23)在垂直方向(v)上被布置在接合线(9)和第一部分层(21)之间。
15.根据权利要求14所述的功率半导体装置，其中，接合线(9)直接接触第三部分层(23)。
16.根据权利要求11所述的功率半导体装置，其中，接合线由如下材料之一形成：AlMg、AlSi、AlTi、AlCu、AlSiCu、AlMgPd。
17.根据权利要求1至3之一所述的功率半导体装置，其中，接合线(9)具有大于100μm的直径。
18.根据权利要求17所述的功率半导体装置，其中，接合线(9)具有大于等于300μm的直径。
19.根据权利要求1至3之一所述的功率半导体装置，其中，接合线(9)未被密封。
20.根据权利要求1至3之一所述的功率半导体装置，其中，功率半导体芯片(10)是MOSFET或者IGBT，并且其中，所述单元(15)是MOSFET的单元或IGBT的单元。
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