CN102097404A - 低衬底电阻的晶圆级芯片尺寸封装及其制造方法 - Google Patents
低衬底电阻的晶圆级芯片尺寸封装及其制造方法 Download PDFInfo
- Publication number
- CN102097404A CN102097404A CN 200910253713 CN200910253713A CN102097404A CN 102097404 A CN102097404 A CN 102097404A CN 200910253713 CN200910253713 CN 200910253713 CN 200910253713 A CN200910253713 A CN 200910253713A CN 102097404 A CN102097404 A CN 102097404A
- Authority
- CN
- China
- Prior art keywords
- semiconductor wafer
- metal layer
- low resistance
- resistance substrate
- crystal wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 89
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 238000004806 packaging method and process Methods 0.000 title abstract description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 146
- 229910052751 metal Inorganic materials 0.000 claims abstract description 141
- 239000002184 metal Substances 0.000 claims abstract description 141
- 239000013078 crystal Substances 0.000 claims description 82
- 238000005538 encapsulation Methods 0.000 claims description 77
- 238000000034 method Methods 0.000 claims description 44
- 229910000679 solder Inorganic materials 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 238000005516 engineering process Methods 0.000 claims description 16
- 239000004593 Epoxy Substances 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 150000002739 metals Chemical class 0.000 claims description 7
- 238000005498 polishing Methods 0.000 claims description 6
- 238000003466 welding Methods 0.000 abstract description 2
- 230000003014 reinforcing effect Effects 0.000 abstract 5
- 230000009286 beneficial effect Effects 0.000 abstract 1
- 238000001465 metallisation Methods 0.000 abstract 1
- 238000011112 process operation Methods 0.000 abstract 1
- 238000012545 processing Methods 0.000 description 16
- 230000000694 effects Effects 0.000 description 4
- 241000587161 Gomphocarpus Species 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 241000196324 Embryophyta Species 0.000 description 1
- -1 as shown in Figure 3 Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims (19)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN 200910253713 CN102097404B (zh) | 2009-12-10 | 2009-12-10 | 低衬底电阻的晶圆级芯片尺寸封装及其制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN 200910253713 CN102097404B (zh) | 2009-12-10 | 2009-12-10 | 低衬底电阻的晶圆级芯片尺寸封装及其制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102097404A true CN102097404A (zh) | 2011-06-15 |
CN102097404B CN102097404B (zh) | 2013-09-11 |
Family
ID=44130408
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN 200910253713 Active CN102097404B (zh) | 2009-12-10 | 2009-12-10 | 低衬底电阻的晶圆级芯片尺寸封装及其制造方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN102097404B (zh) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103579020A (zh) * | 2012-08-07 | 2014-02-12 | 万国半导体股份有限公司 | 一种晶圆级芯片的封装方法 |
CN103839910A (zh) * | 2012-11-21 | 2014-06-04 | 英飞凌科技奥地利有限公司 | 包括芯片载体的半导体器件组件、半导体晶片和制造半导体器件的方法 |
CN105448854A (zh) * | 2014-08-29 | 2016-03-30 | 万国半导体股份有限公司 | 用于带有厚背面金属化的模压芯片级封装的晶圆制作方法 |
CN111463141A (zh) * | 2019-01-18 | 2020-07-28 | 芯恩(青岛)集成电路有限公司 | 一种提高晶圆探针台利用率的方法 |
CN111463160A (zh) * | 2019-01-18 | 2020-07-28 | 芯恩(青岛)集成电路有限公司 | 一种半导体器件及其制造方法 |
CN111613545A (zh) * | 2019-02-26 | 2020-09-01 | 芯恩(青岛)集成电路有限公司 | 一种晶圆及晶圆测试方法 |
CN111613546A (zh) * | 2019-02-26 | 2020-09-01 | 芯恩(青岛)集成电路有限公司 | 一种晶圆及晶圆测试方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070231954A1 (en) * | 2006-03-31 | 2007-10-04 | Kai Liu | Gold/silicon eutectic die bonding method |
US7468544B2 (en) * | 2006-12-07 | 2008-12-23 | Advanced Chip Engineering Technology Inc. | Structure and process for WL-CSP with metal cover |
US20080166837A1 (en) * | 2007-01-10 | 2008-07-10 | Tao Feng | Power MOSFET wafer level chip-scale package |
US20080242052A1 (en) * | 2007-03-30 | 2008-10-02 | Tao Feng | Method of forming ultra thin chips of power devices |
-
2009
- 2009-12-10 CN CN 200910253713 patent/CN102097404B/zh active Active
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103579020A (zh) * | 2012-08-07 | 2014-02-12 | 万国半导体股份有限公司 | 一种晶圆级芯片的封装方法 |
CN103579020B (zh) * | 2012-08-07 | 2016-06-08 | 万国半导体股份有限公司 | 一种晶圆级芯片的封装方法 |
CN103839910A (zh) * | 2012-11-21 | 2014-06-04 | 英飞凌科技奥地利有限公司 | 包括芯片载体的半导体器件组件、半导体晶片和制造半导体器件的方法 |
US9768120B2 (en) | 2012-11-21 | 2017-09-19 | Infineon Technologies Austria Ag | Semiconductor device assembly including a chip carrier, semiconductor wafer and method of manufacturing a semiconductor device |
CN105448854A (zh) * | 2014-08-29 | 2016-03-30 | 万国半导体股份有限公司 | 用于带有厚背面金属化的模压芯片级封装的晶圆制作方法 |
CN111463141A (zh) * | 2019-01-18 | 2020-07-28 | 芯恩(青岛)集成电路有限公司 | 一种提高晶圆探针台利用率的方法 |
CN111463160A (zh) * | 2019-01-18 | 2020-07-28 | 芯恩(青岛)集成电路有限公司 | 一种半导体器件及其制造方法 |
CN111613545A (zh) * | 2019-02-26 | 2020-09-01 | 芯恩(青岛)集成电路有限公司 | 一种晶圆及晶圆测试方法 |
CN111613546A (zh) * | 2019-02-26 | 2020-09-01 | 芯恩(青岛)集成电路有限公司 | 一种晶圆及晶圆测试方法 |
CN111613545B (zh) * | 2019-02-26 | 2023-09-26 | 芯恩(青岛)集成电路有限公司 | 一种晶圆测试结构及晶圆测试方法 |
CN111613546B (zh) * | 2019-02-26 | 2023-09-26 | 芯恩(青岛)集成电路有限公司 | 一种晶圆测试结构及晶圆测试方法 |
Also Published As
Publication number | Publication date |
---|---|
CN102097404B (zh) | 2013-09-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102097404B (zh) | 低衬底电阻的晶圆级芯片尺寸封装及其制造方法 | |
US11626372B2 (en) | Metal-free frame design for silicon bridges for semiconductor packages | |
US7462930B2 (en) | Stack chip and stack chip package having the same | |
US11037863B2 (en) | Semiconductor device | |
US11676889B2 (en) | Guard ring design enabling in-line testing of silicon bridges for semiconductor packages | |
US10229870B2 (en) | Packaged semiconductor device with tensile stress and method of making a packaged semiconductor device with tensile stress | |
US9825002B2 (en) | Flipped die stack | |
US9093437B2 (en) | Packaged vertical power device comprising compressive stress and method of making a packaged vertical power device | |
Motoyoshi et al. | 3D-LSI technology for image sensor | |
CN103926430B (zh) | 一种硅通孔转接板测试方法 | |
US10546827B2 (en) | Flip chip | |
US8076786B2 (en) | Semiconductor package and method for packaging a semiconductor package | |
Hau-Riege et al. | Electromigration studies of lead-free solder balls used for wafer-level packaging | |
TW200625562A (en) | Semiconductor package and fabrication method thereof | |
CN105390471A (zh) | 扇出晶圆级封装结构 | |
TWI421990B (zh) | 低襯底電阻的晶圓級晶片尺寸封裝及其製造方法 | |
CN102651359B (zh) | 具有低阻值基材与低功率损耗的半导体结构 | |
CN105304507A (zh) | 扇出晶圆级封装方法 | |
TWI235470B (en) | Asymmetric bump structure | |
US20080211080A1 (en) | Package structure to improve the reliability for WLP | |
CN101626003B (zh) | 焊线接合结构及焊线接合方法 | |
JP4862991B2 (ja) | 半導体装置の製造方法 | |
Nimura et al. | Hybrid Au-underfill resin bonding with lock-and-key structure | |
CN103413799A (zh) | 凸点结构 | |
CN203536419U (zh) | 提高封装可靠性的铝垫结构 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CP01 | Change in the name or title of a patent holder | ||
CP01 | Change in the name or title of a patent holder |
Address after: No. 495 California Avenue, Sunnyvale mercury Patentee after: ALPHA & OMEGA SEMICONDUCTOR, Ltd. Address before: No. 495 California Avenue, Sunnyvale mercury Patentee before: Alpha and Omega Semiconductor Inc. |
|
TR01 | Transfer of patent right |
Effective date of registration: 20170619 Address after: Chongqing city Beibei district and high tech Industrial Park the road No. 5 of 407 Patentee after: Chongqing Wanguo Semiconductor Technology Co.,Ltd. Address before: Bermuda Hamilton Church 2 Cola Lunden House Street Patentee before: ALPHA & OMEGA SEMICONDUCTOR, Ltd. Effective date of registration: 20170619 Address after: Bermuda Hamilton Church 2 Cola Lunden House Street Patentee after: ALPHA & OMEGA SEMICONDUCTOR, Ltd. Address before: No. 495 California Avenue 94085 Sunnyvale mercury Patentee before: ALPHA & OMEGA SEMICONDUCTOR, Ltd. |
|
TR01 | Transfer of patent right | ||
PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: Wafer level chip scale packaging structure with low substrate resistance and manufacturing method thereof Effective date of registration: 20191210 Granted publication date: 20130911 Pledgee: Chongqing Branch of China Development Bank Pledgor: Chongqing Wanguo Semiconductor Technology Co.,Ltd. Registration number: Y2019500000007 |
|
PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
PC01 | Cancellation of the registration of the contract for pledge of patent right |
Granted publication date: 20130911 Pledgee: Chongqing Branch of China Development Bank Pledgor: Chongqing Wanguo Semiconductor Technology Co.,Ltd. Registration number: Y2019500000007 |
|
PC01 | Cancellation of the registration of the contract for pledge of patent right |