Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of method that reduces the corner defective of shallow trench isolation channels, thereby reduces the corner defective of shallow trench isolation channels effectively.
For achieving the above object, the technical scheme among the present invention is achieved in that
A kind of method that reduces the corner defective of shallow trench isolation channels, this method comprises:
On Semiconductor substrate, forming pad oxide, silicon nitride layer and photoresist layer successively, after carrying out exposure imaging technology, is that mask carries out etching to said silicon nitride layer, pad oxide and Semiconductor substrate with the photoresist layer, forms shallow trench;
After forming said shallow trench, use the chemical vapour deposition technique depositing insulating layer of low deposition rate; Wherein, the deposition rate in the said chemical vapour deposition technique be 1500~2100 dusts/minute;
Remove the insulating barrier on the said silicon nitride layer through the CMP process process; And then remove said silicon nitride layer and pad oxide, form the shallow trench isolation channels structure.
When using the chemical vapour deposition technique depositing insulating layer of low deposition rate, employed gas is silane, and the gas flow of this gas is 60~110 cc/min.
The said insulating barrier of removing on the said silicon nitride layer through the CMP process process comprises:
CMP process process through low downforce is removed the insulating barrier on the said silicon nitride layer.
Downforce in the said CMP process process is 1.2~1.8 pounds/square inch
To sum up can know, a kind of method that reduces the corner defective of shallow trench isolation channels is provided among the present invention.In the method for the corner of said minimizing shallow trench isolation channels defective; Owing to use the chemical vapour deposition technique depositing insulating layer of low deposition rate; And can remove the insulating barrier on the silicon nitride layer through the CMP process process of low downforce, therefore can reduce effectively until the corner defective of eliminating shallow trench isolation channels fully.
Embodiment
For making the object of the invention, technical scheme and advantage express clearlyer, the present invention is remake further detailed explanation below in conjunction with accompanying drawing and specific embodiment.
Before introducing method provided by the invention, need to introduce in detail earlier process and the reason that said Smear Defect produces, for for simplicity, still be that example describes with Fig. 1:
At first; Shown in Fig. 1 (b); Utilizing HDPCVD method depositing insulating layer 110 on silicon nitride layer 104 and formed shallow trench 108, making said insulating barrier 110 that said shallow trench 108 is filled in the full process, because the shape of the corner location of said silicon nitride layer 104 is comparatively sharp-pointed; Therefore in the process of the above-mentioned insulating barrier 110 of deposition, the corner location of said silicon nitride layer 104 is whole silicon nitride layer 104 stressed positions of concentrating the most; And; Because its shape is comparatively sharp-pointed; The insulating barrier that also occurs easily being deposited interconnects the phenomenon of adhering to defective tightness with the corner location of silicon nitride layer, thereby makes that the density of the insulating barrier that deposits in the corner location place of said silicon nitride layer 104 is less and structure is more loose; In addition; When using the HDPCVD method on silicon nitride layer 104 and formed shallow trench 108 during depositing insulating layer 110; Because employed deposition rate (dep rate) is than very fast; Be generally 3000 dusts/minute (A/min); Thereby make that the compression (stress) at interface place of the insulating barrier that in formed shallow trench 108, deposited and AA is generally all bigger, thereby be easy to generate the phenomenon of delaminate (peeling off), thereby produce corner defective (smear defect) at the corner location of above-mentioned shallow trench isolation channels easily.
Secondly, when the insulating barrier 110 to deposition shown in Fig. 1 (c) carries out CMP, need the insulating barrier 110 of silicon nitride layer 104 tops all be removed.And in above-mentioned CMP process; (Down force) is bigger for employed downforce; Be generally 4 pounds/square inch (psi); Less, the short texture of insulating barrier density at the corner location place of said silicon nitride layer in addition, and the compression at the interface place of silicon nitride layer that is deposited and AA is bigger, therefore under the effect of the mechanical lapping of the big downforce in the CMP process; The structure of the insulating barrier at the corner location place of said silicon nitride layer is destroyed easily, thereby easily produces the corner defective at the corner location of above-mentioned shallow trench isolation channels.
In addition, after carrying out the CMP process, also need remove silicon nitride layer 104 and pad oxide 102 through Wet Etch.Because less, the short texture of insulating barrier density at the corner location place of said silicon nitride layer; Therefore in above-mentioned Wet Etch process; The corner location of above-mentioned shallow trench isolation channels will further be destroyed by employed acid solution burn in the Wet Etch process, thereby produces the corner defective at the corner location of above-mentioned shallow trench isolation channels.
According to above-mentioned analysis, in technical scheme of the present invention, a kind of method that reduces the corner defective of shallow trench isolation channels has been proposed to said corners of shallow-channel isolation groove generation of defects reason.Fig. 2 is the schematic flow sheet of the method for the corner defective of minimizing shallow trench isolation channels among the present invention.As shown in Figure 2, the method for the corner defective of the minimizing shallow trench isolation channels that is provided among the present invention comprises the step that is described below:
Step 201 forms pad oxide, silicon nitride layer and photoresist layer successively on Semiconductor substrate, after carrying out exposure imaging technology, be that mask carries out etching to silicon nitride layer, pad oxide and Semiconductor substrate with the photoresist layer, forms shallow trench.
In this step, will at first on Semiconductor substrate, form pad oxide, silicon nitride layer and photoresist layer successively respectively, wherein, said Semiconductor substrate can be silicon base or other insulating material, the material of said pad oxide is SiO
2, the material of said silicon nitride layer is a silicon nitride; Then through exposure imaging technology, definition shallow trench figure, and be mask with the photoresist layer, with dry etching method etch silicon nitride layer, pad oxide and Semiconductor substrate, thereby form a groove.After forming said groove, also can remove photoresist layer, and then remove residual photoresist layer with the wet etching method through the ashing treatment process, finally form required shallow trench.
Step 202 after forming said shallow trench, is used chemical vapour deposition technique (CVD) depositing insulating layer of low deposition rate.
In this step, the chemical vapour deposition technique (for example, the HDPCVD of low deposition rate) that uses low deposition rate is formed insulating barrier on silicon nitride layer, and said insulating barrier can be filled said shallow trench full; The material of said insulating barrier is generally silicon dioxide.In addition, in an embodiment of the present invention, when using the chemical vapour deposition technique depositing insulating layer of low deposition rate, employed gas can be silane (SiH
4), the gas flow of this gas can be 60~110 cc/min (SCCM).
Wherein, the deposition rate of said CVD is 1500~2100A/min; Preferable, the deposition rate of said CVD is 1800A/min.Because the deposition rate of above-mentioned CVD is far below deposition rate of the prior art; Therefore make that the density of formed insulating barrier is big and structure is dense; Reduce the compression at the interface place of the insulating barrier that deposited and AA, thereby can avoid producing the phenomenon of delaminating as far as possible; Simultaneously, the possibility that the corner location that has also reduced above-mentioned shallow trench isolation channels is destroyed by employed acid solution burn in the Wet Etch process, and then can alleviate even eliminate the corner defective that corner location produced at above-mentioned shallow trench isolation channels.
Step 203 is removed the insulating barrier on the silicon nitride layer through CMP process (CMP) process; And then remove silicon nitride layer and pad oxide, finally form the shallow trench isolation channels structure.
In this step, can use CMP process commonly used to remove the insulating barrier on the silicon nitride layer, and after removing silicon nitride layer and pad oxide, finally form the shallow trench isolation channels structure.Concrete CMP process repeats no more at this.
Prove through experimental data; Adopt in the resulting wafer of technological process (wafer) of formation STI of the prior art; Smear Defect detected in the sample area of setting is generally about 28~58; And among the resulting wafer of method of the corner defective of the minimizing shallow trench isolation channels of stating in the use, Smear Defect detected in onesize sample area is generally at 8~9.This shows that the method for the corner defective of the minimizing shallow trench isolation channels that is proposed among the present invention can be eliminated the corner defective that corner location produced at above-mentioned shallow trench isolation channels effectively.
In addition, in an embodiment of the present invention, can also further improve above-mentioned steps 203, amended step is:
Step 203 ', remove the insulating barrier on the silicon nitride layer through CMP process (CMP) process of low downforce; And then remove silicon nitride layer and pad oxide, finally form the shallow trench isolation channels structure.
In this step, will carry out planarization to said insulating barrier, promptly adopt CMP technical process to remove the insulating barrier on the silicon nitride layer with low downforce.Then, again through removal method (for example, Wet Etch) commonly used; Remove silicon nitride layer 304 and pad oxide 302, thereby form required shallow trench isolation channels structure.Wherein, employed downforce is 1.2~1.8psi in the said CMP process with low downforce; Preferable, employed downforce is 1.5psi in the said CMP process.In addition; Except the numerical value of above-mentioned downforce; Employed other corresponding parameter is identical in other parameter in the CMP process of above-mentioned low downforce and the commonly used CMP process; Promptly in the CMP of above-mentioned low downforce process, can directly use other parameter except that downforce in the CMP process commonly used.
Because the downforce of the downforce in the above-mentioned CMP process in the CMP process of the prior art; Therefore make that the structure of insulating barrier at corner location place of silicon nitride layer is destroyed not too easily, thereby can further avoid producing the corner defective at the corner location of above-mentioned shallow trench isolation channels.
Prove that through experimental data among the resulting wafer of method of the corner defective of the minimizing shallow trench isolation channels of stating in the use, Smear Defect detected in onesize sample area is generally about 0~2.This shows that the method for the corner defective of the minimizing shallow trench isolation channels that is proposed among the present invention can significantly reduce even eliminate fully the corner defective that corner location produced at above-mentioned shallow trench isolation channels.
In the method for the corner defective of above-mentioned minimizing shallow trench isolation channels; Owing to use the chemical vapour deposition technique depositing insulating layer of low deposition rate; And can remove the insulating barrier on the silicon nitride layer through the CMP process process of low downforce; Therefore can significantly reduce even eliminate fully the corner defective that corner location produced at above-mentioned shallow trench isolation channels; Lack adverse effect thereby reduced said corner, improved the performance of semiconductor components and devices the electric property of semiconductor components and devices.
The above is merely preferred embodiment of the present invention, is not to be used to limit protection scope of the present invention.All within spirit of the present invention and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.