KR20020011472A - Method of fabricating shallow-trench-isolation utilized the characteristics of base material - Google Patents

Method of fabricating shallow-trench-isolation utilized the characteristics of base material Download PDF

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KR20020011472A
KR20020011472A KR1020000044751A KR20000044751A KR20020011472A KR 20020011472 A KR20020011472 A KR 20020011472A KR 1020000044751 A KR1020000044751 A KR 1020000044751A KR 20000044751 A KR20000044751 A KR 20000044751A KR 20020011472 A KR20020011472 A KR 20020011472A
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shallow trench
forming
film
trench
oxide film
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KR1020000044751A
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KR100419869B1 (en
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김연수
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박종섭
주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition

Abstract

PURPOSE: A shallow trench isolation(STI) method is provided to improve a characteristic of a semiconductor device using an STI, by using an atmospheric pressure chemical vapor deposition(APCVD) method in which the difference of deposition rates according to a base layer is used and a trench is filled with O3/tetra-ethyl-ortho-silicate undoped silicate glass(TEOS USG). CONSTITUTION: A predetermined layer for a shallow trench isolation process is formed on a substrate(10) to form a shallow trench(14). A trench oxide layer is formed on the shallow trench. An etch process is performed regarding the trench oxide layer to expose the upper portion of the substrate and to form a wall oxide layer on the wall of the shallow trench. The shallow trench is filled with a predetermined filling material using the difference of the deposition rates of the substrate and the wall oxide layer.

Description

하지막 의존성을 이용한 쉘로우트렌치분리 형성방법{METHOD OF FABRICATING SHALLOW-TRENCH-ISOLATION UTILIZED THE CHARACTERISTICS OF BASE MATERIAL}Method for forming shallow trench isolation using dependence of underlying film {METHOD OF FABRICATING SHALLOW-TRENCH-ISOLATION UTILIZED THE CHARACTERISTICS OF BASE MATERIAL}

본 발명은 반도체소자의 제조공정에 관한 것으로, 자세하게는 하지막(base material) 의존성을 이용하여 증착속도를 선택적으로 조절하여 쉘로우트렌치분리(Salllow Trench Isolation; 이하 'STI'라 함)공정의 산화막 매립(Gap-Filling)과정을 향상시킴으로써, 트랜지스터의 전기적특성을 향상시킬 수 있는, 하지막 의존성을 이용한 쉘로우트렌치분리 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing process of a semiconductor device, and more particularly, to deposit an oxide film in a shallow trench isolation (STI) process by selectively controlling a deposition rate using a base material dependency. The present invention relates to a method of forming a shallow trench isolation using the underlying film dependency, by improving the (Gap-Filling) process.

STI공정은 종래의 필드산화막(Field Oxide ; Fox) 대신 미소폭의트렌치(Shallow Trench)에 의해 분리막을 형성하는 공정이다. 이러한 STI 공정을 간단히 언급하면, 먼저 실리콘기판 상부에 산화막이나 질화막을 증착하고 여기에 우물형태와 비슷한 쉘로우트렌치를 형성한다. 이후 트렌치매립 산화막으로 트렌치를 매립한 후, 화학기계적연마(CMP)등의 후처리 공정으로 그 상부를 평탄화시키므로써 분리공정을 완성한다.The STI process is a process of forming a separator by a shallow trench instead of a conventional field oxide (FOX). Briefly referring to this STI process, an oxide film or nitride film is first deposited on a silicon substrate, and a shallow trench similar to a well type is formed thereon. Thereafter, the trench is filled with a trench buried oxide film, and then the upper part is planarized by a post-treatment process such as chemical mechanical polishing (CMP) to complete the separation process.

그러나, 전술한 종래 기술에서 쉘로우트렌치 매립용 산화막으로 상압화학기상증착(이하 'APCVD'라 함) O3/TEOS USG(Terra Ethyle Ortho Silicate Undoped Silicate Glass)를 사용할 경우, APCVD O3/TEOS USG의 하지막 의존성으로 인해 보이드(void)나 이음새(seam) 등이 발생하는 문제가 있다. 이러한 보이드나 이음새는 후속공정시 막(film)에 틈이나 결함 등을 야기시킴으로써 소자의 특성에 치명적인 영향을 주는 문제점이 있다.However, in the above-described conventional technique, when atmospheric pressure chemical vapor deposition (hereinafter referred to as 'APCVD') O 3 / TEOS USG (Terra Ethyle Ortho Silicate Undoped Silicate Glass) is used as the oxide film for shallow trench embedding, APCVD O 3 / TEOS USG There is a problem that voids or seams occur due to the underlying film dependence. Such voids or seams have a problem that causes a fatal effect on the characteristics of the device by causing gaps or defects in the film during the subsequent process.

따라서 전술한 문제점을 해결하기 위한 본 발명의 목적은, APCVD O3/TEOS USG의 하지막 의존성을 이용하여 트렌치에 산화막을 매립할 시 트렌치의 밑부분을 옆면에 비해 빠르게 증착시키도록 제작함으로써, 보이드 등의 발생을 예방함으로써 트랜지스터의 전기적특성을 향상시키기 위한, 하지막 의존성을 이용한 쉘로우트렌치분리 형성방법을 제공하는 데 있다.Therefore, an object of the present invention to solve the above problems, by using the underlying film dependency of APCVD O 3 / TEOS USG by making the bottom of the trench to be deposited faster than the side when buried in the trench, voids The present invention provides a method of forming a shallow trench isolation by using the underlying film dependency to improve the electrical characteristics of a transistor by preventing the occurrence of such a material.

도 1 내지 도 3는 본 발명의 일실시예에 따른 쉘로우트렌치분리 형성방법을 설명하기 공정도.1 to 3 is a flow chart illustrating a shallow trench isolation forming method according to an embodiment of the present invention.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

10 : 실리콘기판 12 : 질화막10 silicon substrate 12 nitride film

14 : 트렌치 16 : 트렌치산화막14 trench 16 trench oxide film

18 : 열산화막 20 : 트렌치매립층18: thermal oxide film 20: trench buried layer

본 발명에 따른 하지막 의존성을 이용한 쉘로우트렌치분리 형성방법은, 쉘로우 트렌치 분리를 형성하기 위한 공정에 있어서,The shallow trench isolation forming method using the underlying film dependency according to the present invention is a process for forming shallow trench isolation,

기판 상부에 상기 공정을 위한 소정막을 증착하고 쉘로우트렌치를 형성하는 제1단계; 상기 형성된 쉘로우트렌치 표면에 트렌치산화막을 형성하는 제2단계; 상기 형성된 트렌치산화막에 식각공정을 실시하여, 상기 기판 상부를 드러내고 상기 쉘로우트렌치의 벽쪽에 벽산화막을 형성하는 제3단계; 및, 상기 기판과 상기 벽산화막의 증착율차이를 이용할 수 있는 소정의 매립물질로, 상기 쉘로우트렌치를 매립하여 트렌치매립층을 형성하는 제4단계를 포함한다.Depositing a predetermined film for the process on the substrate and forming a shallow trench; A second step of forming a trench oxide film on the formed shallow trench surface; Performing an etching process on the formed trench oxide film to expose an upper portion of the substrate and to form a wall oxide film on a wall of the shallow trench; And a fourth step of forming a trench buried layer by filling the shallow trench with a predetermined buried material that can use a difference in deposition rate between the substrate and the wall oxide film.

이하 도면들을 참조하여 본 발명의 바람직한 실시예를 자세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1 내지 도 3는 본 발명의 일실시예에 따른 쉘로우트렌치분리 형성방법을 설명하기 공정도이다.1 to 3 is a process chart illustrating a method of forming a shallow trench separation according to an embodiment of the present invention.

APCVD O3/TEOS USG는 하지막(base material) 의존성이 있어서 하지막에 따라 막(film)의 증착속도 등이 다르게 나타난다. 즉 하지막이 실리콘기판인 경우와 열산화막(Thermal Oxide)인 경우에, 같은 조건으로 APCVD O3/TEOS USG를 증착한 후 비교하면, 하지막이 실리콘기판인 경우가 막의 증착율이 빠르고 막의 농도도 높다. 일예로, 오존농도가 5%인 O3/TEOS USG의 증착속도는, 하지막이 실리콘기판인 경우 1300Å/min인 반면, 하지막이 열산화막인 경우는 600Å/min으로 2배 이상 증착속도 차이가 난다. 이러한 차이는 하지막의 특성에 기인하는 데, 실리콘기판의 경우는 소수성적 특성을 나타내고 열산화막은 친수성적 특성을 나타내기 때문이다. 오존(O3)과 반응하여 USG를 만드는 TEOS의 경우 화학구조상 소수성적 특성을 가지고있다. 따라서, 친수성적 특성을 가지는 열산화막위에서 TEOS의 증착반응이 어려우며, 따라서 증착속도 및 막의 농도가 떨어진다.Since APCVD O 3 / TEOS USG has a base material dependency, the deposition rate of a film varies depending on the base film. In other words, when the base film is a silicon substrate and a thermal oxide film, when the APCVD O 3 / TEOS USG is deposited under the same conditions, the deposition rate of the film is fast and the film concentration is high. For example, the deposition rate of O 3 / TEOS USG with an ozone concentration of 5% is 1300 mW / min when the underlying film is a silicon substrate, while the deposition rate is more than twice that when the underlying film is a thermal oxide film at 600 mW / min. . This difference is due to the properties of the underlying film, since the silicon substrate exhibits hydrophobic properties and the thermal oxide film exhibits hydrophilic properties. TEOS, which reacts with ozone (O 3 ) to produce USG, has a hydrophobic character due to its chemical structure. Therefore, it is difficult to deposit TEOS on the thermal oxide film having hydrophilic properties, and thus the deposition rate and the film concentration are reduced.

도 1에 도시한 바와 같이, 본 실시예의 공정은 먼저 실리콘기판(10)상부에 질화막(12)을 형성한다. 이 질화막은 향후 공정시 각 층의 분리 등을 원할히 하기 위해 형성시키는 것이다. 이 후 패턴 및 식각공정을 통하여 트렌치(14)를 형성한다. 이 후 트렌치에 장벽산화막을 약 200∼300Å의 두께로, 평면산화막을 약 100Å의 두께로 증착시켜 트렌치산화막(16)을 형성한다.As shown in FIG. 1, the process of this embodiment first forms a nitride film 12 on the silicon substrate 10. FIG. This nitride film is formed to facilitate separation of each layer in a future process. Thereafter, the trench 14 is formed through a pattern and an etching process. Thereafter, the trench oxide film 16 is formed by depositing a barrier oxide film in the trench at a thickness of about 200 to 300 占 퐉 and a planar oxide film at a thickness of about 100 占 Å.

이 후 도 2와 같이 트렌치(14)의 벽쪽에 스페이서와 같은 형태로 열산화막(18)이 남고 트렌치 바닥의 실리콘기판(10)이 나타나도록, 블랭킷 식각공정을 실시한다.After that, as shown in FIG. 2, a blanket etching process is performed such that the thermal oxide film 18 remains on the wall side of the trench 14 and the silicon substrate 10 at the bottom of the trench appears.

이 후 도 3과 같이, 4∼7%의 고농도 오존(O3)으로 APCVD방식에 따라 O3/TEOS USG를 증착하여 트렌치매립층(20)을 형성한다. 이 공정은 약 400∼530℃의 증착온도범위에서, 상기 트렌치(14)가 충분히 매립되도록 약 6000-10000Å두께로 매립한다.Thereafter, as shown in FIG. 3, the trench buried layer 20 is formed by depositing O 3 / TEOS USG with high concentration ozone (O 3 ) of 4 to 7% according to the APCVD method. In this process, the trench 14 is buried to a thickness of about 6000-10000 mm so that the trench 14 is sufficiently buried in a deposition temperature range of about 400 to 530 ° C.

이러한 증착공정에서 오존(O3)의 농도가 높을수록 O3/TEOS USG의 하지막 의존성이 높아진다. 본 발명은 전술한 바와 같이 이러한 하지막 의존성에 따라 트렌치의 바닥과 벽면의 증착속도가 차이가 나는 것을 이용하는 특징이 있다. 즉 트렌치(14) 매립시 증착공정은 트렌치(14)의 바닥쪽이 벽면보다 빠르게 진행되므로, 종래와 같은 보이드나 이음새(seam) 등의 발생을 방지할 수 있다. 뿐만아니라,후속 CMP 공정시 쉘로우트렌치에 보이드나 이음새(seam) 등에 의해 야기되는 피트(pit)등을 예방하기 때문에, 폴리실리콘층의 에칭시 발생될 결함을 방지할 수 있다.In this deposition process, the higher the concentration of ozone (O 3 ), the higher the underlying film dependency of O 3 / TEOS USG. The present invention is characterized in that the deposition rate of the bottom and the wall of the trench is different according to the underlying film dependency as described above. In other words, when the trench 14 is buried, the bottom side of the trench 14 proceeds faster than the wall surface, and thus, generation of voids or seams, etc. can be prevented. In addition, since a pit or the like caused by voids or seams is prevented in the shallow trench during the subsequent CMP process, defects to be generated during etching of the polysilicon layer can be prevented.

전술한 바와 같이, 본 발명은 하지막의 특성에 따른 증착속도 사이를 이용하도록 상압CVD방식으로 O3/TEOS USG를 사용하여 트렌치를 매립함으로써, STI가 적용되는 반도체소자의 특성을 향상시키고 고집적화를 실현하는 효과가 있다.As described above, the present invention improves the characteristics and high integration of semiconductor devices to which STI is applied by filling trenches using O 3 / TEOS USG by atmospheric CVD to use the deposition rate according to the characteristics of the underlying film. It is effective.

Claims (9)

쉘로우 트렌치 분리를 형성하기 위한 공정에 있어서,In the process for forming the shallow trench isolation, 기판 상부에 상기 공정을 위한 소정막을 증착하고 쉘로우트렌치를 형성하는 제1단계;Depositing a predetermined film for the process on the substrate and forming a shallow trench; 상기 형성된 쉘로우트렌치 표면에 트렌치산화막을 형성하는 제2단계;A second step of forming a trench oxide film on the formed shallow trench surface; 상기 형성된 트렌치산화막에 식각공정을 실시하여, 상기 기판 상부를 드러내고 상기 쉘로우트렌치의 벽쪽에 벽산화막을 형성하는 제3단계; 및,Performing an etching process on the formed trench oxide film to expose an upper portion of the substrate and to form a wall oxide film on a wall of the shallow trench; And, 상기 기판과 상기 벽산화막의 증착율차이를 이용할 수 있는 소정의 매립물질로, 상기 쉘로우트렌치를 매립하여 트렌치매립층을 형성하는 제4단계를 포함하는 것을 특징으로 하는, 하지막 의존성을 이용한 쉘로우트렌치분리 형성방법.And forming a trench buried layer by filling the shallow trench with a predetermined buried material that can use a difference in deposition rate between the substrate and the wall oxide film. Way. 제 1항에 있어서, 상기 쉘로우트렌치분리 형성방법은The method of claim 1, wherein the shallow trench isolation method 상기 소정의 매립물질에 의해 상기 기판 상부가 상기 쉘로우트렌치의 벽보다 빠르게 증착시키는 것을 특징으로 하는, 하지막 의존성을 이용한 쉘로우트렌치분리 형성방법.And depositing an upper portion of the substrate faster than the walls of the shallow trenches by the predetermined buried material. 제 1항에 있어서, 상기 제2단계는The method of claim 1, wherein the second step 상기 쉘로우트렌치에 장벽산화막 및 평면산화막을 형성하는 것을 특징으로 하는, 하지막 의존성을 이용한 쉘로우트렌치분리 형성방법.A method of forming a shallow trench separation using a dependency of an underlying film, characterized in that a barrier oxide film and a planar oxide film are formed in the shallow trench. 제 1항 또는 제 3항에 있어서, 상기 제2단계는The method of claim 1 or 3, wherein the second step 상기 쉘로우트렌치에 장벽산화막은 200Å∼300Å정도로, 평면산화막은 100Å 정도로 형성시키는 것을 특징으로 하는, 하지막 의존성을 이용한 쉘로우트렌치분리 형성방법.2. The shallow trench isolation method using the underlying film dependency of the shallow trench, wherein the barrier oxide film is formed at about 200 kPa to about 300 kPa and the planar oxide film is about 100 kPa. 제 1항에 있어서, 상기 제3단계는The method of claim 1, wherein the third step 블랭킷 식각방법으로 상기 식각공정을 실시하는 것을 특징으로 하는, 하지막 의존성을 이용한 쉘로우트렌치분리 형성방법.A method of forming a shallow trench isolation using underlayer dependence, characterized in that the etching process is performed by a blanket etching method. 제 1항에 있어서, 상기 제3단계는The method of claim 1, wherein the third step 상기 벽화막이 열산화막인 것을 특징으로 하는, 하지막 의존성을 이용한 쉘로우트렌치분리 형성방법.Shallow trench separation forming method using the dependence of the underlying film, characterized in that the mural film is a thermal oxidation film. 제 1항에 있어서, 상기 제4단계는The method of claim 1, wherein the fourth step 소정의 매립물질로 O3/TEOS USG를 사용하여 상기 쉘로우트렌치를 매립하는 것을 특징으로 하는, 하지막 의존성을 이용한 쉘로우트렌치분리 형성방법.A method of forming a shallow trench isolation using underlying film dependency, characterized in that the shallow trench is buried using O 3 / TEOS USG as a predetermined embedding material. 제 7항에 있어서, 상기 제4단계는8. The method of claim 7, wherein the fourth step is 오존(O3)농도가 4％∼7％인 O3/TEOS USG를 이용하는 것을 특징으로 하는, 하지막 의존성을 이용한 쉘로우트렌치분리 형성방법.A method for forming shallow trench isolation using underlayer dependence, characterized by using O 3 / TEOS USG having an ozone (O 3 ) concentration of 4% to 7%. 제 8항에 있어서, 상기 제4단계는The method of claim 8, wherein the fourth step 약 400∼530℃의 온도범위에서 APCVD방식에 따라 약 6000∼10000Å두께로 매립하는 것을 특징으로 하는, 하지막 의존성을 이용한 쉘로우트렌치분리 형성방법.A method for forming shallow trench isolation using underlying film dependence, characterized in that it is buried at a thickness of about 6000 to 10000 kPa in accordance with the APCVD method in the temperature range of about 400 to 530 ° C.
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CN101989564B (en) * 2009-07-31 2012-09-26 中芯国际集成电路制造(上海)有限公司 Method for reducing corner defect of isolation channel of shallow trench
US8347076B2 (en) 2003-12-01 2013-01-01 Samsung Electronics Co., Ltd. System and method for building home domain using smart card which contains information of home network member device

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JPH04151850A (en) * 1990-10-15 1992-05-25 Nec Corp Manufacturing method of trench dielectric isolation type semiconductor integrated circuit
EP0631306B1 (en) * 1993-06-23 2000-04-26 Siemens Aktiengesellschaft Process for manufacturing an isolation region in a substrate for smart-power-technology
KR0165454B1 (en) * 1995-10-25 1999-02-01 김광호 Method for trench isolation
KR19980083840A (en) * 1997-05-19 1998-12-05 윤종용 Device isolation by selective epitaxial growth
KR19990025195A (en) * 1997-09-11 1999-04-06 윤종용 Trench element isolation

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8347076B2 (en) 2003-12-01 2013-01-01 Samsung Electronics Co., Ltd. System and method for building home domain using smart card which contains information of home network member device
CN101989564B (en) * 2009-07-31 2012-09-26 中芯国际集成电路制造(上海)有限公司 Method for reducing corner defect of isolation channel of shallow trench

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