CN101989564A - Method for reducing corner defect of isolation channel of shallow trench - Google Patents
Method for reducing corner defect of isolation channel of shallow trench Download PDFInfo
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- CN101989564A CN101989564A CN2009100557616A CN200910055761A CN101989564A CN 101989564 A CN101989564 A CN 101989564A CN 2009100557616 A CN2009100557616 A CN 2009100557616A CN 200910055761 A CN200910055761 A CN 200910055761A CN 101989564 A CN101989564 A CN 101989564A
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Abstract
The invention discloses a method for reducing corner defects of an isolation channel of a shallow trench, which comprises the following steps: forming a pad oxide layer, a silicon nitride layer and a photoresist layer on a semiconductor substrate in sequence; after the exposure development process is carried out, taking the photoresist layer as a mask to etch the silicon nitride layer, the pad oxide layer and the semiconductor substrate to form the shallow trench; when the shallow trench is formed, depositing an insulating barrier by using chemical vaporous deposition at low rate of deposition; clearing the insulating barrier on the silicon nitride layer through the process of chemically mechanical polishing; and then removing the silicon nitride layer and the pad oxide layer to form the isolation channel of the shallow trench. By using the method of the invention, the corner defects of the isolation channel of the shallow trench are effectively reduced.
Description
Technical field
The present invention relates to the manufacturing technology of semiconductor components and devices, refer in particular to a kind of method that reduces the corner defective of shallow trench isolation channels.
Background technology
Develop rapidly along with semiconductor technology; (CD) is more and more littler for the characteristic size of semiconductor components and devices; the density of active device is more and more higher on the unit are of Semiconductor substrate; distance between each active device is also more and more littler, thereby makes the insulation insulation blocking between each device also become more important.Wherein, shallow trench isolation channels (STI, Shallow Trench Isolation) technology is the most frequently used isolation technology that degree of depth submicron integrated circuit (IC) is made that is used for, and actual applicable cases is verified, in the STI technology, the drift angle shape of sti structure has very big influence for the overall performance of components and parts.
Fig. 1 is the schematic diagram that forms the shallow trench isolation channels structure in the prior art.Shown in Fig. 1 (a), at first on Semiconductor substrate 100, form pad oxide (Pad Oxide) 102, silicon nitride layer 104 and photoresist layer 106 successively respectively, then by exposure imaging technology, definition shallow trench isolation channels figure, and be mask with photoresist layer 106, with dry etching method etch silicon nitride (SiN) layer 104, pad oxide 102 and Semiconductor substrate 100, thereby form shallow trench 108.Then, shown in Fig. 1 (b), by high density plasma CVD method (HDPCVD, High Density Plasma Chemical VaporDeposition) or high-aspect-ratio technology (HARP) on silicon nitride layer 104, form insulating barrier 110, and described insulating barrier 110 is filled described shallow trench 108 full.Then, shown in Fig. 1 (c), insulating barrier 110 is carried out planarization, for example, adopt the insulating barrier 110 on CMP (Chemical Mechanical Polishing) process (CMP, Chemical MechanicalPolishing) the removing silicon nitride layer 104; And then, finally form sti structure by wet etching (Wet Etch) removal silicon nitride layer 104 and pad oxide 102, wherein, the lattice portion branch is depicted as active area (AA, Active Area).Yet, more serious defective often appears when adopting above-mentioned technical process to form the shallow trench isolation channels structure.Be above-mentioned shallow trench isolation channels structure schematic diagram when defective occurring shown in Fig. 1 (d), compare with Fig. 1 (c), corner defective (smear defect) has appearred in the shallow trench isolation channels structure corners place among Fig. 1 (d), the existence of this shallow trench isolation channels structure corners defective causes possible leakage of current (Current Leakage) or kink effect (Kink Effect) easily, thereby the electric property of semiconductor components and devices is caused bigger adverse effect.For example, for non-volatile memory device, even very little leakage of current is also with the very big data retentivity and the circulation durability that must reduce this non-volatile memory device.Therefore, Xiang Guan technical staff are striving to find the method that can effectively reduce and remove the corner defective of shallow trench isolation channels.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of method that reduces the corner defective of shallow trench isolation channels, thereby reduces the corner defective of shallow trench isolation channels effectively.
For achieving the above object, the technical scheme among the present invention is achieved in that
A kind of method that reduces the corner defective of shallow trench isolation channels, this method comprises:
Forming pad oxide, silicon nitride layer and photoresist layer on Semiconductor substrate successively, after carrying out exposure imaging technology, is that mask carries out etching to described silicon nitride layer, pad oxide and Semiconductor substrate with the photoresist layer, forms shallow trench;
After forming described shallow trench, use the chemical vapour deposition technique depositing insulating layer of low deposition rate;
Remove insulating barrier on the described silicon nitride layer by the CMP (Chemical Mechanical Polishing) process process; And then remove described silicon nitride layer and pad oxide, form the shallow trench isolation channels structure.
Deposition rate in the described chemical vapour deposition technique be 1500～2100 dusts/minute.
When using the chemical vapour deposition technique depositing insulating layer of low deposition rate, employed gas is silane, and the gas flow of this gas is 60～110 cc/min.
The described insulating barrier of removing on the described silicon nitride layer by the CMP (Chemical Mechanical Polishing) process process comprises:
Remove insulating barrier on the described silicon nitride layer by the CMP (Chemical Mechanical Polishing) process process of low downforce.
Downforce in the described CMP (Chemical Mechanical Polishing) process process is 1.2～1.8 pounds/square inch
In summary, provide a kind of method that reduces the corner defective of shallow trench isolation channels among the present invention.In the method for the corner of described minimizing shallow trench isolation channels defective, owing to use the chemical vapour deposition technique depositing insulating layer of low deposition rate, and can therefore can reduce effectively by the insulating barrier on the CMP (Chemical Mechanical Polishing) process process removing silicon nitride layer of low downforce until the corner defective of eliminating shallow trench isolation channels fully.
Description of drawings
Fig. 1 is the schematic diagram that forms the shallow trench isolation channels structure in the prior art, comprises Fig. 1 (a)～(d).
Fig. 2 is the schematic flow sheet of the method for the corner defective of minimizing shallow trench isolation channels among the present invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention express clearlyer, the present invention is further described in more detail below in conjunction with drawings and the specific embodiments.
Before introducing method provided by the invention, need to introduce in detail earlier process and the reason that described Smear Defect produces, for for simplicity, still be that example describes with Fig. 1:
At first, shown in Fig. 1 (b), utilizing HDPCVD method depositing insulating layer 110 on silicon nitride layer 104 and formed shallow trench 108, make described insulating barrier 110 that described shallow trench 108 is filled in the full process, because the shape of the corner location of described silicon nitride layer 104 is comparatively sharp-pointed, therefore in the process of the above-mentioned insulating barrier 110 of deposition, the corner location of described silicon nitride layer 104 is whole silicon nitride layer 104 stressed positions of concentrating the most; And, because its shape is comparatively sharp-pointed, the insulating barrier that also occurs easily being deposited interconnects the phenomenon of adhering to defective tightness with the corner location of silicon nitride layer, thereby makes that the density of the insulating barrier that deposits in the corner location place of described silicon nitride layer 104 is less and structure is more loose; In addition, when using the HDPCVD method on silicon nitride layer 104 and formed shallow trench 108 during depositing insulating layer 110, because employed deposition rate (dep rate) is than very fast, be generally 3000 dusts/minute (A/min), thereby make that the compression (stress) at interface place of the insulating barrier that deposited and AA is generally all bigger in formed shallow trench 108, thereby be easy to generate the phenomenon of delaminate (peeling off), thereby produce corner defective (smear defect) at the corner location of above-mentioned shallow trench isolation channels easily.
Secondly, when the insulating barrier 110 to deposition shown in Fig. 1 (c) carries out CMP, the insulating barrier 110 of silicon nitride layer 104 tops all need be removed.And in above-mentioned CMP process, (Down force) is bigger for employed downforce, be generally 4 pounds/square inch (psi), less, the short texture of insulating barrier density at the corner location place of described silicon nitride layer in addition, and the compression at the interface place of silicon nitride layer that is deposited and AA is bigger, therefore under the effect of the mechanical lapping of the big downforce in the CMP process, the structure of the insulating barrier at the corner location place of described silicon nitride layer is destroyed easily, thereby easily in the corner location generation corner of above-mentioned shallow trench isolation channels defective.
In addition, after carrying out the CMP process, also need remove silicon nitride layer 104 and pad oxide 102 by Wet Etch.Because less, the short texture of insulating barrier density at the corner location place of described silicon nitride layer, therefore in above-mentioned Wet Etch process, the corner location of above-mentioned shallow trench isolation channels will further be destroyed by employed acid solution burn in the Wet Etch process, thereby produces the corner defective at the corner location of above-mentioned shallow trench isolation channels.
According to above-mentioned analysis, in technical scheme of the present invention, a kind of method that reduces the corner defective of shallow trench isolation channels has been proposed to described corners of shallow-channel isolation groove generation of defects reason.Fig. 2 is the schematic flow sheet of the method for the corner defective of minimizing shallow trench isolation channels among the present invention.As shown in Figure 2, the method for the corner defective of the minimizing shallow trench isolation channels that is provided among the present invention comprises step as described below:
In this step, will at first form pad oxide, silicon nitride layer and photoresist layer successively respectively on Semiconductor substrate, wherein, described Semiconductor substrate can be silicon base or other insulating material, and the material of described pad oxide is SiO
2, the material of described silicon nitride layer is a silicon nitride; Then by exposure imaging technology, definition shallow trench figure, and be mask with the photoresist layer, with dry etching method etch silicon nitride layer, pad oxide and Semiconductor substrate, thereby form a groove.After forming described groove, also can remove photoresist layer, and then remove residual photoresist layer with the wet etching method by the ashing treatment process, finally form required shallow trench.
In this step, will use the chemical vapour deposition technique (for example, the HDPCVD of low deposition rate) of low deposition rate on silicon nitride layer, to form insulating barrier, and described insulating barrier can be filled described shallow trench full; The material of described insulating barrier is generally silicon dioxide.In addition, in an embodiment of the present invention, when using the chemical vapour deposition technique depositing insulating layer of low deposition rate, employed gas can be silane (SiH
4), the gas flow of this gas can be 60～110 cc/min (SCCM).
Wherein, the deposition rate of described CVD is 1500～2100A/min; Preferable, the deposition rate of described CVD is 1800A/min.Because the deposition rate of above-mentioned CVD is far below deposition rate of the prior art, therefore make that the density of formed insulating barrier is big and structure is dense, reduce the compression at the interface place of the insulating barrier that deposited and AA, thereby can avoid producing the phenomenon of delaminating as far as possible; Simultaneously, the possibility that the corner location that has also reduced above-mentioned shallow trench isolation channels is destroyed by employed acid solution burn in the Wet Etch process, and then can alleviate even eliminate the corner defective that corner location produced at above-mentioned shallow trench isolation channels.
In this step, can use the insulating barrier on the CMP process removing silicon nitride layer commonly used, and after removing silicon nitride layer and pad oxide, finally form the shallow trench isolation channels structure.Concrete CMP process does not repeat them here.
Prove through experimental data, adopt in the resulting wafer of technological process (wafer) of formation STI of the prior art, Smear Defect detected in the sample area of setting is generally about 28～58, and among the resulting wafer of method of the corner defective of the minimizing shallow trench isolation channels of stating in the use, Smear Defect detected in onesize sample area is generally at 8～9.This shows that the method for the corner defective of the minimizing shallow trench isolation channels that is proposed among the present invention can be eliminated the corner defective that corner location produced at above-mentioned shallow trench isolation channels effectively.
In addition, in an embodiment of the present invention, can also further improve above-mentioned steps 203, amended step is:
Step 203 ', by the insulating barrier on CMP (Chemical Mechanical Polishing) process (CMP) the process removing silicon nitride layer of low downforce; And then remove silicon nitride layer and pad oxide, finally form the shallow trench isolation channels structure.
In this step, will carry out planarization, promptly adopt the insulating barrier on the CMP technical process removing silicon nitride layer with low downforce described insulating barrier.Then, again by removal method (for example, Wet Etch) commonly used; Remove silicon nitride layer 304 and pad oxide 302, thereby form required shallow trench isolation channels structure.Wherein, employed downforce is 1.2～1.8psi in the described CMP process with low downforce; Preferable, employed downforce is 1.5psi in the described CMP process.In addition, except the numerical value of above-mentioned downforce, other parameter in the CMP process of above-mentioned low downforce is identical with employed other corresponding parameter in the CMP process of using always, promptly in the CMP of above-mentioned low downforce process, can directly use other parameter except that downforce in the CMP process commonly used.
Because the downforce of the downforce in the above-mentioned CMP process in the CMP process of the prior art, therefore make that the structure of insulating barrier at corner location place of silicon nitride layer is destroyed not too easily, thereby can further avoid producing the corner defective at the corner location of above-mentioned shallow trench isolation channels.
Prove that through experimental data among the resulting wafer of method of the corner defective of the minimizing shallow trench isolation channels of stating in the use, Smear Defect detected in onesize sample area is generally about 0～2.This shows that the method for the corner defective of the minimizing shallow trench isolation channels that is proposed among the present invention can significantly reduce even eliminate fully the corner defective that corner location produced at above-mentioned shallow trench isolation channels.
In the method for the corner defective of above-mentioned minimizing shallow trench isolation channels, owing to use the chemical vapour deposition technique depositing insulating layer of low deposition rate, and can be by the insulating barrier on the CMP (Chemical Mechanical Polishing) process process removing silicon nitride layer of low downforce, therefore can significantly reduce even eliminate fully the corner defective that corner location produced at above-mentioned shallow trench isolation channels, lack adverse effect thereby reduced described corner, improved the performance of semiconductor components and devices the electric property of semiconductor components and devices.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. method that reduces the corner defective of shallow trench isolation channels is characterized in that this method comprises:
Forming pad oxide, silicon nitride layer and photoresist layer on Semiconductor substrate successively, after carrying out exposure imaging technology, is that mask carries out etching to described silicon nitride layer, pad oxide and Semiconductor substrate with the photoresist layer, forms shallow trench;
After forming described shallow trench, use the chemical vapour deposition technique depositing insulating layer of low deposition rate;
Remove insulating barrier on the described silicon nitride layer by the CMP (Chemical Mechanical Polishing) process process; And then remove described silicon nitride layer and pad oxide, form the shallow trench isolation channels structure.
2. method according to claim 1 is characterized in that,
Deposition rate in the described chemical vapour deposition technique be 1500～2100 dusts/minute.
3. method according to claim 1 is characterized in that,
When using the chemical vapour deposition technique depositing insulating layer of low deposition rate, employed gas is silane, and the gas flow of this gas is 60～110 cc/min.
4. method according to claim 1 is characterized in that, the described insulating barrier of removing on the described silicon nitride layer by the CMP (Chemical Mechanical Polishing) process process comprises:
Remove insulating barrier on the described silicon nitride layer by the CMP (Chemical Mechanical Polishing) process process of low downforce.
5. method according to claim 4 is characterized in that,
Downforce in the described CMP (Chemical Mechanical Polishing) process process is 1.2～1.8 pounds/square inch.
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| CN200910055761A CN101989564B (en) | 2009-07-31 | 2009-07-31 | Method for reducing corner defect of isolation channel of shallow trench |
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| CN200910055761A CN101989564B (en) | 2009-07-31 | 2009-07-31 | Method for reducing corner defect of isolation channel of shallow trench |
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| TW347575B (en) * | 1997-06-30 | 1998-12-11 | Taiwan Semiconductor Mfg Co Ltd | Method for forming shallow trench isolation region by selective wet etching |
| TW399295B (en) * | 1998-08-25 | 2000-07-21 | United Microelectronics Corp | Manufacturing method of shallow trench isolation |
| US6180490B1 (en) * | 1999-05-25 | 2001-01-30 | Chartered Semiconductor Manufacturing Ltd. | Method of filling shallow trenches |
| US6541401B1 (en) * | 2000-07-31 | 2003-04-01 | Applied Materials, Inc. | Wafer pretreatment to decrease rate of silicon dioxide deposition on silicon nitride compared to silicon substrate |
| KR100419869B1 (en) * | 2000-08-02 | 2004-02-25 | 주식회사 하이닉스반도체 | Method for forming shallow trench isolation |
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Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20121116 |
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Effective date of registration: 20121116 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Patentee after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |