CN1180467C - Rear shallow groove isolating process - Google Patents
Rear shallow groove isolating process Download PDFInfo
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- CN1180467C CN1180467C CNB021297525A CN02129752A CN1180467C CN 1180467 C CN1180467 C CN 1180467C CN B021297525 A CNB021297525 A CN B021297525A CN 02129752 A CN02129752 A CN 02129752A CN 1180467 C CN1180467 C CN 1180467C
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Abstract
The invention provides a rear shallow groove isolating process. At first, an impure well region is formed at an upper surface of a substrate, and an oxide and a polycrystal silicon layer are orderly formed on the upper surface of the substrate. Subsequently, the polycrystal silicon layer is etched to form a gate in the impure well region, and a drain/source region is formed at two sides of the gate. Thereafter, a first dielectric layer is formed on the substrate to cover the impure well region, the gate and regions except for the impure well region, after that, a second dielectric layer having an approximate flat surface is formed to cover the first dielectric layer. Then a photoresist layer is formed on the second dielectric layer to cover the impure well region, the second dielectric layer, the first dielectric layer and the substrate at outside of the impure well region are eteched to configure a trench region. Finally, the photoresist layer is removed, a third dielectric layer is deposited to be filled in the trench region and cover the second dielectric layer.
Description
Technical field
The invention provides a kind of back shallow-trench isolation (post shallow trench isolation, post-STI) process, form element earlier, form the insulated trench zone again, relate in particular to a kind of shallow slot corner areas of avoiding and produce recessed latent rear shallow groove isolating process.
Background technology
In semiconductor technology; have good isolation in order to make on the chip between each electronic component; produce short circuit phenomenon to avoid the mutual interference of element phase; generally all adopt the selective oxidation method (localizedoxidation isolation, LOCOS) or method of shallow trench isolate with the protection.Because the occupied area of chip of field oxide (field oxide) that produces in the LOCOS technology is too big, and generative process can be followed the generation of beak (bird ' s beak) phenomenon, and therefore the semiconductor technology of live width below 0.25 μ m nearly all adopts method of shallow trench at present.Method of shallow trench is to make a shallow slot and insert megohmite insulant to produce the effect that electricity is isolated at each interelement of chip surface.
Please refer to Fig. 1 to Fig. 3, Fig. 1 to Fig. 3 is existing method of shallow trench schematic diagram.Existing method generally all is to carry out shallow-trench isolation earlier, and then carries out the making of semiconductor element.As shown in Figure 1, semiconductor chip 10 includes a silicon substrate 12, and one silica layer (silicon oxide) 14 is located on the silicon substrate 12, and a silicon nitride layer (silicon nitride) 16 is deposited on the silicon oxide layer 14.Silicon oxide layer 14 and silicon nitride layer 16 are used for respectively as buffer oxide layer of subsequent technique (pad oxide) and mask (mask).Existing making shallow slot isolation method is to utilize photoetching (photolithography) and anisotropic dry etching technologies such as (anisotropic dry etching) earlier, in semiconductor chip 10 lip-deep presumptive areas, form a shallow slot 18, and make shallow slot 18 pass silicon nitride layer 16 and silicon oxide layer 14 gos deep in the silicon substrate 12 to certain depth.
Subsequently, as shown in Figure 2, because the surface that isolates shallow slot 18 is through after the etching, may form part of lattice defects, therefore utilize an oxidation technology again, in one 800 ℃ to 1000 ℃ high temperature furnace pipe, carry out one and feed the dry type oxidation of purity oxygen or the wet oxidation of aerating oxygen and water vapour, form a lining oxide layer (liner oxide layer) 22 with 12 surfaces of the silicon substrate in isolating shallow slot 18, and make and isolate shallow slot 18 and STI corner 23 between silicon substrate 12 surfaces and be oxidized into the profile of slyness, promptly " corner slynessization " (corner-rounding).Carry out a high density plasma CVD (high-density plasma chemical vapor deposition subsequently, HDPCVD) technology, be formed uniformly a HDP oxide layer 20 in semiconductor chip 10 surfaces and fill up shallow slot 18, be used as megohmite insulant, shallow slot 18 reached isolate electrical effect.(chemical mechanical polishing CMP), removes a part of dielectric layer 20, the surface of planarization semiconductor chip 10 then to utilize chemico-mechanical polishing.
At last as shown in Figure 3, utilize existing chemical solvent, for example hot phosphoric acid is removed silicon nitride layer 16 fully, finishes shallow grooved-isolation technique.
Yet existing method of shallow trench has several shortcomings:
1). existing method of shallow trench step is numerous and diverse, thereby cost is higher;
2). when utilizing chemical solvent to remove silicon nitride layer 16 fully, can produce oxide layer depression (oxide-recesses portion) at shallow slot corner areas 23 places in shallow slot zone 18.When follow-up generation grid oxic horizon, easily in shallow slot corner areas 23 places grid oxic horizon thinning phenomenon (gate oxidethinning), and the electric isolating effect of reduction shallow-trench isolation, and then cause the semiconductor element electric energy undesired, for example the Id/Vg curve produces not good two protuberances (double hump) variation, reduces the reliability of product;
3). existing method of shallow trench need additionally carry out corner slynessization step; And
4). existing method of shallow trench uses the CMP method, causes the damage of silicon substrate easily, is easy to generate the saucer effect simultaneously.
Summary of the invention
So main purpose of the present invention is to provide a kind of back shallow-trench isolation, and (post shallow trenchisolation, process post-STI) is to solve the problem of above-mentioned existing manufacture method.
In a preferred embodiment of the invention, a substrate has a upper surface.At first carry out one first ion implantation technology, to form a doped well region in this substrate top surface.Then form an oxide layer and a polysilicon layer in regular turn in this substrate top surface, this polysilicon layer of etching again is to form a grid in this doped well region.Carry out one second ion implantation technology subsequently, form a drain/source zone with these grid both sides in this doped well region.Then on this substrate, form one first dielectric layer, covering the zone beyond this doped well region, this grid and this doped well region, and form second dielectric layer with surface of a flat subsequently, to cover this first dielectric layer.On this second dielectric layer, form a photoresist layer afterwards covering this doped well region, and expose the zone beyond this doped well region.Then carry out a dry method etch technology, this second dielectric layer, this first dielectric layer and this substrate in the zone beyond this doped well region of etching are to form a trench region.Afterwards in removing this photoresist layer, and after depositing one the 3rd dielectric layer and inserting this trench region and be covered on this second dielectric layer, deposit a doped silicate glass layer and be covered on the 3rd dielectric layer.At last this doped silicate glass layer is carried out a hot-fluid and handle, and utilize a chemico-mechanical polishing (chemical mechanical polishing, CMP) technology, this doped silicate glass layer of planarization.
In another embodiment of the present invention, a substrate has an active region, and is formed with semiconductor element in this active region.At first on this substrate, form one first dielectric layer, and form subsequently one have a flat the surface second dielectric layer and cover this first dielectric layer.Then on this second dielectric layer, form the patterning photoresist layer of this active region of covering, to expose this active region zone in addition.Remove this second dielectric layer and this first dielectric layer and this substrate in the zone beyond this active region afterwards, forming a trench region, and remove this patterning photoresist layer immediately.Depositing one the 3rd dielectric layer afterwards inserts this trench region and is covered on this second dielectric layer.In a specific embodiment of the present invention, after abovementioned steps, deposit a doped silicate glass layer to be covered on the 3rd dielectric layer, at last this doped silicate glass layer is carried out a hot-fluid and handle, and utilize a CMP (Chemical Mechanical Polishing) process, this doped silicate glass layer of planarization.
Because manufacture method of the present invention is after the making of finishing grid and depositing this first and second dielectric layer, carry out a dry method etch technology again and remove second dielectric layer in doped well region zone in addition, first dielectric layer and substrate, to form a trench region, therefore omitted corner slynessization (corner-rounding), remove multinomial technologies such as silicon nitride layer and acid soak cleaning, when shortening production time and cost, also can not cause oxide layer depression (oxide-recesses portion), depression flaw (spot) and oxidated layer thickness reduce the problem of (thinning), so can avoid time start voltage neck joint (sub-threshold kink) phenomenon, and semiconductor element conductivity is undesired, and for example the Id/Vg curve produces not good two protuberances (double hump) variation.
In a preferred embodiment of the present invention, the 3rd dielectric layer is one ozone-tetraethoxysilane (ozone-tetra-ethyl-ortho-silicate, O
3-TEOS) layer.
Description of drawings
Fig. 1 to Fig. 3 is existing method of shallow trench schematic diagram; And
Fig. 4 to Fig. 9 is a rear shallow groove isolating process schematic diagram of the present invention.
Description of reference numerals in the accompanying drawing is as follows:
10 semiconductor chips, 12 silicon substrates
14 silicon oxide layers, 16 silicon nitride layers
18 shallow slot 20HDP oxide layers
22 lining oxide layers, 23 shallow slot corner areas
30 semiconductor chips, 32 substrates
34 first ion implantation technologies, 36 doped well regions
38 oxide layers, 40 polysilicon layers
42 grids, 44 second ion implantation technologies
46 drain/sources zone, 50 first dielectric layers
51 second dielectric layers, 52 photoresist layers
56 trench regions 58 the 3rd dielectric layer
60 spaces, 62 doped silicate glass layers
Embodiment
A kind of back of the present invention shallow-trench isolation (post shallow trench isolation, process post-STI) is prior to making semiconductor element on the substrate, for example grid, MOS transistor are carried out shallow grooved-isolation technique again.The inventive method mainly has following step:
1). a substrate is provided, and this substrate has a upper surface;
2). carry out one first ion implantation technology, to form a doped well region in this substrate top surface;
3). form an oxide layer in this substrate top surface;
4). deposition one polysilicon layer on this oxide layer;
5). this polysilicon layer of etching, in this doped well region, to form a grid;
6). carry out one second ion implantation technology, form a drain region and one source pole zone with these grid both sides in this doped well region;
7). on this substrate, form one first dielectric layer,, form second dielectric layer with surface of a flat again, to cover this first dielectric layer to cover the zone beyond this doped well region, this grid and this doped well region;
8). form a photoresist layer on this second dielectric layer, this photoresist layer covers this doped well region and exposes this doped well region zone in addition, to define each shallow slot zone as area of isolation;
9). carry out a dry method etch technology, this first dielectric layer and this substrate in the zone beyond this doped well region of etching are to form this trench region as area of isolation;
10). remove this photoresist layer; And
11). deposit one the 3rd dielectric layer, this second dielectric layer fills in this trench region and is covered on this second dielectric layer.
Please refer to Fig. 4 to Fig. 9, Fig. 4 to Fig. 9 is shallow-trench isolation (post shallow trenchisolation, post-STI) the method schematic diagram of technology behind the present invention.Below promptly describe the preferred embodiments of the present invention in detail by Fig. 4 to Fig. 9.At first, as shown in Figure 4, semiconductor chip 30 includes a substrate 32 with a upper surface.At first carry out one first ion implantation technology 34, form a doped well region 36 with upper surface in substrate 32.Doped well region 36 is used in subsequent technique, as the active region of semiconductor element.
Then, as shown in Figure 5, form an oxide layer 38, and on oxide layer 38, deposit a polysilicon layer 40 in substrate 32 upper surfaces.Afterwards as shown in Figure 6, etching polysilicon layer 40 and oxide layer 38 are to form a grid 42 in doped well region 36.Carry out one second ion implantation technology 44 subsequently, form a drain/source zone 46 with 42 both sides of the grid in doped well region 36.
Then, as shown in Figure 7, on substrate 32, form one by a undoped silicate glass (undopedsilicate glass, USG) layer, or a non-boron phosphorus silicate glass (Borophos-phosilicate glass, BPSG) Ceng first dielectric layer 50 that oxide layer constituted is to cover the zone beyond doped well region 36, grid 42 and the doped well region 36, and form one subsequently by second dielectric layer 51 that bpsg layer constituted, to cover first dielectric layer 50.Wherein first dielectric layer 50 is that (plasma enhanced oxide, PEOX) layer can also be constituted by the silicon oxynitride (SiON) of 300 to 500 dusts in plasma reinforcement oxidation.The main application of first dielectric layer 50 is to protect substrate 32 surfaces and is formed on semiconductor element on the substrate 32.In addition, by carrying out a chemico-mechanical polishing (chemicalmechanical polishing, CMP) technology, the surface that can make second dielectric layer 51 have a flat.On first dielectric layer 50, form a photoresist layer 52 subsequently with covering doped well region 36, and expose the zone beyond the doped well region 36.Photoresist layer 52 can be called a STI photoresist, is used for defining sti region.
As shown in Figure 8, in carrying out a dry method etch technology, first dielectric layer 50 and the substrate 32 in the zone beyond the etching doped well region 36 after forming a trench region 56, are removed (stripping) photoresist layer 52.Deposit one the 3rd dielectric layer 58 immediately inserting trench region 56, and be covered on second dielectric layer 51.Wherein shallow slot zone 56 is formed with a space (air gap) 60 sometimes after inserting the 3rd dielectric layer 58.The formation in space 60 is because shallow slot zone 56 has a little draw ratio (aspect ratio), makes the 3rd dielectric layer 58 that fills in shallow slot zone 56 form the space naturally owing to overhang (overhang) effect.Draw ratio is defined as the degree of depth of shallow slot and the ratio of width.But space 60 is not the essential elements and the emphasis feature of the inventive method, and the principal character of the inventive method is to form earlier semiconductor element, and then forms shallow trench insulation.
As shown in Figure 9, depositing the 3rd dielectric layer 58 with after inserting trench region 56, also can deposit one by boron phosphorus silicate glass (borophosphosilicate glass, BPSG) or phosphosilicate glass (phosphosilicate glass, PSG) doped silicate glass layer 62 that is constituted, be covered on the 3rd dielectric layer 58, and doped silicate glass layer 62 carried out a hot-fluid handle (BPSG flowing).At last, utilize CMP (Chemical Mechanical Polishing) process planarization doped silicate glass layer 62, finish manufacture method of the present invention.
Compared with prior art, rear shallow groove isolating process of the present invention is in the making of finishing grid 42 and deposits first dielectric layer 50 that is made of the USG layer with after covering doped well region 36, grid 42 and doped well region 36 zone in addition, form one second dielectric layer 51 earlier to cover first dielectric layer 50, carry out a dry method etch technology again and remove second dielectric layer 51, first dielectric layer 50 and the substrate 32 in doped well region 36 zone in addition, to form a trench region 56.Owing to omitted corner slynessization (corner-rounding), remove multinomial technologies such as silicon nitride layer and acid soak cleaning, therefore when shortening production time and cost, can not cause the oxide layer depression (oxide-recesses portion) in the existing method of shallow trench, depression flaw (spot) and oxidated layer thickness reduce the problem of (thinning), and then avoid time start voltage neck to save (sub-threshold kink) phenomenon, and semiconductor element conductivity is undesired, and for example the Id/Vg curve produces not good two protuberances (doublehump) variation.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to the covering scope of patent of the present invention.
Claims (11)
1. rear shallow groove isolating process, this method includes the following step:
One substrate is provided, and this substrate has an active region, is formed with semiconductor element in this active region;
On this substrate, form one first dielectric layer;
Form one second dielectric layer covering this first dielectric layer, and the surface of this second dielectric layer with a flat;
Form a patterning photoresist layer on this second dielectric layer, this photoresist layer covers this active region, exposes this active region zone in addition;
Remove this second dielectric layer and this first dielectric layer and this substrate in this active region zone in addition, to form a trench region;
Remove this patterning photoresist layer; And
Deposit one the 3rd dielectric layer, the 3rd dielectric layer fills in this trench region and is covered on this second dielectric layer.
2. method as claimed in claim 1 wherein provides the step of this substrate also to comprise:
Carry out one first ion implantation technology on the upper surface of this substrate, to form a doped well region in this substrate top surface, this doped well region is as this active area;
Form an oxide layer in this substrate top surface;
Deposition one polysilicon layer on this oxide layer;
This polysilicon layer of etching is to form a grid in this doped well region; And
Carry out one second ion implantation technology, form a drain region and one source pole zone with these grid both sides in this doped well region.
3. as the method for claim 1 or 2, wherein this first dielectric layer is a undoped silicate glassy layer.
4. as the method for claim 1 or 2, wherein this second dielectric layer is a boron phosphorus silicate glass layer.
5. as the method for claim 1 or 2, wherein this first dielectric layer and the 3rd dielectric layer all are that a plasma is strengthened oxide layer.
6. as the method for claim 1 or 2, wherein this shallow slot zone is formed with a space after inserting the 3rd dielectric layer.
7. as the method for claim 1 or 2, wherein this method still includes the following step after deposition the 3rd dielectric layer:
Deposit a doped silicate glass layer, be covered on the 3rd dielectric layer;
This doped silicate glass layer is carried out a hot-fluid to be handled; And
This doped silicate glass layer of planarization.
8. method as claimed in claim 7, wherein this doped silicate glass layer is a boron phosphorus silicate glass layer.
9. method as claimed in claim 7, wherein this doped silicate glass layer is a phosphosilicate glass layer.
10. method as claimed in claim 7, wherein the method for this doped silicate glass layer of planarization is to utilize a CMP (Chemical Mechanical Polishing) process.
11. as the method for claim 1 or 2, wherein the 3rd dielectric layer is one ozone-tetraethoxysilane layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US68384902A | 2002-02-22 | 2002-02-22 | |
| US09/683,849 | 2002-02-22 |
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| CN1440067A CN1440067A (en) | 2003-09-03 |
| CN1180467C true CN1180467C (en) | 2004-12-15 |
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| CN101964356A (en) * | 2010-10-25 | 2011-02-02 | 上海宏力半导体制造有限公司 | Semiconductor device and manufacturing method thereof |
| CN111490159A (en) * | 2020-04-17 | 2020-08-04 | 思瑞浦微电子科技（苏州）股份有限公司 | Isolation capacitor and preparation method thereof |
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