CN101958341B - 通过从mos器件的高k/金属栅极去除界面层缩小eot - Google Patents
通过从mos器件的高k/金属栅极去除界面层缩小eot Download PDFInfo
- Publication number
- CN101958341B CN101958341B CN201010229603.0A CN201010229603A CN101958341B CN 101958341 B CN101958341 B CN 101958341B CN 201010229603 A CN201010229603 A CN 201010229603A CN 101958341 B CN101958341 B CN 101958341B
- Authority
- CN
- China
- Prior art keywords
- screen
- phonon
- dielectric
- includes high
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000002184 metal Substances 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 230000008569 process Effects 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 9
- 229910006501 ZrSiO Inorganic materials 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 150000003376 silicon Chemical class 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000008859 change Effects 0.000 description 4
- 239000002800 charge carrier Substances 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 229940123973 Oxygen scavenger Drugs 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
- H01L21/02315—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H01L21/02052—Wet cleaning only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Plasma & Fusion (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
一种通过从MOS器件的高K/金属栅极去除界面层缩小EOT的集成电路结构，包括：半导体衬底以及半导体衬底上方的声子屏蔽层。在半导体衬底与声子屏蔽层之间基本不存在界面层。高K介电层位于声子屏蔽层上方。金属栅极层位于高K介电层上方。
Description
技术领域
总的来说，本发明涉及集成电路器件，更具体地，涉及金属氧化物半导体器件(MOS)的结构及其形成方法。
背景技术
缩小(Scaling)集成电路是对集成电路制造的继续尝试。目前，已经研究了可使用15nm技术制造的小规模集成电路。对于金属氧化物半导体(MOS)器件，缩小将产生高性能的电势。
当使用15nm技术制造MOS器件时，还需要削减栅极介电层的等效氧化层厚度(EOT)，例如，削减至约0.5nm。然而，这存在一定的困难。为了对15nm逻辑技术达到0.5nmEOT的目标，必需去除通常用于当前工艺水平的高K/金属栅极(HKMG)技术的、典型为0.5nm至1.0nm的SiO2界面层。然而，当通常使用的基于Hf的高K介电层与下层硅沟道直接接触时，所得到的MOS器件的沟道区域中的载流子迁移率通常会降至约普通Si迁移率(例如，在高电场下约为1MV/cm)的50％。
图1和图2示出了制造传统MOS器件的中间阶段。参照图1，具有约为1nm厚度的氧化硅界面层12位于衬底10上。包含HfO2的高K介电层14采用原子层沉积(ALD)沉积在界面层12上。接下来，在高K介电层14上形成薄Hf层16作为除氧剂，以从界面层12中取出氧(如箭头15所示)，从而得到图2所示的结构。薄Hf层16被转变为HfO2层并成为HfO2层14的一部分。由于从界面层12中去除了氧，所以界面层12也被转变为硅，这等效于去除了氧化硅界面层12。结果，削减了所得到栅极介电层的EOT的规模，例如，削减至0.6nm。
图1和图2所示处理的缺陷在于沟道区域中的载流子迁移率会降至普通Si迁移率的约90％至约50％之间。此外，减小了所得到栅极介电层的击穿电压。这是因为氧化硅界面层的去除会导致所得到MOS器件的高K介电层的远程软光学声子模式(remotesoftopticalphononmode)与沟道区域中的载流子之间耦合性的增加，从而导致更低的载流子迁移率。因此，在EOT缩小与迁移率降低之间存在折中。
因此，需要能够克服上述现有技术的缺陷的方法和结构。
发明内容
根据本发明的一个方面，提供了一种集成电路结构，包括：半导体衬底和半导体衬底上方的声子屏蔽层(phonon-screeninglayer)。在半导体衬底与声子屏蔽层之间基本上不存在界面层。高K介电层位于声子屏蔽层上方。金属栅极层位于高K介电层上方。
此外还公开了其他实施例。
本发明的有益特征包括减小MOS器件的栅极介电层的有效氧化层厚度(EOT)的可行性，而不会引起载流子迁移率的降低。
附图说明
为了更加完整地了解本发明及其优点，现在将参照附图在下面进行详细描述，其中：
图1和图2示出了制造传统MOS器件的中间阶段的截面图；
图3A以及图4-图7是根据实施例的制造MOS器件的中间阶段的截面图；以及
图3B示出了半导体衬底表面的Si-H端。
具体实施方式
下面将详细讨论本发明实施例的制造和使用。然而，应当理解，本实施例提供了许多可以在广泛的多种特定背景下实施的可应用创造性概念。所讨论的特定实施例仅示出了制造和使用本发明的特定方式，并不限定本发明的范围。
提出了新的金属氧化物半导体(MOS)器件的栅极构以及其形成方法。示出了根据本发明实施例的制造中间阶段。然后讨论了实施例的变化和操作。在本发明的各附图和所示实施例中，类似的标号用于表示类似的元件。
参照图3A，提供了衬底20，其可以由常用半导体材料(例如，硅、锗化硅(SiGe)、碳化硅(SiC)等)形成。浅沟槽隔离(STI)区域(未示出，参照图7中的42)可以形成在衬底20中。在衬底20的表面上可存在本征氧化物22，其可以为二氧化硅(SiO2))。
对图3A所示结构执行清洁处理。该清洁处理可包括两个步骤。第一步(通常称为标准清洁1或SC1)包括将衬底20浸泡在NH4OH/H2O2/H2O的溶液中大约10分钟。该步骤的主要目的在于去除颗粒和有机污染。第二步(通常称为标准清洁2或SC2)使用NCI/H2O2/H2O的混合物浸泡例如大约10分钟。该步骤的目的在于去除金属污染。接下来，例如，可以使用稀释的氢氟酸(DHF)去除本征氧化物22。结果，如图3B示意性所示出的，在衬底20的表面上形成Si-H端。
参照图4，如箭头21所表示的，执行原位下游等离子体处理(in-situdownstreamplasmatreatment)。该原位下游等离子体处理可使用含有氮和氢的气体(例如，N2H2)执行。可选地，还可以使用诸如NH3、NF3或其组合物的气体。下游等离子体处理可以导致衬底20的NH结合面的形成，使得改善了最后执行的原子层沉积(ALD)。
图5示出了声子屏蔽层24的原位形成，其中，在下游等离子体步骤与形成声子屏蔽层24的步骤之间将衬底20保持的真空环境下。在实施例中，声子屏蔽层24具有两个特性。首先，其会导致上面的高K介电层26(图5中未示出，请参照图6)的远程软光学声子模式与沟道区域40(图5中未示出，请参照图7)中的载流子之间的弱耦合性。其次，其保持沟道区域中的载流子迁移率(下文称为第一载流子迁移率)。因此，在声子屏蔽层24中并不使用已知的HfO2和ZrO2。声子屏蔽层24的可用材料包括但不限于AlN、ZrSiO4和Al2O3。在所得到的结构中，在衬底20与声子屏蔽层24之间基本上不存在界面层(SiOx，其中，x为1至2)，这意味着界面层根本不存在或具有小于约的厚度。在示例性实施例中，声子屏蔽层24具有小于约0.8nm，甚至小于约0.6nm的厚度。然而，应当理解，整个说明书中限定的尺寸仅仅是实例，在使用不同的形成技术时可以进行改变。此外，声子屏蔽层24的k值大于氧化硅的k值，甚至大于12。声子屏蔽层24的高k值可以有利地使栅极介电层的EOT减小。
图6示出了高K介电层26的形成。在示例性实施例中，高K介电层26具有大于声子屏蔽层24的k值的k值。此外，高K介电层26的k值可以大于约30，或者甚至大于约40。高K介电层的高k值使得所得MOS器件的栅极介电层的EOT减小。高K介电层26的材料可以具有或不具有声子屏蔽能力。
图6还示出了金属栅极28的形成。金属栅极28的材料取决于所得到的MOS器件为NMOS器件还是PMOS器件。如果所得到的MOS器件为NMOS器件，则金属栅极28可以由具有低功函的边带金属(band-edgemetal)形成。相反，如果所得到的MOS器件为PMOS器件，则金属栅极28可以由具有高功函的边带金属形成。
然后，继续进行处理以形成MOS器件，对图6所示的堆叠层进行图样化以形成所得MOS器件的栅极堆叠。图7示出了示例性MOS器件。所得到的栅极堆叠包括声子屏蔽层24’、高K介电层26’和金属栅极极层28’，它们分别是经过图样化的声子屏蔽层24、高K介电层26、金属栅极极层28和多晶硅的剩余部分。还形成了栅极隔离物32、轻掺杂源极/漏极区34、深源极/漏极区36和硅化物38。这些部件的形成处理在现有技术中是公知的，因此这里不再重复。
本发明的实施例具有多个有利特征。通过去除氧化硅界面层，有效减小了栅极介电层的EOT。在示例性实施例中，声子屏蔽层24(由ZrSiO4形成)的厚度约为0.8nm，且高K介电层26(由k值大于30的高K介电材料形成)的厚度约为1.2nm，栅极介电层的EOT只有0.42nm，其小于15nm技术节点所期望的约0.5nm的目标EOT。另一方面，利用声子屏蔽层24使MOS器件中高K介电层26的远程软光学声子模式与沟道区域40(图7)中的载流子之间的耦合性最小，不会牺牲沟道区域中载流子的载流子迁移率。因此，可以制造性能提高的小规模MOS器件。
尽管已经详细描述了本发明及其优点，但应当理解，在不背离由所附权利要求限定的本发明的精神和范围的前提下，可以做出多种改变、替换和变化。另外，本应用的范围并不限于说明书中描述的处理、机械装置、制造以及物质、方式、方法和步骤的组合。根据本发明的公开内容，本领域普通技术人员可容易地理解，根据本发明，可以利用如这里所描述的对应实施例执行基本相同的功能或实现基本相同的结果、已经存在或之后将要开发的处理、机械装置、制造以及物质、方式、方法或步骤的组合。因此，所附权利要求意在包括这些处理、机械装置、制造以及物质、方式、方法或步骤的组合的范围内。此外，每个权利要求都构成单独的实施例，并且各种权利要求和实施例的组合均在本发明的范围内。
Claims (15)
1.一种集成电路结构，包括：
半导体衬底，其中，所述衬底具有通过下游等离子体处理形成的NH结合面；
声子屏蔽层，在所述半导体衬底上方，其中，在所述半导体衬底与所述声子屏蔽层之间基本不存在界面层；
高K介电层，在所述声子屏蔽层上方；以及
金属栅极层，在所述高K介电层上方。
2.根据权利要求1所述的集成电路结构，其中，所述声子屏蔽层与所述高K介电层物理接触。
3.根据权利要求1所述的集成电路结构，其中，所述高K介电层的k值大于所述声子屏蔽层的k值，以及所述高K介电层具有大于30的k值。
4.根据权利要求1所述的集成电路结构，其中，所述声子屏蔽层由从主要由AlN、ZrSiO4和Al2O3组成的组中选择出的材料形成，其中，所述界面层为氧化硅层。
5.根据权利要求1所述的集成电路结构，还包括位于所述金属栅极层上方的多晶硅层。
6.根据权利要求1所述的集成电路结构，其中，所述声子屏蔽层、所述高K介电层和所述金属栅极层形成栅极堆叠，以及其中，所述集成电路还包括源极/漏极区，所述源极/漏极区具有在所述半导体衬底中并与所述栅极堆叠相邻的部分，以及所述声子屏蔽层和所述高K介电层具有小于0.5nm的组合等效氧化层厚度(EOT)。
7.一种集成电路结构，包括：
硅衬底，其中，该硅衬底具有通过下游等离子体处理形成的NH结合面；
栅极堆叠，包括：
声子屏蔽层，在所述硅衬底上方并与所述硅衬底接触；
高K介电层，在所述声子屏蔽层上方，其中，所述高K介电层的k值大于所述声子屏蔽层的k值；和
金属栅极层，在所述高K介电层上方；以及
源极/漏极区，与所述栅极堆叠相邻。
8.根据权利要求7所述的集成电路结构，其中，所述高K介电层具有大于30的k值。
9.根据权利要求7所述的集成电路结构，其中，所述声子屏蔽层由从主要由AlN、ZrSiO4和Al2O3组成的组中选择出的材料形成。
10.根据权利要求7所述的集成电路结构，还包括位于所述金属栅极层上方的多晶硅层。
11.根据权利要求7所述的集成电路结构，其中，所述声子屏蔽层和所述高K介电层具有小于0.5nm的组合等效氧化层厚度(EOT)。
12.一种集成电路结构，包括：
硅衬底，其中，该硅衬底具有通过下游等离子体处理形成的NH结合面；以及
栅极堆叠，包括：
声子屏蔽层，在所述硅衬底上方并与所述硅衬底接触，其中，所述声子屏蔽层由从主要由AlN、ZrSiO4和Al2O3组成的组中选择出的材料形成；
高K介电层，在所述声子屏蔽层上方，其中，所述高K介电层的k值大于所述声子屏蔽层的k值；和
金属栅极层，在所述高K介电层上方。
13.根据权利要求12所述的集成电路结构，还包括位于所述金属栅极层上方的多晶硅层以及源极/漏极区，所述源极/漏极区具有在所述硅衬底中并与所述栅极堆叠相邻的部分。
14.根据权利要求12所述的集成电路结构，其中，所述声子屏蔽层和所述高K介电层具有小于0.5nm的组合等效氧化层厚度(EOT)。
15.根据权利要求12所述的集成电路结构，其中，所述声子屏蔽层包括AlN、ZrSiO4或Al2O3。
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US22578709P | 2009-07-15 | 2009-07-15 | |
| US61/225,787 | 2009-07-15 | ||
| US12/789,681 | 2010-05-28 | ||
| US12/789,681 US9478637B2 (en) | 2009-07-15 | 2010-05-28 | Scaling EOT by eliminating interfacial layers from high-K/metal gates of MOS devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101958341A CN101958341A (zh) | 2011-01-26 |
| CN101958341B true CN101958341B (zh) | 2015-11-25 |
Family
ID=43464679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010229603.0A Active CN101958341B (zh) | 2009-07-15 | 2010-07-13 | 通过从mos器件的高k/金属栅极去除界面层缩小eot |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US9478637B2 (zh) |
| CN (1) | CN101958341B (zh) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8912061B2 (en) | 2011-06-28 | 2014-12-16 | International Business Machines Corporation | Floating gate device with oxygen scavenging element |
| US8541867B2 (en) | 2011-06-28 | 2013-09-24 | International Business Machines Corporation | Metal insulator metal structure with remote oxygen scavenging |
| US8809152B2 (en) | 2011-11-18 | 2014-08-19 | International Business Machines Corporation | Germanium oxide free atomic layer deposition of silicon oxide and high-k gate dielectric on germanium containing channel for CMOS devices |
| US20130328135A1 (en) * | 2012-06-12 | 2013-12-12 | International Business Machines Corporation | Preventing fully silicided formation in high-k metal gate processing |
| US8716088B2 (en) | 2012-06-27 | 2014-05-06 | International Business Machines Corporation | Scavenging metal stack for a high-K gate dielectric |
| CN103824764A (zh) * | 2012-11-19 | 2014-05-28 | 上海华虹宏力半导体制造有限公司 | 一种沟槽型mos器件中沟槽栅的制备方法 |
| US8772116B2 (en) | 2012-11-20 | 2014-07-08 | International Business Machines Corporation | Dielectric equivalent thickness and capacitance scaling for semiconductor devices |
| CN103617949A (zh) * | 2013-09-13 | 2014-03-05 | 复旦大学 | 利用三氟化氮抑制高介电常数栅介质层和硅衬底之间界面层生长的方法 |
| US9595593B2 (en) * | 2015-06-29 | 2017-03-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure with interfacial layer and method for manufacturing the same |
| US9443953B1 (en) | 2015-08-24 | 2016-09-13 | International Business Machines Corporation | Sacrificial silicon germanium channel for inversion oxide thickness scaling with mitigated work function roll-off and improved negative bias temperature instability |
| US10446400B2 (en) * | 2017-10-20 | 2019-10-15 | Samsung Electronics Co., Ltd. | Method of forming multi-threshold voltage devices and devices so formed |
| US20230100952A1 (en) * | 2021-09-24 | 2023-03-30 | Intel Corporation | High-k or ferroelectric gate oxide with zero-sio2 il process for transistor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6355548B1 (en) * | 1999-12-22 | 2002-03-12 | Hyundai Electronics Industries Co., Ltd. | Method for manufacturing a gate structure incorporated therein a high K dielectric |
| CN1815755A (zh) * | 2004-12-22 | 2006-08-09 | 台湾积体电路制造股份有限公司 | 半导体装置及其制造方法 |
| CN101167177A (zh) * | 2005-05-26 | 2008-04-23 | 应用材料股份有限公司 | 制造受应力电晶体结构的集成制程 |
| CN101593764A (zh) * | 2008-05-30 | 2009-12-02 | 株式会社瑞萨科技 | 半导体器件及其制造方法 |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6407435B1 (en) * | 2000-02-11 | 2002-06-18 | Sharp Laboratories Of America, Inc. | Multilayer dielectric stack and method |
| KR100376266B1 (ko) | 2000-10-20 | 2003-03-17 | 주식회사 하이닉스반도체 | 반도체 소자의 캐패시터 제조 방법 |
| US7253122B2 (en) * | 2002-08-28 | 2007-08-07 | Micron Technology, Inc. | Systems and methods for forming metal oxides using metal diketonates and/or ketoimines |
| US6897095B1 (en) * | 2004-05-12 | 2005-05-24 | Freescale Semiconductor, Inc. | Semiconductor process and integrated circuit having dual metal oxide gate dielectric with single metal gate electrode |
| US7564108B2 (en) * | 2004-12-20 | 2009-07-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Nitrogen treatment to improve high-k gate dielectrics |
| US7691701B1 (en) * | 2009-01-05 | 2010-04-06 | International Business Machines Corporation | Method of forming gate stack and structure thereof |
-
2010
- 2010-05-28 US US12/789,681 patent/US9478637B2/en active Active
- 2010-07-13 CN CN201010229603.0A patent/CN101958341B/zh active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6355548B1 (en) * | 1999-12-22 | 2002-03-12 | Hyundai Electronics Industries Co., Ltd. | Method for manufacturing a gate structure incorporated therein a high K dielectric |
| CN1815755A (zh) * | 2004-12-22 | 2006-08-09 | 台湾积体电路制造股份有限公司 | 半导体装置及其制造方法 |
| CN101167177A (zh) * | 2005-05-26 | 2008-04-23 | 应用材料股份有限公司 | 制造受应力电晶体结构的集成制程 |
| CN101593764A (zh) * | 2008-05-30 | 2009-12-02 | 株式会社瑞萨科技 | 半导体器件及其制造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20110012210A1 (en) | 2011-01-20 |
| US9478637B2 (en) | 2016-10-25 |
| CN101958341A (zh) | 2011-01-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101958341B (zh) | 通过从mos器件的高k/金属栅极去除界面层缩小eot | |
| JP4719161B2 (ja) | トランジスタの製造方法 | |
| US7160781B2 (en) | Transistor device and methods of manufacture thereof | |
| US8507991B2 (en) | Semiconductor device and method of manufacturing the same | |
| CN100442517C (zh) | 具有不同栅极介质的半导体器件及其制造方法 | |
| US8143676B2 (en) | Semiconductor device having a high-dielectric-constant gate insulating film | |
| US7989898B2 (en) | Method for fabricating a dual workfunction semiconductor device and the device made thereof | |
| TWI406414B (zh) | 半導體裝置及其製造方法 | |
| EP2053653A1 (en) | Dual work function semiconductor device and method for manufacturing the same | |
| CN102110651B (zh) | 一种半导体器件及其制造方法 | |
| US7253050B2 (en) | Transistor device and method of manufacture thereof | |
| JP2007150292A (ja) | 半導体素子およびその製造方法 | |
| JP2008306051A (ja) | 半導体装置およびその製造方法 | |
| JP2007110091A (ja) | トランジスタ、およびその製造方法 | |
| JP2009044051A (ja) | 半導体装置及びその製造方法 | |
| CN102064176A (zh) | 一种半导体器件及其制造方法 | |
| JP2010177240A (ja) | 半導体装置及びその製造方法 | |
| US7911028B2 (en) | Semiconductor device and method of manufacturing the same | |
| JP2010272596A (ja) | 半導体装置の製造方法 | |
| JP2010021200A (ja) | 半導体装置の製造方法 | |
| US8778750B2 (en) | Techniques for the fabrication of thick gate dielectric | |
| CN102237268A (zh) | 一种插入式TiN金属栅叠层结构的制备和刻蚀方法 | |
| JP4902888B2 (ja) | 半導体装置およびその製造方法 | |
| CN103107090B (zh) | 制造半导体器件的方法 | |
| JP2010040710A (ja) | 半導体装置及びその製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |