CN101944514B - 半导体封装结构以及封装制作工艺 - Google Patents

半导体封装结构以及封装制作工艺 Download PDF

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CN101944514B
CN101944514B CN2010105069876A CN201010506987A CN101944514B CN 101944514 B CN101944514 B CN 101944514B CN 2010105069876 A CN2010105069876 A CN 2010105069876A CN 201010506987 A CN201010506987 A CN 201010506987A CN 101944514 B CN101944514 B CN 101944514B
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chip
pin
packing colloid
bonding land
chip carrier
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CN101944514A (zh
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韩仁圭
金锡奉
李瑜镛
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

本发明公开一种半导体封装结构与封装制作工艺，其中一封装胶体暴露出一导线架的一芯片座的一下表面，以增加半导体封装结构散热效率。此外，两芯片配置于导线架的同一侧边且封装胶体包覆接合于上芯片的每一引脚的端部，因此可防止于下芯片打线制作工艺与芯片接合步骤中于引脚端上造成刮伤，可提升打线接合性。

Description

半导体封装结构以及封装制作工艺
技术领域
本发明涉及一种半导体封装结构以及封装制作工艺，且特别是涉及一种多芯片(multi-chip)半导体封装结构及其封装制作工艺。
背景技术
随着对小型化与高操作速度持续增长的需求，具有多个芯片的半导体封装结构，例如是多芯片模块(multi-chip modules，MCMs)，在各种各样电子产品中是越来越有吸引力。包括超过一个以上的芯片的多芯片模块通过长的印刷电路板连接线路结合，例如是处理器、存储器与联系逻辑至单一封装内，可帮助缩小系统操作速度限制。此外，多芯片模块(MCMs)可减少介于集成电路芯片之间的内连接长度，因而降低信号延迟与存取时间。
然而，在某些应用(例如是胎压监测系统(tire pressure measurementsystem，TPMS)以监测在汽车轮胎的压力)中，期望具有一芯片，例如是一与其他集成电路芯片分割功能性、可靠性、安全与/或制造性的感测芯片。胎压监测系统典型地具有一感测芯片用以感测胎压与一特殊应用集成电路(application specific integrated circuit，ASIC)以反映温度与系统电池电压。
现有的胎压监测系统是以各式各样的方式进行封装。然而，当条状输送特殊应用集成电路(ASIC)在打线结合与芯片贴合步骤中时，由于引脚端造成刮伤，因而封装结构具有低散热效率与较差的打线结合性。
发明内容
本发明的目的在于提供一种半导体封装结构以及一封装制作工艺，可克服或至少可降低上述现有所提及的问题。
本发明提供一种半导体封装结构，其包括一导线架、一第一芯片、一第一封装胶体、一第二芯片以及一盖体。导线架具有一芯片座以及环绕芯片座配置的多个第一引脚与多个第二引脚。第一芯片配置于芯片座的一上表面且电连接第一引脚与第二引脚。第一封装胶体包覆第一芯片、芯片座的上表面以及每一第一引脚与每一第二引脚的至少一部分。第一封装胶体暴露出芯片座的一下表面且具有一暴露出每一第二引脚的一第一接合区的凹穴。第一封装胶体更包覆每一第二引脚朝向芯片座延伸的一端部。第二芯片配置于第一封装胶体的凹穴内且电连接至第二引脚的第一接合区。盖体配置于第一封装胶体的凹穴的上方。
本发明还提供一种封装制作工艺，其包括提供一导线架。导线架具有一芯片座以及环绕芯片座配置的多个第一引脚与多个第二引脚；配置一第一芯片于芯片座的一上表面上；电连接第一芯片至第一引脚与第二引脚；包覆第一芯片、芯片座的上表面以及每一第一引脚与每一第二引脚的至少一部分于一第一封装胶体内，第一封装胶体具有一暴露出每一第二引脚的一第一接合区的凹穴，其中第一封装胶体的至少一部分形成以覆盖芯片座上的第一芯片，第一封装胶体暴露出芯片座的一下表面，且第一封装胶体更包覆每一第二引脚朝向芯片座延伸的一端部；设置第二芯片于第一封装胶体的凹穴内且直接位在第一芯片上方的第一封装胶的部分上；电连接第二芯片至第二引脚的第一接合区；以及配置一盖体于第一封装胶体的凹穴的上方。
基于上述，第一封装胶体暴露出芯片座的下表面，以提高散热表现，例如是半导体封装结构的散热效率。此外，两芯片配置于导线架的同一侧边且封装胶体包覆每一引脚的端部，因此可防止于打线制作工艺与芯片接合步骤中于引脚端上造成刮伤，可提升打线接合性。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附附图作详细说明如下。
附图说明
图1A与图1B绘示本发明的一实施例的一种半导体封装结构的示意图；
图2A至图2F绘示本发明的一实施例的一种封装制作工艺的示意图。
主要元件符号说明
100：半导体封装结构
110：导线架
112：第一引脚
1124：外引脚部
114：第二引脚
1142：内引脚部
1142a：上表面
1146：端部
116：芯片座
116a：上表面
116b：下表面
117：连接杆
117a：第一向下设置部
117b：第二向下设置部
119：结合部
120：第一芯片
122：打线
124：打线
130：第一封装胶体
132：凹穴
132a：底表面
136：洞
140：第二芯片
150：盖体
152：开孔
160：第二封装胶体
170：停止结构
182：粘着剂
184：粘着剂
192：第一接合区
194：第二接合区
具体实施方式
现将详细参考本发明的实施例，并在附图中说明所述实施例的实例。另外，凡可能之处，在附图及实施方式中使用相同标号的元件/构件代表相同或类似部分。
图1A与图1B绘示本发明的一实施例的一种半导体封装结构100的示意图。图1A绘示半导体封装结构100的俯视图。图1A更绘示半导体封装结构的一内部。图1B为沿图1A之线A-A’的剖面示意图。
请同时参考图1A与图1B，半导体封装结构100主要包括一导线架110以及一包覆于一第一封装胶体130内的第一芯片120，此第一封装胶体130具有一凹穴132用以容置一第二芯片140，以及一配置于第一封装胶体130的凹穴132上方的盖体150。举例来说，第一芯片120可以是一分立器件(discrete device)、一整合电路或一控制芯片，而第二芯片140可以是一暴露环境中的感测器，例如是一化学感测器、一压力感测器、一温度感测器、一光学感测器、一速度感测器或一加速度计。或者是，第二芯片140可以是一表面声波(Surface Acoustic Wave，SAW)装置或其他芯片。盖体150，较佳地，具有一开孔152，用以将第二芯片140暴露于周遭环境中，如同电子芯片的一些型态的需求，例如是至少上述所述的一些感测器。盖体150内的开孔152，较佳地，尺寸为允许感测器(需被暴露于环境中)连通半导体封装结构100之外的环境且同时需防止污染物渗透于凹穴132中。
导线架110具有环绕一芯片座116配置的多个第一引脚112与多个第二引脚114。导线架110可以是由一铜基合金(copper-base alloy)或者是以铜或包含铜的合金所制成。本实施例所适用的导线架可经由下述三种引脚表面处理方式：后电镀铅锡合金、镀雾面锡以及预镀镍钯，再薄镀一层金，例如是预镀导线架(Pre-Plated Frame，PPF)技术。这些第一引脚112与这些第二引脚114皆连接至一结合部119(dam bar)(未绘示)。芯片座116通过多个连接杆117(tie-bars)连接至结合部119。
第一芯片120通过一粘着剂182稳固地贴附于芯片座116的一上表面116a，其中粘着剂182例如是银胶或其他不导电的胶体，且第一芯片120通过多条打线122电连接至这些第一引脚112以及这些第二引脚114。第一封装胶体130包覆第一芯片120用以抗湿性以及抗震性。第一封装胶体130也包覆芯片座116的上表面116a以及每一第一引脚112与每一第二引脚114的至少一部分。
每一第二引脚114的位于内引脚部1142上表面1142a上的第一接合区192暴露于凹穴132内，且通过多条打线124电连接至第二芯片140。此外，每一第二引脚114更具有一第二接合区194，其配置于每一第二引脚114的内引脚部1142的上表面1142a上，且位于第二引脚114朝向芯片座116延伸的端部1146上。第一芯片120电连接至这些第二引脚114的这些第二接合区194。
值得注意的是，第一接合区192与第二接合区194位于每一第二引脚114的内引脚部1142的上表面1142a上。此外，每一第二引脚114的内引脚部1142向下设置，例如是每一第二引脚114的第一接合区192以及第二接合区194低于第二引脚114的其他部分。而且，第一封装胶体130也包覆每一第二引脚114的端部1146与位于其上的第二接合部194。
每一连接杆117与这些第二引脚114一同向下设置，以形成一第一向下设置部117a，此外每一连接杆117更通过另一下向设置步骤向下设置以形成一第二向下设置部117b。另外，与连接杆117连接的芯片座116低于每一第二引脚114的第一接合区192以及第二接合区194，且第一封装胶体130暴露出芯片座116的一下表面116b。因此，散热表现，例如是半导体封装结构100的散热效率，可通过暴露芯片座116的下表面116b来提升。
这些第一引脚112分别具有一从第一封装胶体130的侧边延伸向外的外引脚部1124，其依序可形成标准引脚形态。
第二芯片140通过一粘着剂184稳固地贴附于凹穴132的一底表面132a，粘着剂184例如是银胶或其他非导电的粘着剂，且第二芯片140通过这些打线124电连接至这些第二引脚114。此外，一弹性胶体容置于凹穴132内以形成一覆盖第二芯片140的第二封装胶体160。在本实施例中，一停止结构170(stopper)，较佳地，形成于垂直环绕凹穴132的第一封装胶体130的内壁内，以防止第二封装胶体160溢出于凹穴132外。
需注意的是，至少第一封装胶体130的一部分形成于第二芯片140与芯片座116之间，因此第二芯片140可直接配置第一封装胶体130的部分上以取代芯片座116。由于第一封装胶体130典型地具有一实质上等同于第二芯片140的热膨胀系数(CTE)，因此上面所述的设计可显著地减少第二芯片140与芯片座116之间的分层、芯片翘曲甚至是芯片裂化等问题。
此外，第一封装胶体130包覆第一芯片120与第二芯片140皆配置于芯片座116的同一侧边，且第一封装胶体130包覆每一第二引脚114的端部1146与其上的第二接合区194，因此可防止于第一芯片120的打线制作工艺与芯片接合步骤中于每一第二引脚114的端部1146上造成刮伤，可提升打线接合性。
第一封装胶体130通过一现有封胶过程(molding process)，例如是转移式封胶(transfer molding)，所形成。在封胶过程中，导线架110通过一上模具与一下模具(未绘示)来固定定位，其中上模具、下模具可一同定义一模穴，且此模穴通常是依据第一封装胶体130来塑造。下模具较佳地具有一用以支撑这些第二引脚114的这些内引脚部1142的定位脚，可避免溢胶残留于被暴露的上表面1142a。定位脚将会形成一孔136于第一封装胶体130中。
在一实施例中，半导体封装结构可应用于一胎压监测系统(tire pressuremeasurement system，TPMS)(未绘示)中。在此实施例中，第一芯片120可以是一特殊应用集成电路(application specific integrated circuit，ASIC)，而第二芯片140可以是一压力感测芯片。较佳地，用以形成第二封装胶体160的封装胶体具有充分的弹性，以允许感测芯片可反应周遭压力的变化。较佳地，这些第一引脚112的外引脚部1124的设计是与现有规范的胎压监测系统相容。
虽然在此实施例中详细谈论的半导体封装结构100具有两芯片，但一半导体封装结构具有多于两个芯片在应用的精神和范围之内仍然被考虑。
本实施例更提供一封装制作工艺用以制作前述的半导体封装结构。图2A至图2F绘示本发明的一实施例的一种封装制作工艺的示意图。
首先，请参考图2A和图2B，导线架110具有一芯片座116、多个第一引脚112以及多个第二引脚114。第一芯片120通过粘着剂182结合于芯片座116的上表面116a上，粘着剂182例如是银胶或其他非导电的粘着剂，且第一芯片120通过这些打线122电连接至这些第一引脚112与这些第二引脚114。其中，第一芯片120电连接至每一第二引脚114的内引脚部1142的一上表面1142上的第二接合区194。
接着，请参考图2C，形成第一封装胶体130以包覆第一芯片120、芯片座116的上表面116a以及这些第一引脚112与这些第二引脚114的至少一部分。第一封装胶体130具有一暴露出每一第二引脚114的第一接合区192的凹穴132，其中第一封装胶体130的至少一部分形成以覆盖位于芯片座116上的第一芯片120。第一封装胶体130更暴露出芯片座116的下表面116b，且包覆每一第二引脚114的端部1146以及其上的第二接合区194。
接着，请参考图2D和图2E，第二芯片140通过一粘着剂184稳固地贴附至凹穴132的一底表面132a，此凹穴132是直接位于第一芯片120上方的第一封装胶体130的部分上，而粘着剂184例如是银胶或其他非导电性的粘着剂，且第二芯片140通过这些打线124电连接至每一第二引脚114的第一接合区192。
然后，请参考图2F，形成第二封装胶体160于第一封装胶体130的凹穴132内以包覆第二芯片140。而且，盖体150配置于第一封装胶体130的凹穴132的上方。
在大量生产时，可想而知的是可同时形成多个导线架单位于一导线架条中，以便同时被制造多个半导体封装结构。在上述的实施例中，在图2F的步骤之后可进行一单体化步骤，而完成封装制作工艺。
虽然结合以上实施例揭露了本发明，然而其并非用以限定本发明，任何所属技术领域中熟悉此技术者，在不脱离本发明的精神和范围内，可作些许的更动与润饰，故本发明的保护范围应以附上的权利要求所界定的为准。

Claims (13)

1.一种半导体封装结构，包括：
导线架，具有芯片座以及环绕该芯片座配置的多个第一引脚与多个第二引脚；
第一芯片，配置于该芯片座的一上表面上，该第一芯片电连接该些第一引脚与该些第二引脚；
第一封装胶体，包覆该第一芯片、该芯片座的该上表面以及各该第一引脚与各该第二引脚的至少一部分，该第一封装胶体暴露出该芯片座的一下表面，该第一封装胶体具有一暴露出各该第二引脚的一第一接合区的凹穴，且该第一封装胶体还包覆各该第二引脚朝向该芯片座延伸的一端部；
第二芯片，配置于该第一封装胶体的该凹穴内且电连接至该些第二引脚的该些第一接合区；以及
盖体，配置于该第一封装胶体的该凹穴的上方。
2.如权利要求1所述的半导体封装结构，还包括一粘着剂，其中该第二芯片通过该粘着剂配置于该第一封装胶体的该凹穴的一底表面上。
3.如权利要求1所述的半导体封装结构，还包括一第二封装胶体，配置于第一封装胶体的该凹穴内，以包覆该第二芯片。
4.如权利要求1所述的半导体封装结构，其中该第二芯片为一感测芯片，且该盖体具有一开孔，以允许该感测芯片连通该半导体封装结构之外的环境。
5.如权利要求1所述的半导体封装结构，其中各该第二引脚具有该第一接合区以及一第二接合区，该第一接合区与该第二接合区配置于该第二引脚的一上表面上，该第二接合区位于该第二引脚的该端部且该第一封装胶体包覆该第二接合区，而该第一芯片电连接至该第二接合区。
6.如权利要求1所述的半导体封装结构，其中各该第二引脚的该第一接合区与该第二接合区向下设置以低于该第二引脚的其他部分。
7.如权利要求6所述的半导体封装结构，其中该芯片座向下设置以低于各该第二引脚的该第一接合区与该第二接合区，且该第一封装胶体暴露出该芯片座的该下表面。
8.一种封装制作工艺，包括：
提供一导线架，该导线架具有一芯片座以及环绕该芯片座配置的多个第一引脚以及多个第二引脚；
配置一第一芯片于该芯片座的一上表面上；
电连接该第一芯片至该些第一引脚与该些第二引脚；
包覆该第一芯片、该芯片座的该上表面以及各该第一引脚与各该第二引脚的至少一部分于一第一封装胶体内，该第一封装胶体具有一暴露出各该第二引脚的一第一接合区的凹穴，其中该第一封装胶体的至少一部分形成以覆盖该芯片座上的该第一芯片，该第一封装胶体暴露出该芯片座的一下表面，且该第一封装胶体还包覆各该第二引脚朝向该芯片座延伸的一端部；
设置该第二芯片于该第一封装胶体的该凹穴内且直接位在该第一芯片上方的该第一封装胶体的部分上；
电连接该第二芯片至该些第二引脚的该些第一接合区；以及
配置一盖体于该第一封装胶体的该凹穴的上方。
9.如权利要求8所述的封装制作工艺，其中该第二芯片通过一粘着剂配置于该第一封装胶体的该凹穴的一底表面上。
10.如权利要求8所述的封装制作工艺，还包括提供一第二封装胶体于该第一封装胶体的该凹穴内，以包覆该第二芯片。
11.如权利要求8所述的封装制作工艺，其中各该第二引脚具有该第一接合区以及一第二接合区，该第一接合区与该第二接合区配置于该第二引脚的一上表面，该第二接合区位于该第二引脚朝向该芯片座延伸的该端部且该第一封装胶体包覆该第二接合区，而该第一芯片电连接至该第二接合区。
12.如权利要求8所述的封装制作工艺，其中各该第二引脚的该第一接合区与该第二接合区向下设置以低于该第二引脚的其他部分。
13.如权利要求12所述的封装制作工艺，其中该芯片座向下设置以低于各该第二引脚的该第一接合区与该第二接合区，且该第一封装胶体暴露出该芯片座的该下表面。
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