TWI419301B - 半導體封裝結構以及封裝製程 - Google Patents

半導體封裝結構以及封裝製程 Download PDF

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Publication number
TWI419301B
TWI419301B TW099125142A TW99125142A TWI419301B TW I419301 B TWI419301 B TW I419301B TW 099125142 A TW099125142 A TW 099125142A TW 99125142 A TW99125142 A TW 99125142A TW I419301 B TWI419301 B TW I419301B
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Taiwan
Prior art keywords
wafer
encapsulant
pins
bonding region
disposed
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TW099125142A
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English (en)
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TW201138057A (en
Inventor
Ingyu Han
Seokbong Kim
Yu-Yong Lee
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Advanced Semiconductor Eng
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Publication of TW201138057A publication Critical patent/TW201138057A/zh
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Publication of TWI419301B publication Critical patent/TWI419301B/zh

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    • H01L23/3135—Double encapsulation or coating and encapsulation
    • G—PHYSICS
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    • G01L19/00—Details of, or accessories for, apparatus for measuring steady or quasi-steady pressure of a fluent medium insofar as such details or accessories are not special to particular types of pressure gauges
    • G01L19/0061—Electrical connection means
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    • G—PHYSICS
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Description

半導體封裝結構以及封裝製程
本發明是有關於一種半導體封裝結構以及封裝製程，且特別是有關於一種多晶片(multi-chip)半導體封裝結構及其封裝製程。
隨著對小型化與高操作速度持續增長的需求，具有多個晶片之半導體封裝結構，例如是多晶片模組(multi-chip modules,MCMs)，在各種各樣電子產品中是越來越有吸引力。包括超過一個以上之晶片的多晶片模組透過長的印刷電路板連接線路結合，例如是處理器、記憶體與聯繫邏輯至單一封裝內，可幫助縮小系統操作速度限制。此外，多晶片模組(MCMs)可減少介於積體電路晶片之間的內連接長度，因而降低訊號延遲與存取時間。
然而，於某些應用(例如是胎壓監測系統(tire pressure measurement system,TPMS)以監測在汽車輪胎的壓力)中，期望具有一晶片，例如是一與其他集成電路晶片分割功能性、可靠性、安全與/或製造性的感測晶片。胎壓監測系統典型地具有一感測晶片用以感測胎壓與一特殊應用積體電路(application specific integrated circuit,ASIC)以反映溫度與系統電池電壓。
習知之胎壓監測系統是以各式各樣的方式進行封裝。然而，當條狀輸送特殊應用積體電路(ASIC)於打線結合與晶片貼合步驟中時，由於引腳端造成刮傷，因而封裝結構具有低散熱效率與較差的打線結合性。
本發明提供一種半導體封裝結構以及一封裝製程，可克服或至少可降低上述習知所提及的問題。
本發明提供一種半導體封裝結構，其包括一導線架、一第一晶片、一第一封裝膠體、一第二晶片以及一蓋體。導線架具有一晶片座以及環繞晶片座配置的多個第一引腳與多個第二引腳。第一晶片配置於晶片座的一上表面且電性連接第一引腳與第二引腳。第一封裝膠體包覆第一晶片、晶片座的上表面以及每一第一引腳與每一第二引腳的至少一部分。第一封裝膠體暴露出晶片座的一下表面且具有一暴露出每一第二引腳之一第一接合區的凹穴。第一封裝膠體更包覆每一第二引腳朝向晶片座延伸的一端部。第二晶片配置於第一封裝膠體的凹穴內且電性連接至第二引腳的第一接合區。蓋體配置於第一封裝膠體之凹穴的上方。
本發明還提供一種封裝製程，其包括提供一導線架。導線架具有一晶片座以及環繞晶片座配置的多個第一引腳與多個第二引腳；配置一第一晶片於晶片座的一上表面上；電性連接第一晶片至第一引腳與第二引腳；包覆第一晶片、晶片座的上表面以及每一第一引腳與每一第二引腳的至少一部分於一第一封裝膠體內，第一封裝膠體具有一暴露出每一第二引腳之一第一接合區的凹穴，其中第一封裝膠體的至少一部分形成以覆蓋晶片座上的第一晶片，第一封裝膠體暴露出晶片座的一下表面，且第一封裝膠體更包覆每一第二引腳朝向晶片座延伸的一端部；設置第二晶片於第一封裝膠體的凹穴內且直接位在第一晶片上方之第一封裝膠的部分上；電性連接第二晶片至第二引腳的第一接合區；以及配置一蓋體於第一封裝膠體的凹穴的上方。
基於上述，第一封裝膠體暴露出晶片座的下表面，以提高散熱表現，例如是半導體封裝結構的散熱效率。此外，兩晶片配置於導線架的同一側邊且封裝膠體包覆每一引腳的端部，因此可防止於打線製程與晶片接合步驟中於引腳端上造成刮傷，可提升打線接合性。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
現將詳細參考本發明之實施例，並在附圖中說明所述實施例之實例。另外，凡可能之處，在圖式及實施方式中使用相同標號的元件/構件代表相同或類似部分。
圖1A與圖1B繪示本發明之一實施例之一種半導體封裝結構100的示意圖。圖1A繪示半導體封裝結構100的俯視圖。圖1A更繪示半導體封裝結構的一內部。圖1B為沿圖1A之線A-A’的剖面示意圖。
請同時參考圖1A與圖1B，半導體封裝結構100主要包括一導線架110以及一包覆於一第一封裝膠體130內的第一晶片120，此第一封裝膠體130具有一凹穴132用以容置一第二晶片140，以及一配置於第一封裝膠體130之凹穴132上方的蓋體150。舉例來說，第一晶片120可以是一離散裝置(discrete device)、一整合電路或一控制晶片，而第二晶片140可以是一暴露環境中的感測器，例如是一化學感測器、一壓力感測器、一溫度感測器、一光學感測器、一速度感測器或一加速度計。或者是，第二晶片140可以是一表面超音波(Surface Acoustic Wave,SAW)裝置或其他晶片。蓋體150，較佳地，具有一開孔152，用以將第二晶片140暴露於周遭環境中，如同電子晶片之一些型態的需求，例如是至少上述所述之一些感測器。蓋體150內的開孔152，較佳地，尺寸為允許感測器(需被暴露於環境中)連通半導體封裝結構100之外的環境且同時需防止污染物滲透於凹穴132中。
導線架110具有環繞一晶片座116配置的多個第一引腳112與多個第二引腳114。導線架110可以是由一銅基合金(copper-base alloy)或者是以銅或包含銅的合金所製成。本實施例所適用的導線架可經由下述三種引腳表面處理方式：後電鍍鉛錫合金、鍍霧面錫以及預鍍鎳鈀，再薄鍍一層金，例如是預鍍導線架(Pre-Plated Frame,PPF)技術。這些第一引腳112與這些第二引腳114皆連接至一結合部119(dam bar)(未繪示)。晶片座116透過多個連接桿117(tie-bars)連接至結合部119。
第一晶片120透過一黏著劑182穩固地貼附於晶片座116的一上表面116a，其中黏著劑182例如是銀膠或其他不導電的膠體，且第一晶片120透過多條打線122電性連接至這些第一引腳112以及這些第二引腳114。第一封裝膠體130包覆第一晶片120用以抗濕性以及抗震性。第一封裝膠體130亦包覆晶片座116的上表面116a以及每一第一引腳112與每一第二引腳114的至少一部分。
每一第二引腳114之位於內引腳部1142上表面1142a上的第一接合區192暴露於凹穴132內，且透過多條打線124電性連接至第二晶片140。此外，每一第二引腳114更具有一第二接合區194，其配置於每一第二引腳114之內引腳部1142的上表面1142a上，且位於第二引腳114朝向晶片座116延伸的端部1146上。第一晶片120電性連接至這些第二引腳114的這些第二接合區194。
值得注意的是，第一接合區192與第二接合區194位於每一第二引腳114之內引腳部1142的上表面1142a上。此外，每一第二引腳114的內引腳部1142向下設置，例如是每一第二引腳114的第一接合區192以及第二接合區194低於第二引腳114的其他部分。而且，第一封裝膠體130亦包覆每一第二引腳114的端部1146與位於其上的第二接合部194。
每一連接桿117與這些第二引腳114一同向下設置，以形成一第一向下設置部117a，此外每一連接桿117更透過另一下向設置步驟向下設置以形成一第二向下設置部117b。另外，與連接桿117連接的晶片座116低於每一第二引腳114的第一接合區192以及第二接合區194，且第一封裝膠體130暴露出晶片座116的一下表面116b。因此，散熱表現，例如是半導體封裝結構100的散熱效率，可透過暴露晶片座116的下表面116b來提昇。
這些第一引腳112分別具有一從第一封裝膠體130之側邊延伸向外的外引腳部1124，其依序可形成標準引腳形態。
第二晶片140透過一黏著劑184穩固地貼附於凹穴132的一底表面132a，黏著劑184例如是銀膠或其他非導電的黏著劑，且第二晶片140透過這些打線124電性連接至這些第二引腳114。此外，一彈性膠體容置於凹穴132內以形成一覆蓋第二晶片140的第二封裝膠體160。在本實施例中，一停止結構170(stopper)，較佳地，形成於垂直環繞凹穴132之第一封裝膠體130的內壁內，以防止第二封裝膠體160溢出於凹穴132外。
需注意的是，至少第一封裝膠體130的一部分形成於第二晶片140與晶片座116之間，因此第二晶片140可直接配置第一封裝膠體130的部分上以取代晶片座116。由於第一封裝膠體130典型地具有一實質上等同於第二晶片140的熱膨脹係數(CTE)，因此上面所述之設計可顯著地減少第二晶片140與晶片座116之間的分層、晶片翹曲甚至是晶片裂化等問題。
此外，第一封裝膠體130包覆第一晶片120與第二晶片140皆配置於晶片座116的同一側邊，且第一封裝膠體 130包覆每一第二引腳114的端部1146與其上的第二接合區194，因此可防止於第一晶片120的打線製程與晶片接合步驟中於每一第二引腳114的端部1146上造成刮傷，可提升打線接合性。
第一封裝膠體130透過一習知封膠過程(molding process)，例如是轉移式封膠(transfer molding)，所形成。於封膠過程中，導線架110透過一上模具與一下模具(未繪示)來固定定位，其中上模具、下模具可一同定義一模穴，且此模穴通常是依據第一封裝膠體130來塑造。下模具較佳地具有一用以支撐這些第二引腳114之這些內引腳部1142的定位腳，可避免溢膠殘留於被暴露的上表面1142a。定位腳將會形成一洞136於第一封裝膠體130中。
於一實施例中，半導體封裝結構可應用於一胎壓監測系統(tire pressure measurement system,TPMS)(未繪示)中。在此實施例中，第一晶片120可以是一特殊應用積體電路(application specific integrated circuit,ASIC)，而第二晶片140可以是一壓力感測晶片。較佳地，用以形成第二封裝膠體160的封裝膠體具有充分的彈性，以允許感測晶片可反應週遭壓力的變化。較佳地，這些第一引腳112之外引腳部1124的設計是與現有規範之胎壓監測系統相容。
雖然於此實施例中詳細談論的半導體封裝結構100具有兩晶片，但一半導體封裝結構具有多於兩個晶片在應用的精神和範圍之內仍然被考慮。
本實施例更提供一封裝製程用以製作前述之半導體封裝結構。圖2A至圖2D繪示本發明之一實施例之一種封裝製程的示意圖。
首先，請參考圖2A，導線架110具有一晶片座116、複數個第一引腳112以及複數個第二引腳114。第一晶片120透過黏著劑182結合於晶片座116的上表面116a上，黏著劑182例如是銀膠或其他非導電的黏著劑，且第一晶片120透過這些打線122電性連接至這些第一引腳112與這些第二引腳114。其中，第一晶片120電性連接至每一第二引腳114之內引腳部1142的一上表面1142上的第二接合區194。
接著，請參考圖2B，形成第一封裝膠體130以包覆第一晶片120、晶片座116的上表面116a以及這些第一引腳112與這些第二引腳114的至少一部分。第一封裝膠體130具有一暴露出每一第二引腳114之第一接合區192的凹穴132，其中第一封裝膠體130的至少一部分形成以覆蓋位於晶片座116上的第一晶片120。第一封裝膠體130更暴露出晶片座116的下表面116b，且包覆每一第二引腳114的端部1146以及其上之第二接合區194。
接著，請參考圖2C，第二晶片140透過一黏著劑184穩固地貼附至凹穴132的一底表面132a，此凹穴132是直接位於第一晶片120上方之第一封裝膠體130的部分上，而黏著劑184例如是銀膠或其他非導電性之黏著劑，且第二晶片140透過這些打線124電性連接至每一第二引腳114的第一接合區192。
然後，請參考圖2D，形成第二封裝膠體160於第一封裝膠體130的凹穴132內以包覆第二晶片140。而且，蓋體150配置於第一封裝膠體130之凹穴132的上方。
於大量生產時，可想而知的是可同時形成多個導線架單位於一導線架條中，以便同時被製造多個半導體封裝結構。在上述之實施例中，於圖2D之步驟之後可進行一單體化步驟，而完成封裝製程。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100．．．半導體封裝結構
110．．．導線架
112．．．第一引腳
1124．．．外引腳部
114．．．第二引腳
1142．．．內引腳部
1142a．．．上表面
1146．．．端部
116．．．晶片座
116a．．．上表面
116b．．．下表面
117．．．連接桿
117a．．．第一向下設置部
117b．．．第二向下設置部
119．．．結合部
120．．．第一晶片
122．．．打線
124．．．打線
130．．．第一封裝膠體
132．．．凹穴
132a．．．底表面
136．．．洞
140．．．第二晶片
150．．．蓋體
152．．．開孔
160．．．第二封裝膠體
170．．．停止結構
182．．．黏著劑
184．．．黏著劑
192．．．第一接合區
194．．．第二接合區
圖1A與圖1B繪示本發明之一實施例之一種半導體封裝結構的示意圖。
圖2A至圖2D繪示本發明之一實施例之一種封裝製程的示意圖。
110．．．導線架
114．．．第二引腳
1142．．．內引腳部
1142a．．．上表面
1146．．．端部
116．．．晶片座
116a．．．上表面
116b．．．下表面
117．．．連接桿
117a．．．第一向下設置部
117b．．．第二向下設置部
120．．．第一晶片
122．．．打線
124．．．打線
130．．．第一封裝膠體
132．．．凹穴
132a．．．底表面
136．．．洞
140．．．第二晶片
150．．．蓋體
152．．．開孔
160．．．第二封裝膠體
170．．．停止結構
182．．．黏著劑
184．．．黏著劑
192．．．第一接合區
194．．．第二接合區

Claims (13)

  1. 一種半導體封裝結構，包括：一導線架，具有一晶片座以及環繞該晶片座配置的多個第一引腳與多個第二引腳；一第一晶片，配置於該晶片座的一上表面上，該第一晶片電性連接該些第一引腳與該些第二引腳；一第一封裝膠體，包覆該第一晶片、該晶片座的該上表面以及各該第一引腳與各該第二引腳的至少一部分，該第一封裝膠體暴露出該晶片座的一下表面，該第一封裝膠體具有一暴露出各該第二引腳之一第一接合區的凹穴，且該第一封裝膠體更包覆各該第二引腳朝向該晶片座延伸的一端部；一第二晶片，配置於該第一封裝膠體的該凹穴內且電性連接至該些第二引腳的該些第一接合區；以及一蓋體，配置於該第一封裝膠體之該凹穴的上方。
  2. 如申請專利範圍第1項所述之半導體封裝結構，更包括一黏著劑，其中該第二晶片透過該黏著劑配置於該第一封裝膠體之該凹穴的一底表面上。
  3. 如申請專利範圍第1項所述之半導體封裝結構，更包括一第二封裝膠體，配置於第一封裝膠體的該凹穴內，以包覆該第二晶片。
  4. 如申請專利範圍第1項所述之半導體封裝結構，其中該第二晶片為一感測晶片，且該蓋體具有一開孔，以允許該感測晶片連通該半導體封裝結構之外的環境。
  5. 如申請專利範圍第1項所述之半導體封裝結構，其中各該第二引腳具有該第一接合區以及一第二接合區，該第一接合區與該第二接合區配置於該第二引腳的一上表面上，該第二接合區位於該第二引腳的該端部且該第一封裝膠體包覆該第二接合區，而該第一晶片電性連接至該第二接合區。
  6. 如申請專利範圍第1項所述之半導體封裝結構，其中各該第二引腳的該第一接合區與該第二接合區向下設置以低於該第二引腳的其他部分。
  7. 如申請專利範圍第6項所述之半導體封裝結構，其中該晶片座向下設置以低於各該第二引腳的該第一接合區與該第二接合區，且該第一封裝膠體暴露出該晶片座的該下表面。
  8. 一種封裝製程，包括：提供一導線架，該導線架具有一晶片座以及環繞該晶片座配置的多個第一引腳以及多個第二引腳；配置一第一晶片於該晶片座的一上表面上；電性連接該第一晶片至該些第一引腳與該些第二引腳；包覆該第一晶片、該晶片座的該上表面以及各該第一引腳與各該第二引腳的至少一部分於一第一封裝膠體內，該第一封裝膠體具有一暴露出各該第二引腳之一第一接合區的凹穴，其中該第一封裝膠體的至少一部分形成以覆蓋該晶片座上的該第一晶片，該第一封裝膠體暴露出該晶片座的一下表面，且該第一封裝膠體更包覆各該第二引腳朝向該晶片座延伸的一端部；設置該第二晶片於該第一封裝膠體的該凹穴內且直接位在該第一晶片上方之該第一封裝膠體的部分上；電性連接該第二晶片至該些第二引腳的該些第一接合區；以及配置一蓋體於該第一封裝膠體的該凹穴的上方。
  9. 如申請專利範圍第8項所述之封裝製程，其中該第二晶片透過一黏著劑配置於該第一封裝膠體之該凹穴的一底表面上。
  10. 如申請專利範圍第8項所述之封裝製程，更包括提供一第二封裝膠體於該第一封裝膠體的該凹穴內，以包覆該第二晶片。
  11. 如申請專利範圍第8項所述之封裝製程，其中各該第二引腳具有該第一接合區以及一第二接合區，該第一接合區與該第二接合區配置於該第二引腳的一上表面，該第二接合區位於該第二引腳朝向該晶片座延伸的該端部且該第一封裝膠體包覆該第二接合區，而該第一晶片電性連接至該第二接合區。
  12. 如申請專利範圍第8項所述之封裝製程，其中各該第二引腳的該第一接合區與該第二接合區向下設置以低於該第二引腳的其他部分。
  13. 如申請專利範圍第12項所述之封裝製程，其中該晶片座向下設置以低於各該第二引腳的該第一接合區與該第二接合區，且該第一封裝膠體暴露出該晶片座的該下表面。
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