CN101925995B - 在复合结构上制造外延生长层的方法 - Google Patents

在复合结构上制造外延生长层的方法 Download PDF

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Publication number
CN101925995B
CN101925995B CN2009801025906A CN200980102590A CN101925995B CN 101925995 B CN101925995 B CN 101925995B CN 2009801025906 A CN2009801025906 A CN 2009801025906A CN 200980102590 A CN200980102590 A CN 200980102590A CN 101925995 B CN101925995 B CN 101925995B
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layer
oxide
carrier substrate
bonding
epitaxial growth
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Chinese (zh)
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CN101925995A (zh
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B·福雷
A·马尔科韦基奥
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Soitec SA
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Soitec SA
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/018—Bonding of wafers

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  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
CN2009801025906A 2008-01-21 2009-01-06 在复合结构上制造外延生长层的方法 Active CN101925995B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0850362A FR2926672B1 (fr) 2008-01-21 2008-01-21 Procede de fabrication de couches de materiau epitaxie
FR0850362 2008-01-21
PCT/EP2009/050086 WO2009092624A1 (en) 2008-01-21 2009-01-06 A method of fabricating epitaxially grown layers on a composite structure

Publications (2)

Publication Number Publication Date
CN101925995A CN101925995A (zh) 2010-12-22
CN101925995B true CN101925995B (zh) 2013-06-19

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CN2009801025906A Active CN101925995B (zh) 2008-01-21 2009-01-06 在复合结构上制造外延生长层的方法

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US (1) US8153500B2 (https=)
EP (1) EP2232546B1 (https=)
JP (1) JP5005097B2 (https=)
KR (1) KR101568890B1 (https=)
CN (1) CN101925995B (https=)
AT (1) ATE522930T1 (https=)
FR (1) FR2926672B1 (https=)
WO (1) WO2009092624A1 (https=)

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FR2926674B1 (fr) * 2008-01-21 2010-03-26 Soitec Silicon On Insulator Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable
KR20120052160A (ko) * 2010-11-15 2012-05-23 엔지케이 인슐레이터 엘티디 복합 기판 및 복합 기판의 제조 방법
FR2968121B1 (fr) * 2010-11-30 2012-12-21 Soitec Silicon On Insulator Procede de transfert d'une couche a haute temperature
CN102820393A (zh) * 2011-06-10 2012-12-12 光达光电设备科技（嘉兴）有限公司 复合衬底结构及其制作方法
US8927318B2 (en) * 2011-06-14 2015-01-06 International Business Machines Corporation Spalling methods to form multi-junction photovoltaic structure
US8633094B2 (en) 2011-12-01 2014-01-21 Power Integrations, Inc. GaN high voltage HFET with passivation plus gate dielectric multilayer structure
US8940620B2 (en) * 2011-12-15 2015-01-27 Power Integrations, Inc. Composite wafer for fabrication of semiconductor devices
US8928037B2 (en) 2013-02-28 2015-01-06 Power Integrations, Inc. Heterostructure power transistor with AlSiN passivation layer
FR3007892B1 (fr) * 2013-06-27 2015-07-31 Commissariat Energie Atomique Procede de transfert d'une couche mince avec apport d'energie thermique a une zone fragilisee via une couche inductive
JP6454606B2 (ja) * 2015-06-02 2019-01-16 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
FR3048548B1 (fr) * 2016-03-02 2018-03-02 Soitec Procede de determination d'une energie convenable d'implantation dans un substrat donneur et procede de fabrication d'une structure de type semi-conducteur sur isolant
JP6563360B2 (ja) * 2016-04-05 2019-08-21 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
FR3068508B1 (fr) * 2017-06-30 2019-07-26 Soitec Procede de transfert d'une couche mince sur un substrat support presentant des coefficients de dilatation thermique differents
SG11201913769RA (en) * 2017-07-14 2020-01-30 Sunedison Semiconductor Ltd Method of manufacture of a semiconductor on insulator structure
JP2019151896A (ja) * 2018-03-05 2019-09-12 日本特殊陶業株式会社 ＳｉＣ部材及びこれからなる基板保持部材並びにこれらの製造方法
FR3079660B1 (fr) * 2018-03-29 2020-04-17 Soitec Procede de transfert d'une couche
FR3108774B1 (fr) * 2020-03-27 2022-02-18 Soitec Silicon On Insulator Procede de fabrication d’une structure composite comprenant une couche mince en sic monocristallin sur un substrat support en sic
FR3108775B1 (fr) * 2020-03-27 2022-02-18 Soitec Silicon On Insulator Procede de fabrication d’une structure composite comprenant une couche mince en sic monocristallin sur un substrat support en sic
FR3111232B1 (fr) * 2020-06-09 2022-05-06 Soitec Silicon On Insulator Substrat temporaire demontable compatible avec de tres hautes temperatures et procede de transfert d’une couche utile a partir dudit substrat
CN114448372B (zh) * 2021-12-10 2025-12-12 上海新硅聚合半导体有限公司 一种异质薄膜衬底的制备方法和滤波器

Citations (3)

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Publication number Priority date Publication date Assignee Title
US20060186397A1 (en) * 2000-11-27 2006-08-24 S.O.I. Tec Silicon On Insulator Technologies S.A., A French Company Semiconductor substrates having useful and transfer layers
CN1826433A (zh) * 2003-07-24 2006-08-30 S.O.I.Tec绝缘体上硅技术公司 外延生长层的制造方法
US20060234486A1 (en) * 2005-04-13 2006-10-19 Speck James S Wafer separation technique for the fabrication of free-standing (Al,In,Ga)N wafers

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Publication number Priority date Publication date Assignee Title
FR2767604B1 (fr) 1997-08-19 2000-12-01 Commissariat Energie Atomique Procede de traitement pour le collage moleculaire et le decollage de deux structures
US6326279B1 (en) * 1999-03-26 2001-12-04 Canon Kabushiki Kaisha Process for producing semiconductor article
JP2000353797A (ja) * 1999-06-11 2000-12-19 Mitsubishi Electric Corp 半導体ウエハおよびその製造方法
FR2823599B1 (fr) 2001-04-13 2004-12-17 Commissariat Energie Atomique Substrat demomtable a tenue mecanique controlee et procede de realisation
FR2823596B1 (fr) * 2001-04-13 2004-08-20 Commissariat Energie Atomique Substrat ou structure demontable et procede de realisation
FR2835095B1 (fr) * 2002-01-22 2005-03-18 Procede de preparation d'ensembles a semi-conducteurs separables, notamment pour former des substrats pour l'electronique, l'optoelectrique et l'optique
FR2857982B1 (fr) 2003-07-24 2007-05-18 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
FR2858461B1 (fr) * 2003-07-30 2005-11-04 Soitec Silicon On Insulator Realisation d'une structure comprenant une couche protegeant contre des traitements chimiques
FR2860249B1 (fr) 2003-09-30 2005-12-09 Michel Bruel Procede de fabrication d'une structure en forme de plaque, en particulier en silicium, application de procede, et structure en forme de plaque, en particulier en silicium
FR2865574B1 (fr) 2004-01-26 2006-04-07 Soitec Silicon On Insulator Procede de fabrication d'un substrat demontable
JP2005005723A (ja) * 2004-06-25 2005-01-06 Hitachi Cable Ltd 窒化物半導体エピタキシャルウェハの製造方法及び窒化物半導体エピタキシャルウェハ

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060186397A1 (en) * 2000-11-27 2006-08-24 S.O.I. Tec Silicon On Insulator Technologies S.A., A French Company Semiconductor substrates having useful and transfer layers
CN1826433A (zh) * 2003-07-24 2006-08-30 S.O.I.Tec绝缘体上硅技术公司 外延生长层的制造方法
US20060234486A1 (en) * 2005-04-13 2006-10-19 Speck James S Wafer separation technique for the fabrication of free-standing (Al,In,Ga)N wafers

Also Published As

Publication number Publication date
FR2926672B1 (fr) 2010-03-26
EP2232546A1 (en) 2010-09-29
KR101568890B1 (ko) 2015-11-12
ATE522930T1 (de) 2011-09-15
US20100178749A1 (en) 2010-07-15
WO2009092624A1 (en) 2009-07-30
EP2232546B1 (en) 2011-08-31
JP5005097B2 (ja) 2012-08-22
JP2011510507A (ja) 2011-03-31
US8153500B2 (en) 2012-04-10
FR2926672A1 (fr) 2009-07-24
CN101925995A (zh) 2010-12-22
KR20100100980A (ko) 2010-09-15

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