CN101881986A - Ultralow temperature coefficient band-gap reference circuit based on mixed-mode high-order compensation - Google Patents
Ultralow temperature coefficient band-gap reference circuit based on mixed-mode high-order compensation Download PDFInfo
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Abstract
The invention publishes an ultralow temperature coefficient band-gap reference circuit based on mixed-mode high-order compensation, which comprises a band-gap reference current generating circuit, a feedback control loop, a temperature regulating circuit and an output circuit, wherein the band-gap reference current generating circuit comprises four PMOS (P-channel Metal Oxide Semiconductor) pipes, two NMOS (N-Mental Oxide Semiconductor) pipes, two resistors and two PNP (Plug-and-Play) triodes, the feedback control loop comprises two PMOS pipes, two NMOS pipes and two PNF (Power Noise Filter) triodes, the temperature regulating circuit comprises two NMOS pipes, and the output circuit comprises two PMOS pipes, four resistors and a PNP triode. The circuit has lower temperature coefficient, higher power supply rejection ratio and higher process stability.
Description
Technical field
The present invention relates to a kind of high-order temperature compensation bandgap reference circuit, be specifically related to a kind of mixed-mode high-order temperature compensation bandgap reference circuit, belong to the Analogical Circuit Technique field.
Background technology
Voltage or current reference circuit can provide not with the voltage or the current source of temperature and power source change for system, and reference precision is remarkable day by day to the influence and the effect of system performance.Band-gap reference because of have low-temperature coefficient, high Power Supply Rejection Ratio and with traditional cmos process advantage such as compatibility mutually, obtained to use widely.
Existing voltage-mode band-gap reference is in-40 ℃～125 ℃ temperature ranges, and temperature coefficient can drop in 10ppm/ ℃ after first-order linear compensation, high-order temperature compensatedly can further temperature coefficient be reduced to 3～5ppm/ ℃.The high-order temperature compensated of routine generally is the superposing control of utilizing the multi-channel compensating system electric current, collocation structure complexity not only, chip area footprints is bigger, and technology susceptibility height, can't overcome the influence of process drift to circuit performance, the maximum process drift of reference temperature coefficient reaches tens of times, and its performance and technology stability even not as good as corresponding first-order linear standard of compensation make the practical value of benchmark high-order compensation structure be difficult to embody.In addition, when temperature coefficient was low, the Power Supply Rejection Ratio of benchmark (PSRR) was affected and restricts more significantly, needs compromise to handle to satisfy the requirement of Circuits System to high precision reference.New high-order compensation should satisfy the overall target requirement of the Circuits System under the process stabilizing.
Summary of the invention
Technical matters: technical matters to be solved by this invention is at a kind of ultralow temperature coefficient band-gap reference circuit based on mixed-mode high-order compensation, band-gap reference circuit based on mismatch control under the negative feedback biasing, increase simple segmented compensation structure, realize a kind of mixed-mode high-order compensation method, on the basis that keeps higher Power Supply Rejection Ratio, further reduce temperature coefficient, improve the robustness that circuit technology realizes, satisfy the application need of Circuits System high-precision voltage reference.
Technical scheme: mixed-mode high-order temperature compensation bandgap reference circuit, comprise band-gap reference current generating circuit, feedback control loop, temperature regulation circuit and output circuit, wherein the band-gap reference current generating circuit by four PMOS manage, two NMOS pipe, two resistance and two PNP triodes constitute, two PMOS pipes of feedback control loop route, two NMOS pipes and two PNP triodes constitute, temperature regulation circuit is made of two NMOS pipes, and output circuit is made up of two PMOS pipe and four resistance and a PNP triode;
The band-gap reference current generating circuit: the source electrode of PMOS pipe and the 3rd PMOS pipe connects power supply respectively, the grid of the one PMOS pipe connects the grid of the 3rd PMOS pipe respectively, the drain electrode of the drain electrode of the 2nd PMOS pipe and a NMOS pipe, the drain electrode of the one PMOS pipe connects the source electrode of the 0th PMOS pipe, the drain electrode of the 3rd PMOS pipe connects the source electrode of the 2nd PMOS pipe, the drain electrode of the 0th PMOS pipe connects the drain electrode of the 0th NMOS pipe, the grid of the 0th PMOS pipe connects the grid of the 2nd PMOS pipe, the grid of the 0th NMOS pipe connects the grid of a NMOS pipe, the source electrode of the 0th NMOS pipe connects an end of zero resistance, the source electrode of the one NMOS pipe connects the emitter of a PNP triode, one end of another termination first resistance of zero resistance, the emitter of another termination the 0th PNP triode of first resistance, the collector of the 0th PNP triode respectively with the base stage of the 0th PNP pipe, the collector of the one PNP triode is connected ground connection with base stage;
Feedback control loop: the source electrode of the 6th PMOS pipe and the 7th PMOS pipe connects power supply respectively, the grid of the 6th PMOS pipe connects the grid of the 0th PMOS pipe respectively, the drain electrode of the drain electrode of the 2nd NMOS pipe and the 6th PMOS pipe, the grid of the 7th PMOS pipe connects the drain electrode of the 0th PMOS pipe, the drain electrode of the 7th PMOS pipe connects the drain and gate of the 3rd NMOS pipe respectively, the grid of the grid of the one NMOS pipe and the 2nd NMOS pipe, the source electrode of the 3rd NMOS pipe connects the emitter of the 3rd PNP pipe, the source electrode of the 2nd NMOS pipe connects the emitter of the 2nd PNP pipe, the collector of the 3rd PNP pipe respectively with the base stage of the 3rd PNP pipe, the base stage of the 2nd PNP pipe is connected ground connection with collector;
Temperature regulation circuit: the drain electrode of the 4th NMOS pipe is connected with the two ends of zero resistance respectively with source electrode, the grid of the 4th NMOS pipe is connected with an end or the other end of second resistance, the drain electrode of the 5th NMOS pipe is connected with the two ends of the 4th resistance respectively with source electrode, and the grid of the 5th NMOS pipe is connected with an end or the other end of second resistance;
Output circuit: the source electrode of the 5th PMOS pipe connects power supply, the drain electrode of the 5th PMOS pipe connects the source electrode of the 4th PMOS pipe, the grid of the 5th PMOS pipe connects the grid of a PMOS pipe, the drain electrode of the 4th PMOS pipe is connected in series the emitter that connects the 4th PNP pipe behind second resistance, the 3rd resistance, the 4th resistance, the 5th resistance successively, the grid of the 4th PMOS pipe connects the grid of the 0th PMOS pipe, and the base stage of the 4th PNP pipe is connected back ground connection with collector;
Beneficial effect: circuit of the present invention has lower temperature coefficient, higher Power Supply Rejection Ratio and higher technology stability.Simulation result based on SMIC 0.13 μ m CMOS technology shows that in-40 ℃～130 ℃ temperature ranges, the reference voltage temperature coefficient only is about 0.5ppm/ ℃, and average Power Supply Rejection Ratio can reach more than the 95dB in low-frequency range.
Description of drawings
Fig. 1 high-order temperature compensated circuit structure diagram of the present invention;
Fig. 2 is based on the reference voltage high-order compensation temperature characterisitic of single order nonequilibrium condition;
Fig. 3 benchmark high temperature segmentation NMOS compensates control structure;
The temperature characteristics figure of the output voltage of Fig. 4 reference circuit shown in Figure 1;
The PSRR performance plot of the output voltage of Fig. 5 reference circuit shown in Figure 1.
Embodiment
Enforcement of the present invention is divided into three parts, that is: the high-order compensation technology of (one) mismatch control, (two) self-adaption high-order segmented compensation technology, (three) mixed-mode high-order compensation technology.Be elaborated below in conjunction with the technical scheme of accompanying drawing to invention:
T-I type compensation: the high-order compensation technology of mismatch control
Among Fig. 1, do not consider temperature regulation circuit, if the current mirror in the reference current generating circuit mates fully, two branch road Q0 equate with electric current among the Q1, then can get single order rank linearity band-gap reference and be:
N is Q0 and the ratio of Q1 launch site area, V in the formula
T=KT/q is a thermal voltage, is approximately 26mV under the normal temperature.M is the current mirror transmission coefficient in the output circuit.R
n=R
0+ R
1, benchmark output transfer resistance R
Ref=R
3+ R
4+ R
5If consider V
EBThe nonlinear temperature characteristic and practical application in two branch currents mismatch then following formula should revise.
According to V
EBThe nonlinear temperature characteristic:
V in the formula
GBe the band gap voltage of silicon, normal temperature T
0=300K, γ, α are respectively the coefficient relevant with collector current index temperature coefficient with triode base hole mobility.Consider Q in the side circuit
0With Q
1The current mismatch of branch road, output reference voltage is modified to:
β=I in the formula
C1/ I
C0, as branch current I
C0(T) relative I
C1When (T) having small mismatch Δ I (T), β=1+ Δ I (T)/I
C0(T), the approximation relation according to x → 0 o'clock ln (1+x) ≈ x can get ln β ≈ Δ I (T)/I
C0(T).As long as Δ I is enough little, V
A=V
BCondition still effective, ln β ≈ R then
nΔ I/ (V
TLn/V).Consider the temperature characterisitic of resistance simultaneously:
R(T)＝R
0[1+TC
1(T-T
0)+TC
2(T-T
0)
2] (4)
R in the formula
0Be reference temperature T
0Under resistance, TC
1, TC
2Represent the single order and the second-order temperature coefficient of resistance respectively, and in normal temperature and high temperature range, work respectively.
Non-linear offset voltage V that introduces in (3) then
NLFor:
Because the temperature characterisitic of Δ I and resistance all is the function of temperature, in whole warm area variation range, if CONTROLLED POTENTIAL V
C0Be slightly larger than V
C1Because equating effect, PMOS cascode current mirror impressed current makes NM0, make triode Q0 thereby less variation takes place the NM1 source potential, electric current is along with temperature variation obtains electric current subtle change amount Δ I (T)＞0 among the Q1, the size of this amount of mismatch of reasonable disposition and polarity, and the resistance of resistance, can be with V
NLAs the high-order compensation amount the remaining non-linear negative temperature coefficient in the benchmark is effectively compensated.Because PMOS current mirror and feedback control loop electric current all show as the PTAT characteristic, PM3 grid voltage V
C1To change with temperature, simultaneously V
C0Temperature variation characteristic and V
C1Near-synchronous, the compensation approximately constant that makes the mismatch current item is that PTAT character is constant.V
PTATIn offset compensation amount ln β should be complementary with high-order nonlinear residuals temperatures coefficient amount, the nonuniform compensation effect of non-linear imbalance in whole warm area, require the complementary with it coupling of asymmetric temperature characterisitic of first compensation phase, so that, finally obtain minimum temperature coefficient based on the symmetrical distribution of recovery temperature curve behind the high-order compensation of mismatch control.
Temperature coefficient polarity difference in the benchmark under the nonlinear temperature Xiang Zaigao low-temperature space, low-temperature space is a positive temperature coefficient (PTC), enters high-temperature area and then changes negative temperature coefficient into, promptly Open Side Down for temperature curve.Asymmetric first compensation phase suitably increases the negative temperature coefficient amount, can further compensate the positive temperature coefficient (PTC) in low-temperature space, and the low-temperature space temperature coefficient is reduced; And the negative temperature coefficient in the high-temperature region can utilize the positive temperature coefficient (PTC) of non-linear mismatch current to compensate, and reduces the high-temperature region temperature coefficient, finally is implemented in the high-order compensation characteristic of reference temperature coefficient in the full warm area scope.
Mismatch for current mirror, the harmful effect that mismatch produces high precision reference under the usual conditions, need be compensated or effectively inhibition, but under the accurately controlled condition of current mirror mismatch numerical value and polarity, the non-linear current amount that the working point mismatch produces can become the effective ways of realizing high-order compensation control.The useful area that increases metal-oxide-semiconductor can effectively be controlled the mismatch size, in addition, a metal-oxide-semiconductor in the current mirror is split into the implementation in parallel of some same subunit, helps self mismatch level of Control current mirror equally.In the current mirror deviation formula of being derived by current equation, choosing of W and L should be optimized its overdrive voltage when electric current was identical, improved the currents match precision of current mirror with this.Since choosing, the optimization of circuit parameter can equally also can control the precision of mismatch with the control matching precision.
Fig. 4 (a) is circuit shown in Figure 1 (not considering temperature regulation circuit) V
RefThe temperature characteristics of=1.213V benchmark output can obtain from figure in-40 ℃～130 ℃ temperature ranges that the reference voltage temperature coefficient can be reduced to 1.16ppm/ ℃ after the nonlinear compensation of mismatch control.
T-II type compensation: self-adaption high-order segmented compensation technology
The temperature regulation circuit based on simple segmented compensation is mainly analyzed in this part, i.e. the high-order compensation effect of two NMOS pipe NM4 and NM5 among Fig. 1.
The temperature characterisitic of the balanced type first-order linear standard of compensation first order pole that Open Side Down or opening makes progress shown in Fig. 2 (a) is symmetrically distributed.Because the high-order segmented compensation only works at the local temperature section usually, so high-order compensation should be a starting point with non-equilibrium first-order linear compensated curve.Datum curve opening direction no matter, if adopt the compensation policy of low-temperature space, then the extreme point temperature of single order asymmetrical curve should move to high temperature; On the contrary, if adopt the compensation policy of high-temperature region, then the extreme point temperature of single order asymmetrical curve should move to low temperature.Behind the segmentation high-order compensation, original unimodal extreme value becomes bimodal even the multimodal extreme value, one of them limit is the limit that forms behind original first compensation phase, another limit is a limit newly-increased under the high-order compensation, ripple voltage in the wide warm area scope is changed reach new balance, obtain as Fig. 2 (b) and the temperature characterisitic of the compensation of second order (c) control benefit.
High-order compensation effective function temperature range can be low-temperature space, high-temperature region or whole warm area in theory, consider in the reality that to obtain high precision nonlinear compensation difficulty in full warm area scope bigger, therefore the high-order compensation effective temperature scope of selecting only accounts for the subrange of whole warm area, regulates the complexity of control to reduce the high-order temperature characteristics.
With the non-equilibrium single order reference temperature characteristic that Open Side Down is example, if the single order benchmark is less than normal in high temperature section output, shown in Fig. 2 (c), and it is high-order temperature compensated only effective at high temperature range, because high-order compensation is inoperative under medium and low temperature, promptly the original first compensation phase characteristic of this warm area is not influenced, so the size of the interior nonlinear compensation amount of simple adjustment high-temperature area, multipole value symmetrical balance type high-order compensation family curve can be obtained.For making high-order compensation only effective in the high-temperature region, this moment, the high-order compensation amount should be positive temperature coefficient (PTC).If the single order benchmark is less than normal in low-temperature zone output, shown in Fig. 2 (b), and injection is high-order temperature compensated effective in whole temperature range, this moment, the high-order compensation amount should be negative temperature coefficient, for difficulty is regulated in the high-order compensation characteristic and the reduction that obtain symmetrical balance, the high-order negative temperature coefficient that increases has promptly had obvious compensating action, the effect in the high-temperature region again can not be excessive in middle low-temperature space, and the difficulty relatively-high temperature degree district nonlinear compensation of regulating control is controlled difficulty obviously to be increased.For the benchmark compensation that opening makes progress, similar analysis shows the easier accurate control of the compensation of high-temperature region equally.In a word, in four kinds of possible high-order compensation control strategies that Fig. 2 provides, have only the high-order compensation of Fig. 2 (c) at the high-temperature region positive temperature coefficient (PTC) that Open Side Down, or the high-order compensation of the high-temperature region negative temperature coefficient that makes progress at opening of Fig. 2 (b), help the realization of control structure and the raising of degree of regulation most.
To metal-oxide-semiconductor driving voltage V
GSControl, but realization theory is analyzed the control of desired high temperature section segmented compensation.Basic control strategy is, under the low temperature because of the V of metal-oxide-semiconductor
GS＜V
THAnd do not have the ancillary relief electric current, and after temperature raises, one side V
THDescend, simultaneously V
GSIncrease, both cooperations can make after temperature surpasses a certain critical point metal-oxide-semiconductor because of V
GS＞V
THAnd conducting, the high more offset current that provides of temperature is also big more, when high temperature positive temperature coefficient (PTC) electric current is injected in the output branch road, can realize the nonlinear temperature compensating coefficient control under the high temperature.
The benchmark collocation structure of realizing above control principle as shown in Figure 3.Among Fig. 3 (a), the grid of compensating pipe Mc connect output reference voltage, promptly keep V
G≈ V
RefDo not vary with temperature control V
SV during current potential just makes under the low temperature
GS=V
Ref-V
SLess than the cut-in voltage under this temperature, offset current is zero, and the offset current of positive temperature coefficient (PTC) can be provided after the Mc conducting under the high temperature.The V that is provided with
SCurrent potential is high more, and the corresponding effective initial temperature of compensation is also high more, and the compensating pipe size is big more, and offset current is big more.Because the leakage of compensating pipe Mc directly connects supply voltage, or provides required voltage bias by other branch road, constitute the simple offset current injection type control structure of output branch road relatively.But because M
CCompensating pipe generally all is operated in saturated constant current district, and the offset current that provides is bigger, and the influence of technology imbalance is more remarkable.
Be to suppress the influence of technology imbalance, can be with the drain voltage of Mc pipe by power supply V
DDDriving changes current potential V into
DScalable drives, i.e. Mc shown in Fig. 3 (b) and the parallel-connection structure of Rc, the flow-dividing control mechanism of formation offset current.When temperature variation, no matter how the conducting state of compensating pipe Mc changes, it is former regular constant that total current among Mc and the Rc keeps, the conducting state that is the Mc offset current does not exert an influence to the temperature characterisitic of the other parts of output in the branch road, and only to the temperature characterisitic generation effect of part voltage drop in parallel.Equivalent resistance in parallel is reduced, cause the voltage of parallel-connection structure to reduce, form the compensation mechanism that negative temperature coefficient strengthens under the high temperature.Among Fig. 3, the selection that the selection of Vs voltage should make compensating pipe be operated in weak inversion regime, parallel resistance Rc then makes compensating pipe be in the linear resistance district, and the suitable W/L parameter of design compensation pipe realizes the effective control to faint high-order compensation amount simultaneously.As seen, for the single tube collocation structure, in a certain specified temp section, adjust the gate source voltage of compensating pipe Mc and can realize compensation effect preferably, the especially adjusting that this structure can be stronger to the reference voltage temperature coefficient in the high-temperature region.
Select the suitable W/L parameter of NM5 pipe, grid terminal potential (meeting a or b) and source terminal potential (by R5 and Q4 pressure drop decision) among Fig. 1, make it only begin conducting in the high-temperature region, inoperative under the middle low temperature, because NM5 manages effective driving voltage and the conducting electric current increases with the temperature rising, the electric current positive temperature coefficient (PTC) that flows through R4 reduces, output voltage reduces, and forms Fig. 2 (b) opening second order compensation characteristic shown in the high-temperature region that makes progress.Because NM5 pipe gate source voltage and temperature characterisitic thereof can freely dispose within the specific limits, therefore can be by configuration V
GSVoltage selects suitable high temperature compensatory zone and temperature coefficient thereof to obtain required second order compensation characteristic.
The NM4 pipe is arranged on middle warm area conducting.Select the suitable W/L parameter of NM4 pipe, grid terminal potential (meeting a or b) and source terminal potential (by R1 and Q0 pressure drop decision), make the NM4 pipe be in the subthreshold value high resistance area all the time, owing to cause the trace of this branch road all-in resistance to reduce with the effect in parallel of R0 after the conducting of NM4 pipe, thereby make the faint increase of PTAT electric current of this branch road, the PTAT offset current that increases is mirrored to the output branch road by the Cascode current mirror, be converted into the PTAT bucking voltage, output voltage is raise, form Fig. 2 (c) Open Side Down the second order compensation characteristic shown in the high-temperature region.Because NM4 pipe gate source voltage and temperature characterisitic thereof can freely dispose within the specific limits, therefore can be by configuration V
GSVoltage selects suitable middle high temperature compensatory zone and temperature coefficient thereof to obtain required second order compensation characteristic.
More than two kinds of NMOS pipes in parallel to the incompatibility that influences of output temperature characteristic, therefore can be used.Shown in Fig. 2 (d), to the asymmetric temperature characteristics of the single order that Open Side Down, its very high peak point (zero-temperature coefficient equilibrium point) A is moved to low-temperature space, the temperature characterisitic that negative temperature coefficient strengthens under the high temperature in the formation; Allow the NM4 pipe play a leading role then, positive temperature coefficient (PTC) is improved, form utmost point low peak point B at middle warm area; Because the NM4 pipe works equally in the high-temperature region, when the output reference positive temperature coefficient (PTC) was excessive, the beginning of NM5 pipe played a leading role in the high-temperature region, and output reference begins to descend, and second very high peak point C occur.NM4 and NM5 two pipes cooperate the temperature characteristics that can occur " the M shape " of a utmost point low peak point and two very high peak points at full warm area.
The mixed-mode high-order compensation technology
According to above two parts as can be known to the in-depth analysis of the high-order compensation technology (T-I type) of mismatch control and self-adaption high-order segmented compensation technology (T-II type), effective scope of application difference of two kinds of compensation principles, and the compensation control mode is separate, thereby the use that can cooperatively interact.Wherein the control compensation structure of simple single tube mainly plays the high-order compensation effect in the T-II type in middle high-temperature temperature scope, and T-I type temperature compensation is effective in whole temperature range, and does not need complicated compensating circuit.So,, just might in a wider temperature range, realize the voltage reference that temperature coefficient is lower with less cost in conjunction with this compensation technique of two types.
For the single order temperature coefficient curve that Open Side Down, because it is at equilibrium point T
0The time temperature coefficient be zero, as T＜T
0The time, positive temperature coefficient (PTC) is greater than negative temperature coefficient, as T＞T
0The time, negative temperature coefficient is greater than positive temperature coefficient (PTC).Therefore the adjusting to the single order equilibrium point can make the single order temperature curve show unbalanced Positive and Negative Coefficient Temperature in middle high-temperature scope He in the medium and low temperature scope, and this nonequilibrium single order temperature curve can obtain with the compensation method of T-I type earlier, because the compensation of T-I type has no requirement to the characteristic opening direction of single order voltage temperature, and T-II type method compensation effect optimum in some temperature ranges, it is comparatively suitable therefore to adopt T-I type technology at first to compensate.Asymmetrical single order temperature curve can make its zero-temperature coefficient equilibrium point move to high temperature range by regulating, for utilizing the compensation of T-I type in the middle low-temperature space, the size that only needs to regulate amount of mismatch just can be controlled at remaining positive temperature coefficient (PTC) in the medium and low temperature scope in the single order reference temperature family curve in the littler scope, because the T-I type belongs to the total temperature regional compensation, so control suitable single order equilibrium point can after, originally the stronger negative temperature coefficient in high-temperature region becomes very little, even flex point occurs and make high-temperature region positive temperature coefficient (PTC) effect strengthen.At this moment, utilize the unique advantage of T-II type compensation technique to carry out effective compensation of middle high-temperature region again, promptly have the more high-order compensation that the opposite temperature coefficients electric current is realized temperature characteristics, thereby make the reference voltage temperature curve after the compensation in complete wide temperature range, realize extremely low temperature coefficient by injection.
In like manner, the single order temperature curve that makes progress for opening, still can carry out high-order compensation with the compensation method of T-I type earlier, again the residual temperature coefficient after the compensation be carried out selectable T-II type compensation, finally realize the more fine compensation of second order reference voltage residual temperature coefficient.Obviously, the mixed mode compensation technique of compatible T-I type and T-II type compensation technique, compensation way is very flexible, can realize the higher temperature accuracy of second order compensation in theory than various stand-alone modes, but the circuit conditioning difficulty also obviously increases, not only to regulate the residual temperature characteristic of single order temperature characterisitic, and need further analyze and judge, and then adopt the T-II type temperature compensation of appropriate characteristics to finish whole voltage reference design T-I type compensation back temperature coefficient characteristics.
Can adopt following mixed-mode high-order compensation implementation method flexibly according to the temperature characteristics characteristics after the compensation of T-I type to circuit shown in Figure 1:
(1) T-I type compensation+single tube T-II type compensation (NM4 pipe): if under middle low temperature, obtain the lower temperature characteristics of bipolar peak value point " M shape " or multipole peak value point with the compensation of T-I type, can only carry out the high-temperature region compensation with the NM4 pipe, obtain high temperature " V-arrangement " temperature curve, temperature characteristics shown in final formation Fig. 4 (b), in-40 ℃～130 ℃ temperature ranges, its temperature coefficient is 0.52ppm/ ℃.The method is easier to regulate, and temperature coefficient can be controlled in the 0.5～1ppm/ ℃ of scope usually.
(2) T-I type compensation+two-tube T-II type compensation (NM4 pipe and NM5 pipe): if under middle low temperature, obtain the lower temperature characteristics of " N shape " with the compensation of T-I type, high-temperature region compensation in can carrying out with the NM5 pipe earlier, carry out the high-temperature region compensation with the NM4 pipe again, obtain middle high-temperature region " N shape " temperature curve, finally also can form temperature characteristics shown in Fig. 4 (b); If under middle low temperature, obtain same (1) the same bipolar peak value point " M shape " or the lower temperature characteristics of multipole peak value point with the compensation of T-I type, high-temperature region compensation in also can carrying out with the NM4 pipe earlier, carry out the high-temperature region compensation with the NM5 pipe again, obtain " N shape " temperature curve of middle high-temperature region, temperature characteristics shown in final formation Fig. 4 (c), in-40 ℃～130 ℃ temperature ranges, its temperature coefficient is 0.44ppm/ ℃, the temperature coefficient that the method obtains can be controlled in 0.5ppm/ ℃ usually, but regulates difficulty.
To above two kinds of mixed-mode high-order compensation implementation methods, select the Fig. 4 (b) and (c) circuit of correspondence, in given-40 ℃～130 ℃ full warm area scopes, to (TT, SS, SNFP, FNSP, FF) the reference temperature characteristic under five kinds of typical process angles is carried out simulating, verifying, and its temperature coefficient is respectively (0.52,8.23,2.06,2.38,14.83) and ppm/ ℃, (0.44,9.78,2.21,3.74,25.62) and ppm/ ℃, as seen except temperature under SS and FF process corner is floated greatly, temperature under all the other process corner is floated and is can be controlled in 4ppm/ ℃, has technology stability preferably, repaiies for resistance and transfers acquisition optimum temperature coefficient that condition is provided.
Fig. 5 has provided the PSRR family curve of Fig. 1 mixed-mode high-order compensation circuit, two curves corresponding diagram 4 (b) and (c) PSRR characteristic of related circuit respectively among the figure, the result shows in low-frequency range, its PSRR absolute value is respectively 96.3dB and 102.2dB, and average Power Supply Rejection Ratio can reach more than the 95dB.
Because the inner negative feedback of employing reaches the control based on circuit internal work state point, the circuit that the present invention proposes is in the nature with the first compensation phase structural property to obtain the effect of high-order compensation, simple in structure, on the basis that guarantees higher Power Supply Rejection Ratio, temperature coefficient is reduced to 0.5ppm/ ℃ of magnitude simultaneously, and have technology stability preferably.High-order compensation structure with respect to other type has remarkable advantages aspect the high-precision low cost.
Specifically consist of;
The band-gap reference current generating circuit: the source electrode of PMOS pipe PM1 and the 3rd PMOS pipe PM3 meets power vd D respectively, the grid of the one PMOS pipe PM1 connects the grid of the 3rd PMOS pipe PM3 respectively, the drain electrode of the drain electrode of the 2nd PMOS pipe PM2 and NMOS pipe NM1, the drain electrode of the one PMOS pipe PM1 connects the source electrode of the 0th PMOS pipe PM0, the drain electrode of the 3rd PMOS pipe PM3 connects the source electrode of the 2nd PMOS pipe PM2, the drain electrode of the 0th PMOS pipe PM0 connects the drain electrode of the 0th NMOS pipe NMO, the grid of the 0th PMOS pipe PM0 connects the grid of the 2nd PMOS pipe PM2, the grid of the 0th NMOS pipe NMO connects the grid of NMOS pipe NM1, the source electrode of the 0th NMOS pipe NMO connects the end of zero resistance R0, the source electrode of the one NMOS pipe NM1 connects the emitter of a PNP triode Q1, one end of another termination first resistance R 1 of zero resistance R0, the emitter of another termination the 0th PNP triode Q0 of first resistance R 1, collector and the base stage of the 0th PNP triode Q0, the collector of the one PNP triode Q1 is connected ground connection GND with base stage;
Feedback control loop: the source electrode of the 6th PMOS pipe PM6 and the 7th PMOS pipe PM7 meets power vd D respectively, the grid of the 6th PMOS pipe PM6 connects the grid of the 0th PMOS pipe PM0 respectively, the drain electrode of the drain electrode of the 2nd NMOS pipe NM2 and the 6th PMOS pipe PM6, the grid of the 7th PMOS pipe PM7 connects the drain electrode of the 0th PMOS pipe PM0, the drain electrode of the 7th PMOS pipe PM7 connects the drain and gate of the 3rd NMOS pipe NM3 respectively, the grid of the 0th NMOS pipe NM0, the grid of the grid of the one NMOS pipe NM1 and the 2nd NMOS pipe NM2, the source electrode of the 3rd NMOS pipe NM3 connects the emitter of the 3rd PNP pipe Q3, the source electrode of the 2nd NMOS pipe NM2 connects the emitter of the 2nd PNP pipe Q2, collector and the base stage of the 3rd PNP pipe Q3, the base stage of the 2nd PNP pipe Q2 is connected ground connection GND with collector;
Temperature regulation circuit: the drain electrode of the 4th NMOS pipe NM4 is connected with the two ends of zero resistance R0 respectively with source electrode, the grid of the 4th NMOS pipe NM4 is connected with an end of second resistance R 2, the drain electrode of the 5th NMOS pipe NM5 is connected with the two ends of the 4th resistance R 4 respectively with source electrode, and the grid of the 5th NMOS pipe NM5 is connected with an end of second resistance R 2;
Output circuit: the source electrode of the 5th PMOS pipe PM5 meets power vd D, the drain electrode of the 5th PMOS pipe PM5 connects the source electrode of the 4th PMOS pipe PM4, the grid of the 5th PMOS pipe PM5 connects the grid of PMOS pipe PM1, after being connected in series second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5 successively, the drain electrode of the 4th PMOS pipe PM4 connects the emitter that the 4th PNP manages Q4, the grid of the 4th PMOS pipe PM4 connects the grid of the 0th PMOS pipe PM0, and the base stage of the 4th PNP pipe Q4 is connected back ground connection GND with collector.
Claims (1)
1. the ultralow temperature coefficient band-gap reference circuit based on mixed-mode high-order compensation is characterized in that comprising band-gap reference current generating circuit, feedback control loop, temperature regulation circuit and output circuit; Wherein the band-gap reference current generating circuit by four PMOS manage, two NMOS pipe, two resistance and two PNP triodes constitute, two PMOS pipes of feedback control loop route, two NMOS pipes and two PNP triodes constitute, temperature regulation circuit is made of two NMOS pipes, and output circuit is made up of two PMOS pipes and a PNP triode;
The band-gap reference current generating circuit: the source electrode of PMOS pipe (PM1) and the 3rd PMOS pipe (PM3) connects power supply (VDD) respectively, the grid of the one PMOS pipe (PM1) connects the grid of the 3rd PMOS pipe (PM3) respectively, the drain electrode of the drain electrode of the 2nd PMOS pipe (PM2) and NMOS pipe (NM1), the drain electrode of the one PMOS pipe (PM1) connects the source electrode of the 0th PMOS pipe (PM0), the drain electrode of the 3rd PMOS pipe (PM3) connects the source electrode of the 2nd PMOS pipe (PM2), the drain electrode of the 0th PMOS pipe (PM0) connects the drain electrode of the 0th NMOS pipe (NM0), the grid of the 0th PMOS pipe (PM0) connects the grid of the 2nd PMOS pipe (PM2), the grid of the 0th NMOS pipe (NM0) connects the grid of NMOS pipe (NM1), the source electrode of the 0th NMOS pipe (NM0) connects an end of zero resistance (R0), the source electrode of the one NMOS pipe (NM1) connects the emitter of a PNP triode (Q1), one end of another termination first resistance (R1) of zero resistance (R0), the emitter of another termination the 0th PNP triode (Q0) of first resistance (R1), the collector and the base stage of the 0th PNP triode (Q0), the collector of the one PNP triode (Q1) is connected ground connection (GND) with base stage;
Feedback control loop: the source electrode of the 6th PMOS pipe (PM6) and the 7th PMOS pipe (PM7) connects power supply (VDD) respectively, the grid of the 6th PMOS pipe (PM6) connects the grid of the 0th PMOS pipe (PM0) respectively, the drain electrode of the drain electrode of the 2nd NMOS pipe (NM2) and the 6th PMOS pipe (PM6), the grid of the 7th PMOS pipe (PM7) connects the drain electrode of the 0th PMOS pipe (PM0), the drain electrode of the 7th PMOS pipe (PM7) connects the drain and gate of the 3rd NMOS pipe (NM3) respectively, the grid of the 0th NMOS pipe (NMO), the grid of the grid of the one NMOS pipe (NM1) and the 2nd NMOS pipe (NM2), the source electrode of the 3rd NMOS pipe (NM3) connects the emitter of the 3rd PNP pipe (Q3), the source electrode of the 2nd NMOS pipe (NM2) connects the emitter of the 2nd PNP pipe (Q2), the collector and the base stage of the 3rd PNP pipe (Q3), the base stage of the 2nd PNP pipe (Q2) is connected ground connection (GND) with collector;
Temperature regulation circuit: the drain electrode of the 4th NMOS pipe (NM4) is connected with the two ends of zero resistance (R0) respectively with source electrode, the grid of the 4th NMOS pipe (NM4) is connected with an end of second resistance (R2), the drain electrode of the 5th NMOS pipe (NM5) is connected with the two ends of the 4th resistance (R4) respectively with source electrode, and the grid of the 5th NMOS pipe (NM5) is connected with an end of second resistance (R2);
Output circuit: the source electrode of the 5th PMOS pipe (PM5) connects power supply (VDD), the drain electrode of the 5th PMOS pipe (PM5) connects the source electrode of the 4th PMOS pipe (PM4), the grid of the 5th PMOS pipe (PM5) connects the grid of PMOS pipe (PM1), the drain electrode of the 4th PMOS pipe (PM4) is connected in series second resistance (R2) successively, the 3rd resistance (R3), the 4th resistance (R4), connect the emitter of the 4th PNP pipe (Q4) behind the 5th resistance (R5), the grid of the 4th PMOS pipe (PM4) connects the grid of the 0th PMOS pipe (PM0), and the base stage of the 4th PNP pipe (Q4) is connected back ground connection (GND) with collector.
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