CN101866824B - 用于再生衬底的表面的方法 - Google Patents

用于再生衬底的表面的方法 Download PDF

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Publication number
CN101866824B
CN101866824B CN200910246888.6A CN200910246888A CN101866824B CN 101866824 B CN101866824 B CN 101866824B CN 200910246888 A CN200910246888 A CN 200910246888A CN 101866824 B CN101866824 B CN 101866824B
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China
Prior art keywords
layer
substrate
protruding
topography
filling material
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Expired - Fee Related
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CN200910246888.6A
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English (en)
Chinese (zh)
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CN101866824A (zh
Inventor
阿齐兹·哈拉米-艾蒂里斯
塞巴斯蒂安·凯尔迪勒
沃尔特·施瓦岑贝格
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Soitec SA
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Soitec SA
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Publication of CN101866824A publication Critical patent/CN101866824A/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/12—Preparing bulk and homogeneous wafers
    • H10P90/16—Preparing bulk and homogeneous wafers by reclaiming or re-processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Mechanical Treatment Of Semiconductor (AREA)
CN200910246888.6A 2009-02-12 2009-12-16 用于再生衬底的表面的方法 Expired - Fee Related CN101866824B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP09290104A EP2219208B1 (en) 2009-02-12 2009-02-12 Method for reclaiming a surface of a substrate
EP09290104.0 2009-02-12

Publications (2)

Publication Number Publication Date
CN101866824A CN101866824A (zh) 2010-10-20
CN101866824B true CN101866824B (zh) 2014-03-05

Family

ID=40725919

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200910246888.6A Expired - Fee Related CN101866824B (zh) 2009-02-12 2009-12-16 用于再生衬底的表面的方法

Country Status (7)

Country Link
US (1) US8435897B2 (https=)
EP (1) EP2219208B1 (https=)
JP (1) JP5219094B2 (https=)
KR (1) KR101536334B1 (https=)
CN (1) CN101866824B (https=)
SG (1) SG164310A1 (https=)
TW (1) TWI480939B (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100022070A1 (en) * 2008-07-22 2010-01-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing soi substrate
FR2971365B1 (fr) * 2011-02-08 2013-02-22 Soitec Silicon On Insulator Méthode de recyclage d'un substrat source
JP5799740B2 (ja) * 2011-10-17 2015-10-28 信越半導体株式会社 剥離ウェーハの再生加工方法
CN103646867B (zh) * 2013-11-29 2016-04-06 上海华力微电子有限公司 改善晶圆剥落缺陷的方法
JP6676365B2 (ja) * 2015-12-21 2020-04-08 キヤノン株式会社 撮像装置の製造方法
FR3074608B1 (fr) * 2017-12-05 2019-12-06 Soitec Procede de preparation d'un residu de substrat donneur, substrat obtenu a l'issu de ce procede, et utilisation d'un tel susbtrat
US10373818B1 (en) * 2018-01-31 2019-08-06 Taiwan Semiconductor Manufacturing Co., Ltd. Method of wafer recycling
SE1950611A1 (en) * 2019-05-23 2020-09-29 Ascatron Ab Crystal efficient SiC device wafer production
FR3120159B1 (fr) 2021-02-23 2023-06-23 Soitec Silicon On Insulator Procédé de préparation du résidu d’un substrat donneur ayant subi un prélèvement d’une couche par délamination
CN113192823B (zh) * 2021-04-27 2022-06-21 麦斯克电子材料股份有限公司 一种soi键合工艺后衬底片的再生加工方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1221218A (zh) * 1997-12-26 1999-06-30 索尼株式会社 半导体衬底和薄膜器件及其制造方法以及阳极化处理装置
CN1234601A (zh) * 1998-01-30 1999-11-10 佳能株式会社 Soi衬底的回收方法和再生的衬底
CN1466170A (zh) * 2002-06-04 2004-01-07 中芯国际集成电路制造(上海)有限公司 可重复使用的晶圆控片及其形成方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5867302A (en) * 1997-08-07 1999-02-02 Sandia Corporation Bistable microelectromechanical actuator
US6863593B1 (en) 1998-11-02 2005-03-08 Applied Materials, Inc. Chemical mechanical polishing a substrate having a filler layer and a stop layer
JP3943782B2 (ja) * 1999-11-29 2007-07-11 信越半導体株式会社 剥離ウエーハの再生処理方法及び再生処理された剥離ウエーハ
CN100557785C (zh) * 2002-08-26 2009-11-04 S.O.I.Tec绝缘体上硅技术公司 具有缓冲结构的晶片的再循环
JP4492054B2 (ja) * 2003-08-28 2010-06-30 株式会社Sumco 剥離ウェーハの再生処理方法及び再生されたウェーハ
US6987055B2 (en) * 2004-01-09 2006-01-17 Micron Technology, Inc. Methods for deposition of semiconductor material
US7402520B2 (en) * 2004-11-26 2008-07-22 Applied Materials, Inc. Edge removal of silicon-on-insulator transfer wafer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1221218A (zh) * 1997-12-26 1999-06-30 索尼株式会社 半导体衬底和薄膜器件及其制造方法以及阳极化处理装置
CN1234601A (zh) * 1998-01-30 1999-11-10 佳能株式会社 Soi衬底的回收方法和再生的衬底
CN1466170A (zh) * 2002-06-04 2004-01-07 中芯国际集成电路制造(上海)有限公司 可重复使用的晶圆控片及其形成方法

Also Published As

Publication number Publication date
SG164310A1 (en) 2010-09-29
KR20100092363A (ko) 2010-08-20
EP2219208A1 (en) 2010-08-18
US20100200854A1 (en) 2010-08-12
TW201030830A (en) 2010-08-16
KR101536334B1 (ko) 2015-07-13
TWI480939B (zh) 2015-04-11
JP5219094B2 (ja) 2013-06-26
EP2219208B1 (en) 2012-08-29
JP2010186987A (ja) 2010-08-26
CN101866824A (zh) 2010-10-20
US8435897B2 (en) 2013-05-07

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Owner name: SAWTEK INC.

Free format text: FORMER NAME: SOITEC SILICON ON INSULATOR

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Address after: French Boerning

Patentee after: Soitec Silicon On Insulator

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Patentee before: Silicon on Insulator Technologies S. A.

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Granted publication date: 20140305

Termination date: 20181216