CN101834162A - 芯片封装结构及方法 - Google Patents

芯片封装结构及方法 Download PDF

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CN101834162A
CN101834162A CN200910106126A CN200910106126A CN101834162A CN 101834162 A CN101834162 A CN 101834162A CN 200910106126 A CN200910106126 A CN 200910106126A CN 200910106126 A CN200910106126 A CN 200910106126A CN 101834162 A CN101834162 A CN 101834162A
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chip
cushion layer
bed course
width
spacing cushion
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傅敬尧
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AMBIT ELECTRONICS (ZHONGSHAN) Co Ltd
Hon Hai Precision Industry Co Ltd
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AMBIT ELECTRONICS (ZHONGSHAN) Co Ltd
Hon Hai Precision Industry Co Ltd
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Priority to US12/507,154 priority patent/US20100230826A1/en
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Abstract

一种芯片封装结构，包括基板、间隔垫层、芯片及多个焊线。基板上设有多个金手指，间隔垫层与基板一体成型。芯片通过黏着剂固定于间隔垫层上，所述芯片包括多个焊垫。所述间隔垫层的长度和宽度小于所述芯片的长度和宽度。所述焊线电性连接所述金手指和所述焊垫。因为间隔垫层的长度和宽度小于芯片的长度和宽度，从而在黏晶过程中，银胶不会污染基板的金手指和芯片。本发明还提供一种芯片封装方法。

Description

芯片封装结构及方法
技术领域
本发明涉及一种芯片封装结构，尤指一种防止黏晶胶污染芯片的封装结构。
背景技术
在电子产品功能不断增加而体积又必须轻薄短小的趋势下，芯片的体积也必须轻薄短小，从而芯片的封装已成为封装产业普遍面对的挑战。
请参照图4，揭示了一种现有芯片封装结构500。所述芯片封装结构500包括基板510、间隔垫层520、芯片530、多个焊线540及黏着剂550，间隔垫层520的长度和宽度大于芯片530的长度和宽度。在芯片530封装过程中，间隔垫层520首先在黏晶站通过黏着剂550固定于基板510上，再将芯片530通过黏着剂550固定于间隔垫层520上。接着在打线站将芯片530的焊垫532与基板510的金手指512通过焊线540电性连接。最后再以黑胶560将芯片530和焊线540封固于其中。
然而因间隔垫层520的长度和宽度大于芯片530的长度和宽度，在黏晶过程中很容易发生溢胶而造成银胶污染芯片，进而造成产品不良率上升。同时，因需单独制作和组装间隔垫层520，而延长了生产周期，增加了成本。
发明内容
有鉴于此，需提供一种防止黏晶胶污染芯片的芯片封装结构。
还需提供一种防止黏晶胶污染芯片的芯片封装方法。
一种芯片封装结构，包括基板、间隔垫层、芯片及多个焊线。基板上设有多个金手指，间隔垫层与基板一体成型。芯片是通过黏着剂固定于间隔垫层之上，所述芯片包括多个焊垫。所述间隔垫层的长度和宽度小于所述芯片的长度和宽度。所述焊线电性连接所述金手指和所述焊垫。
一种芯片封装方法，用于将芯片封装于基板上，所述芯片包括多个焊垫，所述基板包括多个金手指。所述方法包括：在基板上以电镀方式生成间隔垫层；将所述芯片固定于所述间隔垫层上；电性连接所述金手指和所述焊垫；及封装所述芯片；其中，所述间隔垫层的长度和宽度小于所述芯片的长度和宽度。
本发明的芯片封装结构，因为间隔垫层的长度和宽度小于芯片的长度和宽度，从而在黏晶过程中，银胶不会污染基板的金手指和芯片。
附图说明
图1是本发明的芯片封装结构的剖视示意图。
图2是本发明另一种实施方式的芯片封装结构的剖视示意图。
图3是本发明的芯片封装方法。
图4是现有芯片封装结构的剖视示意图。
具体实施方式
图1是本发明的芯片封装结构100的剖视示意图。本发明的芯片封装结构100包括基板10、间隔垫层20、芯片30、多个焊线40及黏着剂50。
基板10为印刷电路板，其上设有多个金手指12。
间隔垫层20与基板10一体成型。间隔垫层20的厚度大于金手指12的厚度，其长度和宽度小于芯片30的长度和宽度。多个金手指12分布于间隔垫层20的外围。在本实施方式中，间隔垫层20与金手指12的材质相同，均为导电材料，且间隔垫层20的制造方法与金手指12的制造方法一样，均通过电镀方式生成。在其它实施方式中，间隔垫层20的材质也可与金手指12的材质不相同，为其它导电材料，如硅胶或其它热膨胀系数与芯片30接近的金属。
芯片30包括多个焊垫32，所述焊垫32通过所述焊线40与基板10上的金手指12电性连接。在本实施方式中，芯片30为厚度小于或等于50微米(um)的薄芯片。
黏着剂50用于将芯片30黏着于间隔垫层20之上。在本实施方式中，黏着剂50为银胶。因间隔垫层20的尺寸小于芯片30的尺寸，从而间隔垫层20与焊垫32以及金手指12之间有较大的缓冲空间，所以不至于因为溢胶或其它银胶控制不良的问题而污染焊垫32及金手指12。且间隔垫层20的厚度大于基板10金手指12的厚度，进一步加大了间隔垫层20与金手指12之间的缓冲空间，更进一步防止污染金手指12。在其它实施方式中，黏着剂50也可以采用其它适当的黏着剂。
因本发明的间隔垫层20与基板10通过电镀方式一体成型，从而在整个生产过程中不需额外制作和固定间隔垫层20，进而缩短了生产周期，降低了成本。
本发明的芯片封装结构100还包括封胶体60。封胶体60位于基板10上，用于将间隔垫层20、芯片30及所述焊线40封固于封胶体60中。在本实施方式中，封胶体60为黑胶。
图2是本发明另一种实施方式的芯片封装结构200的剖视示意图，芯片封装结构200的结构与芯片封装结构100的结构相同，并能完成相同的功能，实现相同的效果。芯片封装结构200与芯片封装结构100之区别在于：芯片封装结构200包括一个有台阶的间隔垫层220。间隔垫层220与基板210通过电镀方式一体成型，其包括第一垫层222和第二垫层224。第一垫层222的长度和宽度小于第二垫层224的长度和宽度，从而在第一垫层222和第二垫层224之间形成一个台阶226，同时第一垫层222的长度和宽度小于芯片230的长度和宽度。芯片230通过黏着剂250固定于间隔垫层220上，黏着剂250覆盖芯片230与所述第一垫片222相连的两表面及所述第一垫片222和所述第二垫片224之间的台阶226。在本实施方式中，第二垫层224的长度和宽度可以小于芯片230的长度和宽度也可以大于芯片230的长度和宽度。
图3是本发明芯片封装方法，用于将芯片30封装于基板10上，所述芯片30包括多个焊垫32，所述基板10包括多个金手指12。在步骤301，在基板10上以一体成型的方式生成间隔垫层20。在本实施方式中，间隔垫层20通过电镀方式生成，间隔垫层20的厚度大于所述金手指12的厚度。在步骤303，通过黏着剂50将芯片30固定于间隔垫层20上。在本实施方式中，所述间隔垫层20的长度和宽度小于芯片30的长度和宽度。在其它实施方式中，所述间隔垫层为台阶式，其长度和宽度小于芯片30的长度和宽度。在步骤305，通过焊线40电性连接所述金手指12和所述焊垫32。在步骤307，通过封胶体60将间隔垫层20、芯片30及所述焊线40封固于封胶体60中。在本实施方式中，芯片30为厚度小于或等于50微米的薄芯片。

Claims (10)

1.一种芯片封装结构，其特征在于，包括：
基板，包括多个金手指；
间隔垫层，与所述基板一体成型；
芯片，通过黏着剂固定于所述间隔垫层之上，所述芯片包括多个焊垫，所述间隔垫层的长度和宽度小于所述芯片的长度和宽度；及
多个焊线，用于电性连接所述金手指和所述焊垫。
2.如权利要求1所述的芯片封装结构，其特征在于，通过电镀方式与所述基板一体成型，且所述间隔垫层的厚度大于每一个金手指的厚度。
3.如权利要求1或2所述的芯片封装结构，其特征在于，所述间隔垫层包括第一垫层和第二垫层，所述第一垫层位于所述芯片和所述第二垫层之间，所述第一垫层和所述第二垫层之间形成一个台阶。
4.如权利要求3所述的芯片封装结构，其特征在于，所述第一垫层的长度和宽度小于所述第二垫层的长度和宽度，且小于所述芯片的长度和宽度。
5.如权利要求1所述的芯片封装结构，其特征在于，所述芯片的厚度小于或等于50微米。
6.一种芯片封装方法，用于将芯片封装于基板上，所述芯片包括多个焊垫，所述基板包括多个金手指，其特征在于，所述方法包括：
在基板上以电镀方式生成间隔垫层；
将所述芯片固定于所述间隔垫层上；
电性连接所述金手指和所述焊垫；及
封装所述芯片；
其中，所述间隔垫层的长度和宽度小于所述芯片的长度和宽度。
7.如权利要求6所述的芯片封装方法，其特征在于，所述间隔垫层的厚度大于每一个金手指的厚度。
8.如权利要求6或7所述的芯片封装方法，其特征在于，所述间隔垫层包括第一垫层和第二垫层，所述第一垫层位于所述芯片和所述第二垫层之间，所述第一垫层和所述第二垫层之间形成一台阶。
9.如权利要求8所述的芯片封装方法，其特征在于，所述第一垫层的长度和宽度小于所述第二垫层的长度和宽度，且小于所述芯片的长度和宽度。
10.如权利要求6所述的芯片封装方法，其特征在于，所述芯片的厚度小于或等于50微米。
CN200910106126A 2009-03-12 2009-03-12 芯片封装结构及方法 Pending CN101834162A (zh)

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CN102593079A (zh) * 2012-03-15 2012-07-18 南通富士通微电子股份有限公司 芯片封装结构及芯片封装方法
CN103700656A (zh) * 2012-09-27 2014-04-02 国碁电子(中山)有限公司 厚膜混合电路结构及制造方法

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US6198171B1 (en) * 1999-12-30 2001-03-06 Siliconware Precision Industries Co., Ltd. Thermally enhanced quad flat non-lead package of semiconductor
JP3895570B2 (ja) * 2000-12-28 2007-03-22 株式会社ルネサステクノロジ 半導体装置
JP2003204027A (ja) * 2002-01-09 2003-07-18 Matsushita Electric Ind Co Ltd リードフレーム及びその製造方法、樹脂封止型半導体装置及びその製造方法
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CN102593079A (zh) * 2012-03-15 2012-07-18 南通富士通微电子股份有限公司 芯片封装结构及芯片封装方法
CN103700656A (zh) * 2012-09-27 2014-04-02 国碁电子(中山)有限公司 厚膜混合电路结构及制造方法

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