CN101828274B - 用于半导体晶片与装置的具有阻挡层的镍锡接合体系 - Google Patents

用于半导体晶片与装置的具有阻挡层的镍锡接合体系 Download PDF

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CN101828274B
CN101828274B CN2008801119275A CN200880111927A CN101828274B CN 101828274 B CN101828274 B CN 101828274B CN 2008801119275 A CN2008801119275 A CN 2008801119275A CN 200880111927 A CN200880111927 A CN 200880111927A CN 101828274 B CN101828274 B CN 101828274B
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layer
emitting diode
tin
light emitting
nickel
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马修·德奥诺费奥
大卫·B·斯雷特
约翰·A·埃德蒙德
华双·孔
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Kerui Led Co
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Abstract

公开了一种发光二极管结构(37),其包括由外延层(21,22)形成的发光激活部和支承该激活部的载体基底(23)。以镍和锡为主的接合金属体系(27)将该激活部连接至该载体基底。至少一层钛粘附层(25,26)在该激活部与该载体基底之间,铂阻挡层(35,40)在该镍-锡接合体系与该钛粘附层之间。该铂层具有的厚度足以基本上防止该镍锡接合体系中的锡迁移至该钛粘附层中或迁移通过该钛粘附层。

Description

用于半导体晶片与装置的具有阻挡层的镍锡接合体系
技术领域
本发明涉及用于在发光二极管(LED)制造期间将带有LED的基底晶片固定至其它基底晶片的金属接合体系的结构和组成。
背景技术
发光二极管(LED)是一类通过促进在适当的半导体材料中的电子-空穴复合过程而将施加电压转换为光的光子半导体器件。而且,在复合过程中释放的一些或全部能量产生光子。
典型的LED包括形成通过其发生电流注入的p-n结以产生复合过程的p型和n型外延层(“外延层”)。这些外延层典型地在相同或不同的半导体基底上生长。由于能够以相对高的晶体品质生产外延层,因而提高所得器件的品质和工作。器件的基底部分可能不需要相同水平的品质,或者在一些情况下,由与一个或多个外延层相同的材料形成的基底是不容易获得的(或者根本不能获得)。
由于第III族氮化物材料的宽带隙和直接跃迁的特性,第III族氮化物材料有利于较短波长发光二极管;即,在电磁光谱的蓝色、紫色和紫外线区域中发射的那些。第III族氮化物材料能够结合其它颜色的二极管或者结合磷光体产生白光。同时,难以或者不可能获得适合尺寸和质量的第III族氮化物基底晶体。结果,基于第III族氮化物材料体系的LED典型地包括蓝宝石或碳化硅(SiC)基底上的第III族氮化物外延层。
出于许多原因,当该发光半导体材料的外延层在基底上形成(典型地通过化学气相沉积(“CVD”)生长)时,在一些情况下能够将该所得前体结构添加至另外的基底。第二基底可不同于半导体,或者如果其为半导体,出于半导电的目的第二基底不是必须存在。例如,在共同转让和共同未决的美国专利申请公开号20060060877中,出于安装和制造的目的使用第二基底,以形成最终LED结构的一部分。在此将公开号为20060060877的内容全部引入以作参考。作为在此处和别处提及的,一些类型的LED的制造包括降低原始基底厚度的一步或多步(例如,因为为了使开始制造步骤较容易,原始基底是较厚的)。相关的背景技术在共同转让的美国专利申请公开号20060049411、20060060872、20060060874和20060060879中提及。
在其它结构中,为了反转(倒装)其常规取向,将发光二极管安装至第二基底。换句话说,在典型的取向中,将基底安装至引线框,外延层形成LED的发射面。然而,在倒装芯片取向中,外延层朝向引线框安装,基底设置LED的光发射面。此类倒装芯片二极管制造工艺中的各步骤能够需要带有LED的基底晶片暂时地或永久地连接至另外的基底晶片。在一些倒装芯片的实施方案中,在将外延层安装至暂时或永久的基底晶片之后,从外延层中除去带有LED的基底晶片。
将带有LED的基底晶片(在此还称为“生长”晶片或基底)连接至另外的基底晶片(“载体”晶片或基底)的常规方式包括当期望永久接合时,以与焊接或钎焊相同或类似的方式使用各种金属层。在许多情形下,锡层(Ti)形成于或沉积于各个要连接的表面上,然后添加另外的接合金属(bonding metals)层,以在各第一和第二基底(有时称为给体与受体基底)上形成接合金属结构。
出于许多原因,金(Au)在这些接合金属层中已历史性地成为主要元素。因为其抗氧化和其它化学反应(这使其对于珠宝和相关物品理所当然地历史性具有价值),金还由于其耐蚀性即,避免不期望地的与其环境的反应而受到青睐。金形成相对低熔点的合金或化合物的能力(相对于纯金)还使其对于钎焊(soldering)目的是理想的。
然而,即使在单独的半导体器件中以少量使用时,当市场如今需求的数量超过数百万单独的发光二极管时,金的费用变得非常可观。
作为另一因素,相互焊接的晶片需要施加一些热。因此,用于将LED基底晶片连接至第二基底晶片的焊接步骤将LED加热至某种程度。作为本领域技术人员公知的,升高发光半导体外延层的温度增加相应地在外延层中产生缺陷的概率。典型地,金-锡类焊接(压焊(bonding)、钎焊)体系需要约300℃以上的温度。虽然例如第III族氮化物材料的外延层能够理论上耐受此类温度,但实际上这些温度显著地增加接合步骤产生显著的缺陷的概率。
还作为另外的因素,当将单独的LED与晶片分离并安装在引线框上(例如形成灯)时,将其典型地用另一焊接步骤而安装在引线框上。如果LED已包含焊料接合(solder bond),现有的焊料接合应当期望地保持不受将接合晶片的芯片焊接至引线框所需的温度的影响。因此,能够使LED焊接至引线框的温度将受到基底-基底接合的熔化温度的限制。换句话说,基底-基底接合的熔炼(metallurgy)的热特性可以不利地限定能够用于将单独的LED连接至单独的引线框的焊接类型。
因此,存在以下需要:利用改进特性的镍-锡接合体系,同时避免当从镍层迁移(migrates)锡以形成不期望物质例如游离锡、钛锡合金或者其它热不稳定性金属间化合物时引发的问题。
发明内容
一方面,本发明为包括由外延层形成的发光激活部和用于支承该激活部的载体基底的发光二极管结构。以镍和锡为主的接合金属体系将激活部连接至载体基底。至少一个钛粘附层(adhesion layer)在激活部与载体基底之间,铂阻挡层在镍锡接合体系与钛粘附层之间。该铂层具有足以基本上防止镍锡接合体系中的锡迁移至钛粘附层中或者迁移通过钛粘附层的厚度。
另一方面,本发明为包括由至少两个第III族氮化物的外延层形成的发光激活部和用于支承该激活部的载体基底的发光二极管前体结构。接合金属结构在激活部与载体基底之间。该接合金属结构包括在两个镍外层之间的锡中间层,其中锡的相对量大于通过与任一单一镍层反应消耗的量,但是小于提供超过两个镍层的功能性反应的锡的量。钛粘附层在激活部与接合金属结构之间,铂阻挡层在钛粘附层与接合金属结构之间,用于防止接合结构中的锡迁移至钛粘附层中或迁移通过钛粘附层。
再一方面,本发明为包括连接在一起的生长结构和载体结构的发光二极管用前体结构。该生长结构包括生长基底、在该生长基底上的发光外延层和在该外延层上用于连接至载体结构的金属接合体系。该生长结构金属接合体系主要由镍层和锡层形成,其中钛粘附层在该镍层与外延层之间,铂阻挡层在钛粘附层与镍层之间。该载体结构包括载体基底、在该载体基底上的钛粘附层、在该钛层上的铂阻挡层和在该铂层上用于连接至该生长结构的镍层。当将生长结构上的接合金属体系与载体结构上的镍层连接和加热时,各个铂阻挡层防止锡迁移至任一钛粘附层中或者迁移通过任一钛粘附层。
又一方面,本发明为在引线框上的发光二极管结构。在此方面,本发明包括由外延层形成的发光激活部、用于支承该激活部的载体基底和用焊料组合物固定至载体基底的引线框或等同结构。接合金属体系将激活部连接至载体基底,其中阻挡层在接合金属体系与外延层之间。该阻挡层由一材料形成并具有一定的厚度,以足以基本上阻止具有比焊料组合物的熔点更低的熔点的游离金属或合金的形成或迁移。
本发明的前述和其它目的与优点及其实现方式基于以下详细描述并结合附图将变得显而易见。
附图说明
图1为具有镍-锡接合体系的LED结构的横截面示意图。
图2-5为具有镍-锡接合体系的结构的横截面照片。
图6、7和8为用氩连续轰击之后获取的图5中所示表面的俄歇(Auger)谱。
图9和10为具有镍-锡接合体系的LED结构的照片。
图11-12为从图10的照片中所示表面获取的两个位置的EDS谱。
图13为根据本发明的结构的横截面照片。
图14为根据本发明的结构的横截面示意图。
图15为根据本发明结构的另一实施方案的横截面示意图。
图16为本发明的另一实施方案的横截面示意图。
具体实施方式
本发明为作为特别用于发光二极管某些结构的改进金属接合体系。
单独的LED器件的性质与工作在本领域是公知的,在此将不再赘述。适合的参考文献包括Sze,PHYSICS OFSEMICONDUCTOR DEVICES,第二版(1981);Schubert,LIGHT-EMITTING DIODES,Cambridge University Press(2003)和Zetterling,PROCESS TECHNOLOGY FOR SILICONCARBIDE DEVICES,Electronic Materials Information Service(2002)。
在‘158申请中提及的接合体系成功地指出当通够主要由镍(Ni)和锡(Sn)形成接合体系期间金占主要地位时引起大量问题。如其中所述,虽然锡的熔点相对低(232℃),但包括约30至70重量%之间的锡的由镍-锡化合物形成的合金具有都高于750℃的熔点。因此,在‘158申请中描述的该接合体系成功地满足耐受在将晶片相互接合后进行的制造步骤期间发生的在250-300℃范围内的热剧增(thermal excursions)的标准。
利用‘158申请中的镍-锡接合体系形成的器件已实现许多期望的目标。然而,随着其用途的增加,已发现锡不期望地迁移通过相邻的镍层。即使当锡与镍的比例量为预期全部锡以镍-锡合金的形式存在的比例量时,也趋于发生此迁移。已观察到几个产生的问题。首先,当迁移的锡到达典型存在的钛粘附层时,其能够形成在稍后制造步骤所需的温度下热不稳定的钛-锡化合物。此类化合物在稍后制造步骤期间能够以固态反应,当使用终端器件(end device)时,它们经受热老化。这些金属间化合物即使在实际上没有熔化的情况下也还能够引起分层(delamination)问题。其次,锡能够迁移和形成与钛粘附层相邻的游离锡部分。由于锡的232℃的熔点,该游离锡部分或热不稳定的合金在结构中造成具有更高的在制造温度步骤时分离趋势的位置。
理论上,增加在与锡层相邻的层中的镍量应当成功地阻止任意给定量的锡迁移通过镍层。然而,实际上即使当相邻镍层的厚度翻倍时锡也持续迁移。这表明锡在镍中具有适当高的迁移率,仅厚度可能不能解决问题。更重要的是,仅仅增加接合层(bonding layer)的厚度(由此增加引入该结合层的LED、灯和封装体的厚度)不能提供特殊结构或电子优点。虽然可能形成绝对阻止锡迁移的镍层,但是其相对厚度将产生相应缺点例如制造困难、尺寸和成本。
图1表示以20概括指示的此类发光二极管结构。该二极管20包括典型地由氮化镓或其它适合的第III族氮化物形成的各个外延层21和22。这些外延层隔着阻挡金属体系24、一对钛粘附层25和26以及镍锡接合体系27而由载体基底23支承。在示例性实施方案中,该载体基底选自由铝、铜硅和碳化硅组成的组,在许多实例中硅是普遍的。
应理解,此处的描述和图是示例性的而不是对能够从本发明受益的二极管结构的限定。因此,虽然LED能够具有与GaN的一p型和一n型层一样基本的结构,LED还能够由多个外延层形成,其中的一些可包括InGaN和通常包括AlGaN的缓冲层。发光结构能够包括p-n结、量子阱、多量子阱和超晶格结构。
还应理解,此处广义上使用的表示相对位置的结构术语例如“在...上”“在...上方”和“在...之间”为所列举的项目之间的关系而不是(例如)所列举的项目之间的直接接触。在说明书的任意指定部分,该含义在上下文中将都是清楚的。
图2为具有图1中示意性示出的基本结构的发光二极管的横截面的显微照片。相同元件用图1中的附图标记通用标记。因此,由符号(brackets)21、22表示氮化镓外延层,24表示阻挡金属、25和26表示钛层,27表示镍-锡接合体系和23表示硅基底。然而,图2还示出空隙区域30,所述空隙区域30的一些部分作为暗色阴影紧邻在阻挡层24下方出现,其它部分作为浅灰色表面在钛层25上方出现。如稍前所述,该空隙空间由当锡迁移并与钛层25和26反应或者锡形成游离锡或形成其它不期望地的热不稳定性金属间化合物时发生的分层而产生。
图3为与图2相同但具有强调由分层产生的空隙30的稍微不同取向的结构的另一视图。
图4为图3的局部放大图,其示出在阻挡金属层24正下方的剩余的钛层25。由分层产生的空隙空间作为暗色空间30再次可见。
图5至8确定由本发明解决的问题的本质。图5为沿由图2、3和4旋转约(但不精确)90度的取向上的结构的又一图。在标记为“2”的分层面部分上进行俄歇谱分析。在图5中,外延层21和22的分层部分出现在左下角,镍锡接合金属体系27的上部(top)对应于“2”指定的目标,硅基底指定为23。
在任意利用氩的溅射轰击之前获取图6的俄歇谱。其表明在动能值为380和416电子伏特(eV)处存在钛。
图7示出在金的参比溅射速率为约5埃/秒下氩溅射30秒之后源自相同目标区域的谱图。在约510eV处的主峰(large peak)表明存在源自当将分层部分暴露至大气时该层上形成的本征氧化物(native oxide)的氧。与图6相比,代表锡的峰在约423和435eV处变得明显,但是所预期的镍的峰(例如在约700eV处)完全不存在。此谱图证明表面上存在锡和钛(而不是镍和锡),其进一步表明镍既不作为合金保留锡也不防止锡迁移至钛层中或迁移通过钛层。
图8为轰击90秒之后获取的相同谱图,其中锡在426和432eV处的峰特性是明显的。图8再次示出不存在镍,从而证实图7的结果和问题的存在。
图9-12示出相同问题的不同方面,即存在大量的游离锡。在适合的情况下,结构相似的部分标有与稍前图示中相同的标记。图9是为了分析接合结构已除去外延层的结构的横截面视图。因此,再将金属阻挡层指定为24,镍-锡接合体系指定为27。再将由分层产生的空隙标记为30,硅载体基底标记为23。然而,图9还示出多个部分的游离锡31。图10为该接合层27的分层面的平面视图。
图11和12为证实指定为31的部分是锡的EDS谱。图11为从在图10中指定为“1”的块体获取的EDS谱。正如图11所示,该试样几乎全部是锡,不存在钛或镍。
当从标记为“3”的位置(即,非块状结构)获取相同的分析时,谱图表明存在金、锡和钛,但是再次表明几乎不存在镍或不存在镍。
图13为包括铂阻挡层的以34概括指示的根据本发明的LED结构的横截面显微照片(micrograph)。在适合的情况中,同样的元件标有与如稍前图示中相同的附图标记。因此,结构34包括两个氮化镓外延层21和22,尽管其在照片中作为单层出现。再将阻挡金属层指定为24,再将镍锡接合体系(包含少量金)指定为27。钛粘附层作为暗色线25和26出现在镍锡接合体系27的相对侧上。铂阻挡层作为亮色线35出现在镍锡接合体系27的上方。
在优选的实施方案中,选择镍和锡的量以确保全部锡将与镍反应。在最优选的实施方案中,镍锡和任意其它存在元素(例如金)的量为发生完全反应而几乎没有或没有剩留能够随着时间进行扩散、热老化或者任意其它不利的过程的量。
铂代表有利的阻挡金属,这是因为铂能够与任意到达铂-锡界面的锡形成金属间相。在这点上,已发现当阻挡层与锡反应时阻挡层是最有效的。因此,有效的阻挡层与锡反应而不仅仅阻挡锡扩散。这些铂-锡相在二极管进一步进行制造的温度范围内是稳定的,并在热老化期间趋于保持稳定。换句话说,铂层的存在防止低熔点化合物、其它热不稳定性金属间化合物的形成或者防止锡迁移至与镍界面相对的粘附界面。
熟知制造发光二极管的人员将认识到,在此描述的阻挡层和相关结构的特性与将二极管暴露于任意给定温度期间的正常和预期时间的情况有关。通常,将在此描述的该类型的二极管在200℃附近的温度下典型地经受至例如化学气相沉积等的步骤(以增加钝化层等)约一小时的时间。将各种退火工艺(例如为了获得或改进欧姆接触)在稍微升高的温度(例如约290℃)下进行约一小时时间。将利用回流工艺使二极管固定至引线框(“晶片固定(die attach)”)在更高温度(约315℃-350℃)下典型地进行较短时间例如5或10秒。典型的工作条件为小于50℃。已证实高温(100℃)工作寿命,超过1000小时而没有接合的劣化。
因此,应理解,在此描述的阻挡层和金属体系在至少需要进行这些制造工艺的时间内和典型地更长的时间内保持其期望的性能。
如图13的中心部分相对清晰的外观所示,铂阻挡层35防止镍-锡接合体系27中的锡迁移至钛层25或者通过钛层25。因此,图13为避免在(例如)图1和9中可见的该类型分层的示例性结构。
虽然钛粘附层经常存在于载体侧和接合金属体系的外延侧二者上,但是本发明即使在不存在钛时,即在使用本领域熟练技术人员已知的其它粘附层的结构中、或者在铂能够用作粘附层的结构中或者不包括粘附层的结构中,也提供它的优点。
图13还示出通过铂阻挡层35解决的问题。特别地,图13的用箭头标记为36的照片部分中,钛粘附层26趋于消失于镍-锡接合体系或者由于镍-锡接合体系27而模糊。这进一步表明,在不存在铂阻挡层时,镍锡接合体系27中的锡将迁移至钛层26或者通过钛层26(或者迁移至钛层26和迁移通过钛层26),形成低熔点钛-锡化合物、其它热不稳定金属间化合物或者游离锡。
图13还包括示出在约330℃的温度下发生铂层35的局部化相互作用的标记为38的区域。钛层25保持良好地限定于在该区域38的上方。当进一步加热图13的结构(例如加热至约350℃)时,观察到更多的该局部化相互作用。
在示例性实施方案中,铂与锡之间的局部化相互作用(例如图13中的区域38)在接近约330℃的接合温度下和在施加一定量量的力(典型地约6500牛顿下)下趋于变得更加显著。在较低温度例如约240摄氏度下,铂与锡之间的局部化相互作用是不明显的。因此,实用的接合温度范围从约锡的熔点(232℃)开始直至约350摄氏度,其中优选的范围介于约240℃至330℃之间。
阻挡层在金属接合体系的外延侧上或者在载体基底侧上或者在两者上提供结构的优点。因此,本发明包括全部三种可能性。作为到此为止的一般观察(非本发明限定),不含阻挡层的二极管趋于在外延侧上比在载体基底侧上更多地趋于分层。
图13还示出本发明具有在接合线的厚度方面的优点,因为阻挡层使越薄的接合线越实用。术语“接合线”在本领域通常是公知的,作为在此使用的是指金属接合体系27。在本发明中,接合线为典型地小于6微米(μm)厚,其中示例性实施方案中为小于3μm厚。薄的接合线提供几个优点,例如降低制造成本和降低在金属体系中的应力。相比之下,特别当应用于薄的(例如小于150μm)晶片中时,高的应力能够产生相对高程度的晶片翘曲(wafer bowing)。此类翘曲能够增加稍后制造与加工的难度。晶片翘曲还能够导致在例如对于卡盘(chuck)或光刻(photolithography)保持真空等的步骤期间在较厚晶片(例如约600μm)中的加工困难。当然,许多不同因素能够影响晶片应力,(例如接合温度、接合压力、沉积技术),但是本发明提供最小化接合线厚度因而最小化由过量的接合线厚度导致的任意应力的机会。
正如稍前指明的,铂阻挡层(图13中的35)阻止锡迁移越过阻挡层35。这使得通过铂阻挡层35而不是通过简单地增加存在于接合层27中的镍量(因此避免增加接合线的厚度)来限制锡。
图14为包括图13中所示的元件并还示出器件载体晶片侧上的第二铂阻挡层的以37概括指示的根据本发明的发光二极管的示意图。再将氮化镓层指定为21和22,将金属阻挡层指定为24,将基底指定为23。在镍-锡接合体系27的相对侧上的钛粘附层表示为25和26。
图14包括图13中所示的铂阻挡层35,并还包括在器件37的载体基底侧上的第二铂阻挡层40。
在本发明的示例性实施方案中,接合金属体系27为大于75%的镍和锡以及在一些情况下为大于85%的镍和锡的金属合金。如果存在,金是受限定的,其中在示例性实施方案中含有小于50重量%的金,和更典型地小于20重量%的金。
图15示出以42概括指示的前体生长结构和以43概括指示的载体结构的情况下的本发明。该生长结构42包括生长基底44,所述生长基底44在示例性实施方案中由碳化硅形成,因为其与第III族氮化物的晶格匹配比与其它基底材料例如蓝宝石的晶格匹配更好。该生长结构42包括第III族氮化物外延层45和46,所述第III族氮化物外延层45和46在示例性实施方案中由氮化镓形成,但是如稍前所指明,其能够包括InGaN,还能够包括更多的复合结构例如异质结、双异质结、量子阱、多量子阱和超晶格结构。
将典型存在的阻挡金属指定为48。
生长结构42包括在外延层45和46上的用于将生长结构42连接至载体结构43的金属接合体系。该生长结构金属接合体系主要由镍层47和锡层50与在该镍层50和外延层45和46之间的钛粘附层51、在该钛粘附层51和该镍层47之间的铂阻挡层52形成。
该载体结构43包括典型地选自由硅与碳化硅组成的组的载体基底53、在该载体基底53上的第二钛层54、在该第二钛粘附层54上的第二铂阻挡层55、在该第二铂层55上用于将载体结构43连接至生长结构42的第二镍层56。
当将生长结构42上的接合金属体系和载体结构43上的镍层连接并加热时,各个铂阻挡层52和55防止源自层50的锡迁移至任一钛粘附层51或54中或迁移通过任一钛粘附层51或54。
图15还示出,在该实施方案中,生长结构42和载体结构43能够各自包括用于改进当连接所述结构时的接合的金闪光层(flash layer)。生长结构42在锡层50上具有金闪光层57,载体结构43在第二镍层56上具有金闪光层60。
在示例性实施方案中,生长结构42中锡层50的厚度为生长结构42中镍层47厚度的约5至10倍之间。
在说明性的而非要求保护的本发明限定的示例性实施方案中,生长结构42上的层具有以下厚度:钛粘附层51为约100纳米,铂阻挡层52为约150纳米,镍层47为约200纳米,锡层50为2微米厚和金闪光层57为30纳米。
在对应的载体结构43上,钛粘附层54为100纳米,铂阻挡层55为1500埃,镍层56为300纳米和金闪光层60为5纳米。
在另一实施方案(未示出)中,约100纳米的金附加层位于生长结构42上,在2微米锡层与200纳米镍层之间。
在其它实施方案中,在生长结构42或载体结构43中的镍量能够依赖于期望的最终结构与组成而增加至300或400纳米。
当将图15中示出的各个结构42和43在适度压力下放置在一起时将其加热从而形成接合结构。其后依赖于设计的选择能够将生长基底44薄化或将其除去。
图16示出在引线框的情况下的本发明。如在一些其它附图中,前面参考的元件标有与其在其它附图中相同的附图标记。
因此,图16示出以60概括指示的发光二极管结构。该结构60包括由外延层21和22形成的发光部。载体基底23支承外延层21和22。将载体基底用焊料组合物62固定至引线框61。应理解,示意性和以代表性形式示出该引线框和焊料组合物,将发光二极管以相同或类似的方式固定至其它装置和其它类似及等同的结构均落入本发明的范围内。
接合金属体系27将外延层21和22连接至载体基底23。阻挡层63位于接合金属体系27与外延层21、22之间。阻挡层63由一材料形成并具有一定的厚度,以足以基本上阻止具有比焊料组合物62的熔点更低熔点或证实在此类温度下热不稳定性的游离金属或合金形成或迁移。
如关于前面实施方案所述,当金属接合体系27以镍和锡为主时,铂作为示例性阻挡层。还如关于其它实施方案所述,二极管结构60还典型地包括在金属接合体系27与外延层21、22之间的粘附层25,其中铂阻挡层63位于粘附层25与镍-锡接合体系27之间。如在其它示例性实施方案中,由于钛对于该目的有利性能,该粘附层包括钛。
图16还示出通常(但不必要)用于该结构的阻挡金属体系24连同与载体基底23直接相邻的第二钛粘附层26以及在接合金属体系27与第二粘附层26之间的另一铂阻挡层64一起用于该结构,所述铂阻挡层64同样地防止具有低熔点的游离的金属或合金(特别是锡)或者其它热不稳定性金属间化合物的形成或者迁移至载体基底上的钛粘附层26中或迁移通过载体基底上的钛粘附层26。然而,如稍前所指明,如果阻挡层也提供令人满意的粘合性,就可省略特定的钛粘附层。
在附图和说明书中已提及本发明的优选实施方案,虽然已采用特定的术语,但它们仅仅是以一般性和描述性的意义使用,并不是出于限制在权利要求中限定的本发明的范围的目的。

Claims (26)

1.一种发光二极管结构,其包括:
由外延层形成的发光激活部;
用于支承所述发光激活部的载体基底;
以镍和锡为主的接合金属体系,其将所述发光激活部连接至所述载体基底,其中所述接合金属体系以小于50重量%的量包含金;和
至少一个与所述接合金属体系相邻的阻挡层,所述阻挡层包含足以基本上防止所述接合金属体系中的锡迁移通过所述阻挡层的厚度的铂。
2.根据权利要求1所述的发光二极管结构,其中所述阻挡层能够形成在240℃至350℃之间的温度范围内是热稳定的与锡的金属间化合物。
3.根据权利要求1所述的发光二极管结构,其进一步包括至少一个在所述发光激活部与所述阻挡层之间的钛粘附层。
4.根据权利要求3所述的发光二极管结构,其中所述钛粘附层包括钛。
5.根据权利要求1所述的发光二极管结构,其中所述接合金属体系包括大于85重量%的镍和锡的金属合金。
6.根据权利要求1所述的发光二极管结构,其中所述接合金属体系为以小于20重量%的量包含金的金属合金。
7.根据权利要求1所述的发光二极管结构,其中所述发光激活部由第III族氮化物材料体系形成。
8.根据权利要求4所述的发光二极管结构,其进一步包括:
在所述接合金属体系与所述载体基底之间的第二钛粘附层;和
在所述钛粘附层与所述接合金属体系之间的第二铂阻挡层。
9.根据权利要求4所述的发光二极管结构,其中:
所述发光激活部由至少两个第III族氮化物的外延层形成;
在所述发光激活部与所述载体基底之间的所述接合金属体系包括在两个镍外层之间的锡中间层,其中锡的相对量大于通过与任一单一镍层反应消耗的量,但是小于提供超过两个镍层的功能性反应的锡的量。
10.根据权利要求1或权利要求9所述的发光二极管结构,其中所述外延层包括氮化镓。
11.根据权利要求1或权利要求9所述的发光二极管结构,其中所述载体基底选自由铝、铜、硅和碳化硅组成的组。
12.根据权利要求9所述的发光二极管结构,其中所述锡层的厚度在任一所述镍层厚度的5至10倍之间。
13.根据权利要求9所述的发光二极管结构,所述发光二极管结构进一步包括在所述载体基底与所述接合金属体系之间的第二钛层。
14.根据权利要求13所述的发光二极管结构,其进一步包括在所述第二钛层与所述接合金属体系之间的第二铂层。
15.根据权利要求1或权利要求9所述的发光二极管结构,其中所述接合金属体系为小于6微米厚。
16.根据权利要求1或权利要求9所述的发光二极管结构,其中所述接合金属体系为小于3微米厚。
17.一种发光二极管用前体结构,所述前体结构包括:
连接在一起的生长结构和载体结构;
所述生长结构包括生长基底、在所述生长基底上的发光外延层和在所述发光外延层上用于连接至所述载体结构的接合金属体系;
所述生长结构的接合金属体系主要由镍层和锡层形成,其中钛粘附层在所述镍层与所述发光外延层之间和铂阻挡层在所述钛粘附层与所述镍层之间;和
所述载体结构包括载体基底、在所述载体基底上的第二钛粘附层、在所述第二钛层上的第二铂阻挡层和在所述第二铂阻挡层上用于连接至所述生长结构的镍层;
以致当将在所述生长结构上的所述接合金属体系与在所述载体结构上的所述镍层连接并加热时,所述各个铂阻挡层防止锡迁移至任一所述钛粘附层中或者迁移通过任一所述钛粘附层。
18.根据权利要求17所述的发光二极管用前体结构,其中所述生长基底选自由碳化硅和蓝宝石组成的组,所述发光外延层包括第III族氮化物,所述载体基底选自由硅和碳化硅组成的组。
19.根据权利要求18所述的发光二极管用前体结构,其中所述发光外延层包括氮化镓,所述载体基底包括硅。
20.根据权利要求17所述的发光二极管用前体结构,其进一步包括:
在所述生长结构的接合金属体系的镍-锡部分上的金闪光层和
在所述载体结构上的所述镍层上的金闪光层,用于在各个金闪光层处连接所述生长结构和所述载体结构。
21.根据权利要求17所述的发光二极管用前体结构,其中在所述生长结构中的所述锡层的厚度为在所述生长结构中的所述镍层厚度的5至10倍之间。
22.根据权利要求1所述的发光二极管结构,其进一步包括用焊料组合物固定至所述载体基底的引线框。
23.根据权利要求22所述的发光二极管结构,所述发光二极管结构进一步包括在所述接合金属体系与所述发光激活部之间的粘附层,其中所述阻挡层在所述粘附层与所述接合金属体系之间。
24.根据权利要求23所述的发光二极管结构,其中所述粘附层包括钛。
25.根据权利要求22所述的发光二极管结构,其中所述接合金属体系为小于6微米厚。
26.根据权利要求22所述的发光二极管结构,其中所述接合金属体系为小于3微米厚。
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Families Citing this family (111)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7410945B2 (en) * 2002-10-16 2008-08-12 The University Of Queensland Treatment of inflammatory bowel disease
US8698184B2 (en) 2011-01-21 2014-04-15 Cree, Inc. Light emitting diodes with low junction temperature and solid state backlight components including light emitting diodes with low junction temperature
US9443903B2 (en) * 2006-06-30 2016-09-13 Cree, Inc. Low temperature high strength metal stack for die attachment
JP5426081B2 (ja) * 2007-06-20 2014-02-26 スタンレー電気株式会社 基板接合方法及び半導体装置
US8664747B2 (en) * 2008-04-28 2014-03-04 Toshiba Techno Center Inc. Trenched substrate for crystal growth and wafer bonding
JP2010186829A (ja) * 2009-02-10 2010-08-26 Toshiba Corp 発光素子の製造方法
KR100974776B1 (ko) * 2009-02-10 2010-08-06 엘지이노텍 주식회사 발광 소자
US8207547B2 (en) 2009-06-10 2012-06-26 Brudgelux, Inc. Thin-film LED with P and N contacts electrically isolated from the substrate
TWI405409B (zh) * 2009-08-27 2013-08-11 Novatek Microelectronics Corp 低電壓差動訊號輸出級
US8525221B2 (en) 2009-11-25 2013-09-03 Toshiba Techno Center, Inc. LED with improved injection efficiency
TWI401825B (zh) * 2009-11-27 2013-07-11 Ind Tech Res Inst 發光二極體晶片的固晶方法及固晶完成之發光二極體
CN102104090B (zh) * 2009-12-22 2014-03-19 财团法人工业技术研究院 发光二极管芯片固晶方法、固晶的发光二极管及芯片结构
US8492242B2 (en) * 2010-05-25 2013-07-23 Micron Technology, Inc. Dry flux bonding device and method
TWI446577B (zh) * 2010-12-23 2014-07-21 Ind Tech Res Inst Led晶圓之接合方法、led晶粒之製造方法及led晶圓與基體之接合結構
US8803001B2 (en) 2011-06-21 2014-08-12 Toyota Motor Engineering & Manufacturing North America, Inc. Bonding area design for transient liquid phase bonding process
US8395165B2 (en) 2011-07-08 2013-03-12 Bridelux, Inc. Laterally contacted blue LED with superlattice current spreading layer
US20130026480A1 (en) 2011-07-25 2013-01-31 Bridgelux, Inc. Nucleation of Aluminum Nitride on a Silicon Substrate Using an Ammonia Preflow
US8916906B2 (en) 2011-07-29 2014-12-23 Kabushiki Kaisha Toshiba Boron-containing buffer layer for growing gallium nitride on silicon
US9142743B2 (en) 2011-08-02 2015-09-22 Kabushiki Kaisha Toshiba High temperature gold-free wafer bonding for light emitting diodes
US9012939B2 (en) 2011-08-02 2015-04-21 Kabushiki Kaisha Toshiba N-type gallium-nitride layer having multiple conductive intervening layers
US8865565B2 (en) 2011-08-02 2014-10-21 Kabushiki Kaisha Toshiba LED having a low defect N-type layer that has grown on a silicon substrate
US9343641B2 (en) 2011-08-02 2016-05-17 Manutius Ip, Inc. Non-reactive barrier metal for eutectic bonding process
US20130032810A1 (en) 2011-08-03 2013-02-07 Bridgelux, Inc. Led on silicon substrate using zinc-sulfide as buffer layer
US8564010B2 (en) 2011-08-04 2013-10-22 Toshiba Techno Center Inc. Distributed current blocking structures for light emitting diodes
US8624482B2 (en) 2011-09-01 2014-01-07 Toshiba Techno Center Inc. Distributed bragg reflector for reflecting light of multiple wavelengths from an LED
US8669585B1 (en) 2011-09-03 2014-03-11 Toshiba Techno Center Inc. LED that has bounding silicon-doped regions on either side of a strain release layer
US8558247B2 (en) 2011-09-06 2013-10-15 Toshiba Techno Center Inc. GaN LEDs with improved area and method for making the same
US8686430B2 (en) 2011-09-07 2014-04-01 Toshiba Techno Center Inc. Buffer layer for GaN-on-Si LED
US8853668B2 (en) 2011-09-29 2014-10-07 Kabushiki Kaisha Toshiba Light emitting regions for use with light emitting devices
US8664679B2 (en) 2011-09-29 2014-03-04 Toshiba Techno Center Inc. Light emitting devices having light coupling layers with recessed electrodes
US8698163B2 (en) 2011-09-29 2014-04-15 Toshiba Techno Center Inc. P-type doping layers for use with light emitting devices
US20130082274A1 (en) 2011-09-29 2013-04-04 Bridgelux, Inc. Light emitting devices having dislocation density maintaining buffer layers
US9178114B2 (en) 2011-09-29 2015-11-03 Manutius Ip, Inc. P-type doping layers for use with light emitting devices
US9012921B2 (en) 2011-09-29 2015-04-21 Kabushiki Kaisha Toshiba Light emitting devices having light coupling layers
US8581267B2 (en) 2011-11-09 2013-11-12 Toshiba Techno Center Inc. Series connected segmented LED
US8552465B2 (en) 2011-11-09 2013-10-08 Toshiba Techno Center Inc. Method for reducing stress in epitaxial growth
US9620478B2 (en) 2011-11-18 2017-04-11 Apple Inc. Method of fabricating a micro device transfer head
US8518204B2 (en) 2011-11-18 2013-08-27 LuxVue Technology Corporation Method of fabricating and transferring a micro device and an array of micro devices utilizing an intermediate electrically conductive bonding layer
US8573469B2 (en) 2011-11-18 2013-11-05 LuxVue Technology Corporation Method of forming a micro LED structure and array of micro LED structures with an electrically insulating layer
US8794501B2 (en) 2011-11-18 2014-08-05 LuxVue Technology Corporation Method of transferring a light emitting diode
US8349116B1 (en) 2011-11-18 2013-01-08 LuxVue Technology Corporation Micro device transfer head heater assembly and method of transferring a micro device
WO2013116086A1 (en) * 2012-01-30 2013-08-08 Cree, Inc. Low temperature high strength metal stack for die attachment
US9773750B2 (en) 2012-02-09 2017-09-26 Apple Inc. Method of transferring and bonding an array of micro devices
WO2013126458A1 (en) * 2012-02-24 2013-08-29 Skyworks Solutions, Inc. Improved structures, devices and methods releated to copper interconnects for compound semiconductors
US9044822B2 (en) 2012-04-17 2015-06-02 Toyota Motor Engineering & Manufacturing North America, Inc. Transient liquid phase bonding process for double sided power modules
US10058951B2 (en) 2012-04-17 2018-08-28 Toyota Motor Engineering & Manufacturing North America, Inc. Alloy formation control of transient liquid phase bonding
US9548332B2 (en) 2012-04-27 2017-01-17 Apple Inc. Method of forming a micro LED device with self-aligned metallization stack
US9105492B2 (en) 2012-05-08 2015-08-11 LuxVue Technology Corporation Compliant micro device transfer head
US8415771B1 (en) 2012-05-25 2013-04-09 LuxVue Technology Corporation Micro device transfer head with silicon electrode
US9034754B2 (en) 2012-05-25 2015-05-19 LuxVue Technology Corporation Method of forming a micro device transfer head with silicon electrode
US8415768B1 (en) 2012-07-06 2013-04-09 LuxVue Technology Corporation Compliant monopolar micro device transfer head with silicon electrode
US8383506B1 (en) 2012-07-06 2013-02-26 LuxVue Technology Corporation Method of forming a compliant monopolar micro device transfer head with silicon electrode
US8569115B1 (en) 2012-07-06 2013-10-29 LuxVue Technology Corporation Method of forming a compliant bipolar micro device transfer head with silicon electrodes
US8415767B1 (en) 2012-07-06 2013-04-09 LuxVue Technology Corporation Compliant bipolar micro device transfer head with silicon electrodes
US8933433B2 (en) 2012-07-30 2015-01-13 LuxVue Technology Corporation Method and structure for receiving a micro device
US10165835B2 (en) 2012-08-20 2019-01-01 Forever Mount, LLC Brazed joint for attachment of gemstones to each other and/or a metallic mount
US8791530B2 (en) 2012-09-06 2014-07-29 LuxVue Technology Corporation Compliant micro device transfer head with integrated electrode leads
US9162880B2 (en) 2012-09-07 2015-10-20 LuxVue Technology Corporation Mass transfer tool
US8835940B2 (en) 2012-09-24 2014-09-16 LuxVue Technology Corporation Micro device stabilization post
US8941215B2 (en) 2012-09-24 2015-01-27 LuxVue Technology Corporation Micro device stabilization post
US9558721B2 (en) 2012-10-15 2017-01-31 Apple Inc. Content-based adaptive refresh schemes for low-power displays
US9255001B2 (en) 2012-12-10 2016-02-09 LuxVue Technology Corporation Micro device transfer head array with metal electrodes
US9178123B2 (en) 2012-12-10 2015-11-03 LuxVue Technology Corporation Light emitting device reflective bank structure
US9159700B2 (en) 2012-12-10 2015-10-13 LuxVue Technology Corporation Active matrix emissive micro LED display
US9236815B2 (en) 2012-12-10 2016-01-12 LuxVue Technology Corporation Compliant micro device transfer head array with metal electrodes
US9029880B2 (en) 2012-12-10 2015-05-12 LuxVue Technology Corporation Active matrix display panel with ground tie lines
US9105714B2 (en) 2012-12-11 2015-08-11 LuxVue Technology Corporation Stabilization structure including sacrificial release layer and staging bollards
US9166114B2 (en) 2012-12-11 2015-10-20 LuxVue Technology Corporation Stabilization structure including sacrificial release layer and staging cavity
US9314930B2 (en) 2012-12-14 2016-04-19 LuxVue Technology Corporation Micro pick up array with integrated pivot mount
US9391042B2 (en) 2012-12-14 2016-07-12 Apple Inc. Micro device transfer system with pivot mount
US9153171B2 (en) 2012-12-17 2015-10-06 LuxVue Technology Corporation Smart pixel lighting and display microcontroller
US9308649B2 (en) 2013-02-25 2016-04-12 LuxVue Techonology Corporation Mass transfer tool manipulator assembly
US9095980B2 (en) 2013-02-25 2015-08-04 LuxVue Technology Corporation Micro pick up array mount with integrated displacement sensor
US9252375B2 (en) 2013-03-15 2016-02-02 LuxVue Technology Corporation Method of fabricating a light emitting diode display with integrated defect detection test
US9676047B2 (en) 2013-03-15 2017-06-13 Samsung Electronics Co., Ltd. Method of forming metal bonding layer and method of manufacturing semiconductor light emitting device using the same
KR102061565B1 (ko) * 2014-03-13 2020-01-02 삼성전자주식회사 금속 접합층 형성방법 및 그를 이용한 반도체 발광소자 제조방법
US8791474B1 (en) 2013-03-15 2014-07-29 LuxVue Technology Corporation Light emitting diode display with redundancy scheme
US9484504B2 (en) 2013-05-14 2016-11-01 Apple Inc. Micro LED with wavelength conversion layer
US9217541B2 (en) 2013-05-14 2015-12-22 LuxVue Technology Corporation Stabilization structure including shear release posts
US9136161B2 (en) 2013-06-04 2015-09-15 LuxVue Technology Corporation Micro pick up array with compliant contact
ES2952036T3 (es) 2013-06-12 2023-10-26 Rohinni Inc Teclado de retroiluminación con fuentes generadoras de luz depositadas
US8987765B2 (en) 2013-06-17 2015-03-24 LuxVue Technology Corporation Reflective bank structure and method for integrating a light emitting device
US9111464B2 (en) 2013-06-18 2015-08-18 LuxVue Technology Corporation LED display with wavelength conversion layer
US8928021B1 (en) 2013-06-18 2015-01-06 LuxVue Technology Corporation LED light pipe
US9035279B2 (en) 2013-07-08 2015-05-19 LuxVue Technology Corporation Micro device with stabilization post
US9296111B2 (en) 2013-07-22 2016-03-29 LuxVue Technology Corporation Micro pick up array alignment encoder
US9087764B2 (en) 2013-07-26 2015-07-21 LuxVue Technology Corporation Adhesive wafer bonding with controlled thickness variation
US9153548B2 (en) 2013-09-16 2015-10-06 Lux Vue Technology Corporation Adhesive wafer bonding with sacrificial spacers for controlled thickness variation
US9367094B2 (en) 2013-12-17 2016-06-14 Apple Inc. Display module and system applications
US9768345B2 (en) 2013-12-20 2017-09-19 Apple Inc. LED with current injection confinement trench
US9450147B2 (en) 2013-12-27 2016-09-20 Apple Inc. LED with internally confined current injection area
US9583466B2 (en) 2013-12-27 2017-02-28 Apple Inc. Etch removal of current distribution layer for LED current confinement
US9542638B2 (en) 2014-02-18 2017-01-10 Apple Inc. RFID tag and micro chip integration design
US9583533B2 (en) 2014-03-13 2017-02-28 Apple Inc. LED device with embedded nanowire LEDs
US9522468B2 (en) 2014-05-08 2016-12-20 Apple Inc. Mass transfer tool manipulator assembly with remote center of compliance
US9318475B2 (en) 2014-05-15 2016-04-19 LuxVue Technology Corporation Flexible display and method of formation with sacrificial release layer
US9741286B2 (en) 2014-06-03 2017-08-22 Apple Inc. Interactive display panel with emitting and sensing diodes
US9624100B2 (en) 2014-06-12 2017-04-18 Apple Inc. Micro pick up array pivot mount with integrated strain sensing elements
US9570002B2 (en) 2014-06-17 2017-02-14 Apple Inc. Interactive display panel with IR diodes
US9425151B2 (en) 2014-06-17 2016-08-23 Apple Inc. Compliant electrostatic transfer head with spring support layer
KR102311677B1 (ko) * 2014-08-13 2021-10-12 삼성전자주식회사 반도체소자 및 그 제조방법
US9705432B2 (en) 2014-09-30 2017-07-11 Apple Inc. Micro pick up array pivot mount design for strain amplification
US9828244B2 (en) 2014-09-30 2017-11-28 Apple Inc. Compliant electrostatic transfer head with defined cavity
US9478583B2 (en) 2014-12-08 2016-10-25 Apple Inc. Wearable display having an array of LEDs on a conformable silicon substrate
DE102015120773A1 (de) * 2015-11-30 2017-06-01 Osram Opto Semiconductors Gmbh Bauelement und Verfahren zur Herstellung eines Bauelements
WO2017124109A1 (en) 2016-01-15 2017-07-20 Rohinni, LLC Apparatus and method of backlighting through a cover on the apparatus
CN106057692B (zh) * 2016-05-26 2018-08-21 河南工业大学 一种三维集成电路堆栈集成方法及三维集成电路
DE112016006934B4 (de) * 2016-07-04 2020-01-23 Mitsubishi Electric Corporation Halbleitereinheit und Verfahren zur Herstellung derselben
WO2021014904A1 (ja) * 2019-07-25 2021-01-28 株式会社大真空 発光装置のリッド材、リッド材の製造方法および発光装置
KR102591964B1 (ko) * 2021-06-21 2023-10-23 주식회사 코닉에스티 접합 금속 적층체, 금속 접합용 적층 구조체 및 금속 접합 방법
KR102591963B1 (ko) * 2021-06-21 2023-10-23 주식회사 코닉에스티 금속 접합용 적층 구조체 및 금속 접합 방법

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5234153A (en) * 1992-08-28 1993-08-10 At&T Bell Laboratories Permanent metallic bonding method
US7023089B1 (en) * 2004-03-31 2006-04-04 Intel Corporation Low temperature packaging apparatus and method
TW200631200A (en) * 2005-02-23 2006-09-01 Cree Inc Substrate removal process for high light extraction LEDs
JP2007158133A (ja) * 2005-12-06 2007-06-21 Toyoda Gosei Co Ltd Iii族窒化物系化合物半導体素子の製造方法

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB234648A (en) 1924-06-19 1925-06-04 American Mach & Foundry Improvements in or relating to the treatment of lead and other metals
US3648357A (en) 1969-07-31 1972-03-14 Gen Dynamics Corp Method for sealing microelectronic device packages
US4418857A (en) 1980-12-31 1983-12-06 International Business Machines Corp. High melting point process for Au:Sn:80:20 brazing alloy for chip carriers
US5197654A (en) 1991-11-15 1993-03-30 Avishay Katz Bonding method using solder composed of multiple alternating gold and tin layers
JP3271475B2 (ja) 1994-08-01 2002-04-02 株式会社デンソー 電気素子の接合材料および接合方法
US6082610A (en) 1997-06-23 2000-07-04 Ford Motor Company Method of forming interconnections on electronic modules
US6342442B1 (en) * 1998-11-20 2002-01-29 Agere Systems Guardian Corp. Kinetically controlled solder bonding
US6320206B1 (en) 1999-02-05 2001-11-20 Lumileds Lighting, U.S., Llc Light emitting devices having wafer bonded aluminum gallium indium nitride structures and mirror stacks
US6222207B1 (en) 1999-05-24 2001-04-24 Lumileds Lighting, U.S. Llc Diffusion barrier for increased mirror reflectivity in reflective solderable contacts on high power LED chip
US20020068373A1 (en) 2000-02-16 2002-06-06 Nova Crystals, Inc. Method for fabricating light emitting diodes
US6335263B1 (en) 2000-03-22 2002-01-01 The Regents Of The University Of California Method of forming a low temperature metal bond for use in the transfer of bulk and thin film materials
JP2001176999A (ja) 2000-11-27 2001-06-29 Tanaka Kikinzoku Kogyo Kk 電子部品の気密封止方法
JP3388410B2 (ja) 2000-12-12 2003-03-24 鈴鹿工業高等専門学校長 すず−ニッケル合金膜の製造方法
CN1269612C (zh) 2000-12-21 2006-08-16 株式会社日立制作所 焊锡箔、半导体器件、电子器件、半导体组件及功率组件
US6787435B2 (en) * 2001-07-05 2004-09-07 Gelcore Llc GaN LED with solderable backside metal
US6740906B2 (en) * 2001-07-23 2004-05-25 Cree, Inc. Light emitting diodes including modifications for submount bonding
US6744142B2 (en) 2002-06-19 2004-06-01 National Central University Flip chip interconnection structure and process of making the same
KR101030068B1 (ko) 2002-07-08 2011-04-19 니치아 카가쿠 고교 가부시키가이샤 질화물 반도체 소자의 제조방법 및 질화물 반도체 소자
US7168608B2 (en) 2002-12-24 2007-01-30 Avago Technologies General Ip (Singapore) Pte. Ltd. System and method for hermetic seal formation
US6786390B2 (en) * 2003-02-04 2004-09-07 United Epitaxy Company Ltd. LED stack manufacturing method and its structure thereof
US7247514B2 (en) * 2003-04-11 2007-07-24 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for producing the same
TWI230450B (en) 2003-06-30 2005-04-01 Advanced Semiconductor Eng Under bump metallurgy structure
JP2005117020A (ja) * 2003-09-16 2005-04-28 Stanley Electric Co Ltd 窒化ガリウム系化合物半導体素子とその製造方法
KR101025844B1 (ko) * 2003-10-01 2011-03-30 삼성전자주식회사 SnAgAu 솔더범프, 이의 제조 방법 및 이 방법을이용한 발광소자 본딩 방법
US7332365B2 (en) 2004-05-18 2008-02-19 Cree, Inc. Method for fabricating group-III nitride devices and devices fabricated using method
US8174037B2 (en) 2004-09-22 2012-05-08 Cree, Inc. High efficiency group III nitride LED with lenticular surface
US8513686B2 (en) 2004-09-22 2013-08-20 Cree, Inc. High output small area group III nitride LEDs
US7259402B2 (en) 2004-09-22 2007-08-21 Cree, Inc. High efficiency group III nitride-silicon carbide light emitting diode
US7737459B2 (en) 2004-09-22 2010-06-15 Cree, Inc. High output group III nitride light emitting diodes
TWI257714B (en) * 2004-10-20 2006-07-01 Arima Optoelectronics Corp Light-emitting device using multilayer composite metal plated layer as flip-chip electrode
JP4906256B2 (ja) * 2004-11-10 2012-03-28 株式会社沖データ 半導体複合装置の製造方法
US7692207B2 (en) 2005-01-21 2010-04-06 Luminus Devices, Inc. Packaging designs for LEDs
JP4891556B2 (ja) 2005-03-24 2012-03-07 株式会社東芝 半導体装置の製造方法
TWI285969B (en) * 2005-06-22 2007-08-21 Epistar Corp Light emitting diode and method of the same
US8643195B2 (en) 2006-06-30 2014-02-04 Cree, Inc. Nickel tin bonding system for semiconductor wafers and devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5234153A (en) * 1992-08-28 1993-08-10 At&T Bell Laboratories Permanent metallic bonding method
US7023089B1 (en) * 2004-03-31 2006-04-04 Intel Corporation Low temperature packaging apparatus and method
TW200631200A (en) * 2005-02-23 2006-09-01 Cree Inc Substrate removal process for high light extraction LEDs
JP2007158133A (ja) * 2005-12-06 2007-06-21 Toyoda Gosei Co Ltd Iii族窒化物系化合物半導体素子の製造方法

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