CN101740553A - 3dic叠层中的冷却通道 - Google Patents

3dic叠层中的冷却通道 Download PDF

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CN101740553A
CN101740553A CN200910222543A CN200910222543A CN101740553A CN 101740553 A CN101740553 A CN 101740553A CN 200910222543 A CN200910222543 A CN 200910222543A CN 200910222543 A CN200910222543 A CN 200910222543A CN 101740553 A CN101740553 A CN 101740553A
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semiconductor substrate
tube core
dielectric layer
integrated circuit
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CN101740553B (zh
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卿恺明
萧景文
王宗鼎
曾明鸿
陈承先
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种包括3DIC叠层中的冷却通道的集成电路结构，该管芯包括：半导体衬底；第一介电层，在半导体衬底之上；互连结构，包括介电层中的金属线和通孔；多个通道，从半导体衬底内部延伸到介电层内部；以及介电膜，在互连结构之上并密封多个通道的一部分。多个通道被配置为使液体流过其中。

Description

3DIC叠层中的冷却通道
相关申请的交叉参考
本申请要求于2008年11月13日临时提交的标题为“Cooling Structuresand TSV Structures for 3D IC Stacking”的美国专利申请第61/114,367号申请，其申请结合于此作为参考。
技术领域
本公开总的来说涉及集成电路器件，更具体地，涉及半导体管芯和封装件及其形成方法。
背景技术
自从发明了集成电路，半导体工业就由于各种电子部件(即，晶体管、二极管、电阻器、电容器等)的集成密度的持续改进而经历了连续的快速增长。通常，集成密度的这种改进由最小特征尺寸的反复减小而造成，从而使得更多部件被集成到给定的芯片区域中。这些集成改进本质上基本是二维(2D)的，这是因为被集成部件占据的体积基本上都在半导体晶片的表面上。尽管光刻法的显著改进导致了2D集成电路形成的显著改进，但是对可以二维实现的密度存在物理限制。这些限制中的一种限制是制造这些部件所需要的最小尺寸。此外，当将多个器件放在一个芯片上时，需要更加复杂的设计。
为了解决上述问题，通常使用三维集成电路(3DIC)和叠层管芯。管芯被堆叠，并且叠层管芯中的集成电路通过硅穿孔(TSV，through-siliconvia)来互连或布线。
众所周知，叠层管芯的问题是热耗散。例如，当顶部管芯被堆叠在底部管芯上时，散热器可安装在顶部管芯上。因此，顶部管芯可具有良好的热耗散性能。然而，在底部管芯中产生的热量必须在其可到达散热器之前穿过顶部管芯，因此，底部管芯会遭受热耗散问题。当底部管芯产生大量热量时，例如，当底部管芯是诸如中央计算单元(CPU)的计算管芯时，该问题就可能变得更加严重。
发明内容
根据一个方面，集成电路结构包括管芯，该管芯包括：半导体衬底、在半导体衬底上方的第一介电层、包括介电层中的金属线和通孔的互连结构、从半导体衬底内部延伸至介电层内部的多个通道以及在互连结构上方并密封多个通道的一部分的介电膜。多个通道被配置为允许液体流过其中。
还公开了其他实施例。
附图说明
为了更加全面理解这些实施例及其优点，现在将结合附图进行以下描述，其中：
图1至图18是制造第一晶片/管芯中的通道的中间阶段的截面图；
图19至图23示出了制造第二晶片/管芯中的通道的中间阶段的截面图；
图24至图26示出了将第一晶片/管芯与第二晶片/管芯的堆叠、流体管(fluidic tube)的安装以及冷却剂的引导；以及
图27示出了通道的顶视图。
具体实施方式
下面，详细论述本发明实施例的制造和使用。然而，应该理解，这些实施例提供了可在各种具体情况下具体化的多种可应用的发明构思。所论述的具体实施例仅仅是说明性的，并不限制本公开的范围。
提出了包括冷却通道的新的集成电路结构及其形成方法。示出了制造实施例的中间阶段。论述了实施例的变化和操作。在各视图和说明性实施例中，类似的参考标号用于表示类似元件。
参考图1，提供了包括衬底10的晶片2。晶片2也被称为底部晶片。衬底10可以是诸如体硅衬底的半导体衬底，尽管其可以包括其他半导体材料，诸如，III族元素、IV族元素和/或V族元素。诸如晶体管(未示出)的半导体器件可以形成于衬底10的前面/前侧10a(图1中面朝上的表面10a)。
衬底穿孔(TSV)20(也表示为20_1或20_2)被形成为从衬底10的前表面10a延伸到衬底10中。隔离层22形成在TSV 20的侧壁和底部上，并且使TSV 20与衬底10电绝缘。隔离层22可以由通用的介电材料(例如，氮化硅、氧化硅(如正硅酸乙酯(TEOS)氧化物)等)形成。TSV 20包括作为用于引导电信号的信号TSV的TSV 20_2以及用于形成用来引导诸如水的冷却剂的通道的TSV 20_1。
互连结构12(包括形成在其中的金属线23和通孔25)形成在衬底10的前侧10a上，并且可以连接至半导体器件。互连结构12可包括通常已知的内层间介电(ILD)层(诸如示例层19)和金属层间介电(IMD)层21，其可以由具有低于约2.5(或者甚至低于约2.0)的k值的低k介电材料形成。另外，钝化层(诸如示例层27)可形成为互连结构12的顶面部分。钝化层可以由诸如氧化硅、氮化硅、非掺杂硅玻璃(USG)、聚酰亚胺和/或其多层的材料形成。介电层19、21和27、金属线23以及通孔25的细节在后续的附图中没有示出，尽管它们可以形成在每个实施例中。
在形成互连结构12期间，也形成了通道结构14，其还包括金属线(例如，水平延伸的部分)和通孔(例如，垂直延伸的部分)。通道结构14以及用于信号连接的金属线和通孔的形成可包括公知的镶嵌工艺。因此，通道结构14可由铜、铜合金等形成。另外，通道结构14还可以包括扩散势垒材料，诸如钛、钽、氮化钛和氮化钽。通道结构14可包括多个互连部分，每一个均形成围绕一部分介电层的金属管。通道结构14可包括不垂直对准于下部的上部和/或垂直对准于下部的上部。
接下来，如图2所示，去除被通道结构14围绕的一部分介电材料(下文也称为通道介电材料)。去除工艺可包括形成覆盖晶片2的掩模16、然后图样化掩模16，使得露出通道介电材料，同时覆盖介电材料的其他部分。然后，例如通过诸如湿蚀刻的等向性蚀刻来去除通道介电材料。通过去除通道介电材料留下的空间是通道18。根据所得到通道的设计以及通道终止的位置，可以将铜、钨、硅、金属硅化物等用作蚀刻停止层来停止蚀刻。例如，在通道18的侧壁上，通道结构14中的铜可用于停止蚀刻，而在通道18的底部20，通道18可以面向衬底10，因此，诸如硅化镍或硅化钴的金属硅化物可用于停止蚀刻。在一个实施例中，通道18包括主通道18_1和连接至主通道18_1的柱状通道(shaft)18_2。柱状通道18_2的形成可帮助去除填充主通道18_1的通道介电材料。另外，在所得到集成电路结构的使用中，柱状通道18_2还起到用于引导冷却剂的的通道的作用。
应该注意，图2所示的通道18可路过互连结构12的各层进行布线。作为通道布线的结果，通道18可包括在不同介电层中并且彼此不垂直重叠的部分18_4和18_5。这提供了用于定制通道18的设计的能力，使得只有介电层的期望部分具有贯通的通道18，而介电层的非期望部分不具有贯通的通道18。例如，互连结构12中的一些金属层(诸如，金属层1和2，分别称为M1和M2)可以仅具有贯通的最小量的通道18，而诸如M8和M9的其他部分可以具有大量通道。
参照图3，掩模16被去除，并且介电膜22被层压在晶片2上。介电膜22可以是由聚酰亚胺、聚对亚苯基苯并二噁唑(PBO)、环氧树脂、底层填料材料等形成的干膜。另外，介电膜22可以是光敏干膜，使得层压并图样化介电膜22的步骤被简化。在示例性实施例中，介电膜22由
Figure G2009102225437D00041
提供的PerMX300持久性光刻胶制成。通过使层压的介电膜22覆盖通道18，通道18被密封但未被填充。
接下来，如图4所示，对介电膜22进行图样化，并形成凸块24，从而得到如图5所示的结构。凸块24可以是焊料凸块。在其他实施例中，凸块24可以是包括铜区以及铜区上的镍层(未示出)的铜凸块。另外，薄的焊料层(未示出)或薄的金层(未示出)可以被镀在镍层的顶部之上。凸块24可连接至衬底10的表面处的集成电路器件(未示出)，和/或电连接至信号TSV 20_2。
图6示出了衬底10的背侧10b的抛光，使得露出了TSV 20。接下来，如图7所示，执行背侧光刻法，并形成并图样化掩模26(其可以是光刻胶)。通过掩模26中的开口露出TSV 20_1，同时信号TSV 20_2被覆盖。然后，如图8所示，通过掩模26中的开口蚀刻TSV 20_1。通过去除TSV 20_1所留下的开口连接至原始通道18。也就是说，通道18扩展并穿过衬底20。可控制去除工艺，使得通道结构14仍然使通道18与互连结构12中的低k介电材料绝缘。在一个实施例中，选择TSV 20_1和/或通道结构14的材料以具有高蚀刻选择性(例如，大于约100)。在图9中，掩模22被去除。
图10至图18示出了根据可选实施例的形成顶部晶片2中的通道18的中间阶段的截面图，除了互连结构12中的通道18是垂直的且不具有柱状通道。除非另外特定，该实施例中的部件的材料和形成方法基本上与由图1至图9中所示实施例的类似参考标号表示的类似部件相同。因而，图10至图18所示实施例的形成细节可以在图1至图9所示实施例的论述中发现。
参照图10，提供了包括衬底10的晶片2，并形成TSV 20和互连结构12。参照图11，通道18通过蚀刻透过互连结构12中的介电材料而形成在互连结构中。因而，通过通道18露出TSV 20。另外，扩散势垒层和铜层(未示出)可形成在通道18的侧壁上，使得通道18与互连结构12中的介电材料绝缘。可选地，除了该实施例中的通道结构14不可以包括任何柱状通道之外，可形成类似于图1所示通道结构的通道结构14(图10中未示出)，因此，所得到的通道18具有平滑且垂直的侧壁。图11还示出了一些通道18_3不直接在任一TSV 20之上。尽管在图11的截面图中所示的通道18_3彼此绝缘，但如图27所示，如果以顶视图表示，则它们可以互连。
在图12中，形成介电膜22。因此，通道18被密封。接下来，如图13所示，介电膜22被图样化，接着如图14所示，形成凸块24。在图15中，衬底10的后侧10b通过抛光而凹进去，因此，露出TSV 20(包括20_1和20_2)。在图16和图17中，形成掩模26，通过其去除TSV 20_1，使得通道18从互连结构12内部延伸到衬底10中。在图18中，掩模26被去除。
图19至图23示出了晶片100(其也被称为顶部晶片)的处理的截面图。图19和图20示出了第一实施例的形成的截面图。晶片100包括衬底110，其可以是由例如硅形成的半导体衬底。衬底110具有前侧110a(此处形成诸如晶体管的半导体器件)以及背侧110b(此处没有形成晶体管)。另外，包括介电层(未示出)中的金属线和通孔的互连结构112形成在正侧110a上。凸块124形成在互连结构112之上，并且可以电连接至半导体器件。参照图20，介电膜122被涂覆并图样化，并通过介电膜122中的开口露出凸块124。介电膜122可以由基本上与图9中的介电膜22相同的材料制成。
图21至图23示出了用于形成顶部晶片100的另一个实施例。图21示出了顶部晶片100，其基本上与图19所示的晶片100相同。接下来，如图22所示，凸块124形成在互连结构112之上。通道118也通过使用例如蚀刻而形成在互连结构122中。此外，尽管未示出，但金属管(未示出)形成在通道118的侧壁上，使得通道118与互连结构112中的(低k)介电材料绝缘。接下来，如图23所示，形成介电膜122(其可以由基本上与介电膜22(图9和图18))相同的材料形成)。由此，一些通道118被密封。
图23还示出了通过蚀刻介电膜122来将通道延伸到介电膜122中。可观察到，一些通道118延伸到介电材料122中，并且被用作冷却剂的(多个)入口和(多个)出口。未延伸到介电膜122中的那些通道开口被用于将冷却剂从(多个)入口传送至(多个)出口。
图24至图26示出了用于将底部晶片2(或底部晶片2中的底部管芯(也使用参考标号2表示))接合于顶部晶片100(或顶部晶片100中的顶部管芯(也使用参考标号100来表示))的实施例。图24示出了接合于图9所示底部管芯/晶片2的图23所示顶部管芯/晶片100。可观察到，通道118连接至通道18以形成连续的通道。介电膜122被按压到底部管芯/晶片2，因此，通道118被密封。凸块124接合于底部管芯/晶片2，并且电连接至TSV 20_2。
流体管30附接至底部管芯/晶片2。图24示出了流体管30中的一个被用作液体的入口30_1。在堆叠集成电路的操作期间，用作冷却剂的液体被馈送至入口30_1，使其流过通道18和118，并从(多个)出口30_2流出。因此，在管芯2的操作期间所产生的热量通过冷却剂消散。冷却剂还流过顶部管芯100中的通道118，因此，还将热量从顶部管芯100带出去。在一个实施例中，冷却剂是去离子水。在其他实施例中，冷却剂包括乙二醇、相变材料等。
图27示意性示出了顶视图，其中，示出了入口30_1、出口30_2以及将入口30_1连接至出口30_2的通道18和118。通道18可以或可以不包括柱状通道18_3。
图25示出了接合于图18所示底部管芯/晶片的图20所示顶部管芯/晶片100。可观察到，没有通道形成在顶部管芯/晶片100中，因此，仅底部管芯2被冷却剂冷却。
图26示出了接合于图18所示底部管芯/晶片2的图23所示顶部管芯/晶片100。可观察到，通道118连接至通道18以形成连续的通道，使得冷却剂可以流过通道118和18，因此，顶部管芯100和底部管芯2都可以被冷却。此外，介电膜122被按压至底部管芯/晶片2，因此，通道118被密封。
在这些实施例中，用于引导冷却剂的通道形成在底部管芯以及(可能地)顶部管芯的正侧。在底部管芯和顶部管芯的操作期间，在底部管芯中所产生的热量可通过流过底部管芯的冷却剂而带走。这导致散消散性能的显著增强，特别是对于底部管芯。因此，这些实施例可以用于诸如计算单元的产生更多热量的管芯。
尽管已详细描述了实施例及其优点，但应该理解，在不背离所附权利要求所限定的实施例的精神和范围的情况下，可进行各种改变、替换和变更。此外，本发明的范围并不旨在限制于本说明书中所描述的物质、装置、方法和步骤的工艺、机器、产品以及组合的特定实施例。本领域的普通技术人员从本公开中容易理解，可以根据本公开利用现有或后来发展的物质、装置、方法或步骤(其执行基本上与本文中所描述的对应实施例相同的功能或者基本实现与本文所描述的对应实施例相同的结果)的工艺、机器、产品和组合。因此，所附权利要求旨在包括在其范围内，诸如物质、装置、方法或步骤的工艺、机器、产品、组合。另外，每项权利要求构成单独的实施例，并且各项权利要求和实施例的结合都在本发明的范围内。

Claims (15)

1.一种集成电路结构，包括：
第一管芯，包括：
第一半导体衬底；
第一介电层，在所述第一半导体衬底之上；
第一互连结构，处于所述第一介电层中；
第一多个通道，从所述半导体衬底的内部延伸至所述第一介电层的内部；以及
第一介电膜，在所述第一互连结构之上并密封所述第一多个通道的一部分，其中，所述第一多个通道被配置为使液体流过其中。
2.根据权利要求1所述的集成电路结构，还包括第一流体管和第二流体管，所述第一流体管和所述第二流体管的每一个均附接至所述多个通道中的一个，其中，所述流体管的内部空间与所述第一多个通道形成连续空间。
3.根据权利要求2所述的集成电路结构，其中，所述第一多个通道将所述第一流体管连接至所述第二流体管，以及其中，从所述第一半导体衬底的正侧贯穿至所述第一半导体衬底的背侧，所述第一多个通道中的第一个连接至所述第一流体管，以及所述第一多个通道中的第二个连接至所述第二流体管。
4.根据权利要求1所述的集成电路结构，其中，所述第一多个通道中的至少一部分被垂直限制在所述第一介电层的钝化层与所述第一介电膜之间，其中，所述第一介电膜是光敏膜。
5.根据权利要求1所述的集成电路结构，还包括第二管芯，所述第二管芯接合至所述第一管芯中的所述第一半导体衬底的背侧，
其中，所述第二管芯还包括：
第二半导体衬底；
第二互连结构，在第二介电层中，并且在所述第二半导体衬底的正侧上；
第二多个通道，从所述第二半导体衬底的内部延伸到所述第二介电层的内部，其中，所述第二多个通道的内部空间连接至所述第一多个通道的内部空间；以及
第二介电膜，覆盖所述第二互连结构并密封所述第二多个通道中的一部分。
6.根据权利要求5所述的集成电路结构，其中，所述第二管芯还包括：
第二半导体衬底；
第二互连结构，在第二介电层中，并且在所述第二半导体衬底的正侧上，其中，不具有形成在所述第二介电层中并连接至所述第一多个通道的通道。
7.根据权利要求1所述的集成电路结构，其中，所述第一多个通道包括所述第一介电层的第一层中的第一部分以及所述第一介电层的第二层中的第二部分，并且其中，所述第一部分没有与所述第二部分垂直重叠，
其中，所述集成电路结构还包括柱状通道，所述柱状通道在所述互连结构中，所述柱状通道的内部空间是所述第一多个通道的一部分。
8.一种集成电路结构，包括：
第一管芯，包括：
第一半导体衬底；
第一互连结构，包括第一介电层中的金属线和通孔，并在所述第一半导体衬底的正侧上；
第一开口和第二开口，从所述第一半导体衬底的正侧延伸至所述第一半导体衬底的后侧；以及
第一多个通道，在所述第一介电层中，并将所述第一开口连接至所述第二开口；以及
第二管芯，接合至所述第一管芯。
9.根据权利要求8所述的集成电路结构，其中，所述第一多个通道通过所述第一多个通道的侧壁上的金属管而与第一多个介电层分离。
10.根据权利要求8所述的集成电路结构，其中，所述第二管芯包括第二多个通道，并被配置为将所述第一开口连接至所述第二开口。
11.根据权利要求8所述的集成电路结构，其中，所述第二管芯不包括连接在所述第一开口和所述第二开口之间的通道。
12.根据权利要求8所述的集成电路结构，还包括填充所述第一开口、所述第二开口和所述第一多个通道的冷却剂，其中，所述第一多个通道被配置为使所述冷却剂从所述第一开口流至所述第二开口。
13.一种集成电路结构，包括：
第一管芯，包括：
第一半导体衬底；
衬底穿孔(TSV)，从所述第一半导体衬底的前面延伸到所述第一半导体衬底的背面；
第一互连结构，包括第一介电层中的金属线和通孔，并在所述第一半导体衬底的前侧上；
通道，从所述第一半导体衬底的前面延伸到所述第一半导体衬底的背面，其中，所述通道被配置为使液体流过其中；以及
第二管芯，结合至所述第一管芯，并包括：
第二半导体衬底；
第二互连结构，包括第二介电层中的附加金属线和附加通孔，并在所述第二半导体衬底的前侧上；和
凸块，在所述第二管芯的表面处，并电连接至所述TSV。
14.根据权利要求13所述的集成电路结构，还包括流体管，所述流体管附接至所述第一管芯的背面，其中，所述流体管的内部空间与所述第一半导体衬底中的所述通道相结合，以形成连续的空间。
15.根据权利要求13所述的集成电路结构，还包括第一多个通道，所述第一多个通道在所述第一介电层中，其中，所述第一多个通道被配置为使液体从所述第一半导体衬底中的通道流到所述第一多个通道，
以及其中，所述第二管芯还包括第二多个通道，所述第二多个通道在所述第二介电层中，其中，所述第二多个通道使液体从所述第一半导体衬底中的通道流到所述第二多个通道。
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