CN112151675A - 半导体结构和形成半导体结构的方法 - Google Patents

半导体结构和形成半导体结构的方法 Download PDF

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Publication number
CN112151675A
CN112151675A CN202010597523.4A CN202010597523A CN112151675A CN 112151675 A CN112151675 A CN 112151675A CN 202010597523 A CN202010597523 A CN 202010597523A CN 112151675 A CN112151675 A CN 112151675A
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semiconductor substrate
semiconductor
trench
capacitor
capacitor electrode
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高敏峰
杨敦年
林杏芝
刘人诚
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一些实施例涉及包括具有正面和背面的半导体衬底的半导体结构。互连结构设置在正面上方。互连结构包括可操作地将设置在半导体衬底的正面中或上的半导体晶体管器件彼此耦接的多个金属线和通孔。沟槽设置在半导体衬底的背面中。沟槽填充有内部电容器电极、位于内部电容器电极上面的电容器介电层和位于电容器介电层上面的外部电容器电极。本发明的实施例还涉及形成半导体结构的方法。

Description

半导体结构和形成半导体结构的方法
技术领域
本发明的实施例涉及半导体结构和形成半导体结构的方法。
背景技术
移动电话和其它移动器件通常依靠陶瓷电容器和其它无源器件，这些电容器和其它无源器件离散地安装至移动器件的印刷电路板(PCB)并且通过PCB电耦接至移动器件的集成电路(IC)。然而，这占用了PCB上的大量表面积，并且因此限制了移动器件尺寸和/或移动器件功能。此外，离散地安装和电耦接无源器件增加了制造成本。因此，移动器件越来越多地转向集成无源器件(IPD)，以减小尺寸、降低成本并且增加功能性。IPD是一个或多个无源器件的集合，这些器件嵌入在单片器件中并且封装为集成电路(IC)。
发明内容
本发明的一些实施例提供了一种半导体结构，包括：半导体衬底，具有正面和背面；前侧互连结构，设置在所述正面上方，所述前侧互连结构包括可操作地将设置在所述半导体衬底的正面中或上的半导体器件彼此耦接的多个金属线和通孔；以及沟槽，设置在所述半导体衬底的所述背面中，所述沟槽在所述沟槽中填充有内部电容器电极、位于所述沟槽中和所述内部电容器电极上面的电容器介电层以及位于所述沟槽中和所述电容器介电层上面的外部电容器电极。
本发明的另一些实施例提供了一种半导体结构，包括：第一半导体衬底，具有第一正面和第一背面；第二半导体衬底，具有第二正面和第二背面，所述第二半导体衬底设置在所述第一半导体衬底上方；第一互连结构，设置在所述第一半导体衬底的所述第一正面和所述第二半导体衬底的所述第二正面之间，所述第一互连结构包括可操作地将设置在所述第一半导体衬底的所述第一正面中或上的第一半导体器件彼此耦接的第一多个金属线和通孔；第二互连结构，设置在所述第一互连结构和所述第二半导体衬底的所述第二正面之间，所述第二互连结构包括可操作地将设置在所述第二半导体衬底的所述第二正面中或上的第二半导体器件彼此耦接的第二多个金属线和通孔；第一沟槽，设置在所述第一半导体衬底的所述第一背面中，所述第一沟槽填充有第一内部电容器电极、位于所述第一内部电容器电极上面的第一电容器介电层和位于所述第一电容器介电层上面的第一外部电容器电极；以及第二沟槽，设置在所述第二半导体衬底的所述第二背面中，所述第二沟槽填充有第二内部电容器电极、位于所述第二内部电容器电极上面的第二电容器介电层和位于所述第二电容器介电层上面的第二外部电容器电极。
本发明的又一些实施例提供了一种形成半导体结构的方法，包括：在半导体衬底的前侧上形成半导体器件；在所述半导体衬底的背侧中形成沟槽；在所述半导体衬底的所述背侧上的所述沟槽中交替形成导电层和绝缘层，以建立背侧电容器；以及在所述半导体衬底的所述背侧上形成背侧互连结构，以耦接至所述背侧电容器的电容器电极。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1示出了包括具有高电容密度的背侧沟槽电容器的半导体结构的一些实施例的截面图。
图2示出了包括具有高电容密度的背侧沟槽电容器的半导体结构的一些实施例的截面图。
图3示出了包括背侧沟槽电容器的三维IC的一些实施例的截面图。
图4至图11示出了一系列截面图，它们共同示出了根据本发明的一些实施例的制造半导体结构的一些实施例。
图12示出了描述根据本发明的方法的一些实施例的流程图。
具体实施方式
本发明提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其它方式定向(旋转90度或在其它方位上)，而在此使用的空间相对描述符可以同样地作出相应的解释。
金属绝缘体金属(MIM)或金属氧化物金属(MOM)电容器通常嵌入在集成电路(IC)中并且用于代替陶瓷电容器以减小移动器件的尺寸、减小移动器件的成本、增加移动器件的功能或上述的任意组合。在某些情况下，将MIM或MOM电容器布置在半导体衬底的前侧上面的互连结构中。例如，互连结构可以由堆叠在彼此上方并且通过垂直通孔互连的多个水平金属线(例如，导线)构成，其中，互连结构可操作地将半导体衬底前侧上的半导体器件(例如，晶体管)彼此耦接，以实现预定的电路配置。MIM/MOM电容器的电极可以形成在衬底前侧上方的互连结构中，从而使得MIM/MOM电容器可以容易地与IC的其余部分集成在一起。然而，对于大电容值，对于这种MIM/MOM电容器通常需要IC上的较大面积。这增加了IC的成本，并且因此在某些方面还不是最佳解决方案。
本申请的各个实施例针对形成在半导体衬底的背侧上的电容器。因此，在半导体衬底的前侧上形成诸如晶体管的半导体器件，并且在衬底的前侧上方形成互连结构，以可操作地将半导体器件彼此耦接。沟槽形成在衬底的背侧中，并且交替地内衬有堆叠在彼此上方的导电层和介电层，以在衬底背侧的沟槽中建立电容器。通过在衬底背侧的沟槽中形成电容器，与传统的MIM/MOM电容器相比，电容器对IC的整体面积的影响受到限制。此外，在某些情况下，可以将多个这样的衬底(每个衬底包括一个或多个背侧电容器)堆叠在彼此上方，以形成在相对较小的占位面积中提供相对较高的电容值的三维IC。
参考图1，提供了包括背侧沟槽电容器的半导体结构100的一些实施例的截面图。
半导体结构100包括具有正面102f和背面102b的半导体衬底102。诸如晶体管的半导体器件110设置在正面102f上。所示的半导体器件110表现为包括掺杂有第一掺杂导电率(例如，n型)的第一源极/漏极区域126和第二源极/漏极区域128的晶体管。示为与图1中的阱区域130相对应的体区域掺杂有第二掺杂导电率(例如，p型)，并且将第一源极/漏极区域126和第二源极/漏极区域128彼此分隔开。第二掺杂类型与第一掺杂类型相反。栅电极132设置在体区域上方，并且通过栅极电介质134与体区域分隔开。包括有源器件(诸如双极结型晶体管(BJT)或finFET)和/或无源器件(诸如电阻器或二极管)的其它半导体器件可以存在于正面102f上。
前侧互连结构104设置在正面102f上方。前侧互连结构104包括可操作地将半导体器件110彼此耦接的多个前侧金属线和前侧通孔。
前侧互连结构104包括嵌入在介电材料层中的多个导电层。介电材料层包括多个层间介电(ILD)层106a、106b、106c，每层均可以包括合适的介电材料。例如，在本实施例中，多个ILD层106a、106b、106c可以包括低介电常数(低-k)材料，该材料的常数低于热氧化硅的常数。在其它实施例中，ILD层106a、106b、106c包括二氧化硅或另一介电材料。介电材料可以通过CVD、HDPCVD、PECVD、它们的组合或其它合适的工艺形成。为了说明的目的，在图1中仅示出了三个前侧ILD层，但是应该理解，可以实现任何数量的前侧ILD层，并且所示出的前侧ILD层仅是示例性的。
前侧互连结构104中的多个导电层提供各个半导体器件110之间的互连。多个导电层包括金属线，该金属线包括金属一线108a、金属二线108b等至最顶部金属线108c。多个导电层还包括用于将金属一线108a耦接至半导体器件110的接触件110a，以及用于耦接相邻金属线(例如，108b和108c)的通孔110b、110c。前侧互连结构104的导电层可以包括通过包括PVD、CVD、它们的组合的工艺或其它合适的工艺形成的导电材料，诸如铝、铝/硅/铜合金、钛、氮化钛、钨、多晶硅、金属硅化物或它们的组合。形成前侧互连结构104的其它制造技术可以包括光刻工艺和蚀刻以图案化用于垂直连接(例如，通孔/接触件)和水平连接(例如，金属层)的导电材料。可选地，可以使用铜多层互连来形成金属图案。铜互连结构可以包括铜、铜合金、钛、氮化钛、钽、氮化钽、钨、多晶硅、金属硅化物或它们的组合。铜互连可以通过包括介电沉积、蚀刻、沉积和平坦化的镶嵌技术形成。沉积可以包括溅射、电镀、CVD或其它合适的工艺。
沟槽112设置在半导体衬底102的背面102b中。沟槽112填充有底部电容器电极114、位于底部电容器电极114上面的电容器介电层116和位于电容器介电层116上面的上部电容器电极118。电容器介电层116将底部电容器电极114和上部电容器电极118彼此分隔开，从而在半导体衬底的最靠近背面102b的区域中建立一个或多个电容器元件。
在图1的实施例中，沟槽112的最内表面112i与半导体衬底中的半导体器件110的阱区域130的底部范围间隔开并且位于其正下方。在一些实施例中，掺杂区域136内衬沟槽112的最内表面、沟槽侧壁以及可选的半导体衬底的背侧，并且可以用作另一个电容器电极。因此，在图1中，第一电容器元件101可以包括由电容器介电层116的内部部分间隔开的掺杂区域136和底部电容器电极114，而第二电容器元件103可包括由电容器介电层116的外部部分间隔开的底部电容器电极114和上部电容器电极118。在一些实施例中，第一电容器元件101可以与第二电容器元件103并联布置，以实现每单位面积的电容的进一步增加。
背侧互连结构120包括将底部电容器电极114和上部电容器电极118可操作地耦接至半导体器件110和/或其它背侧沟槽电容器的多个背侧金属线和背侧接触件/通孔。在一些实施例中，背侧金属线比前侧金属线厚，但是在其它实施例中，背侧金属线与前侧金属线的厚度相同。该配置在IC的相对较小的区域中提供相对较高的密度电容。
背侧互连结构120包括嵌入在背侧介电材料层中的多个背侧导电层。介电材料层包括多个背侧ILD层142a、142b，每层均可以包括合适的介电材料。例如，在本实施例中，多个背侧ILD层142a、142b可以包括低介电常数(低-k)材料，该材料的常数低于热氧化硅的常数。在其它实施例中，背侧ILD层142a、142b包括二氧化硅或另一介电材料。介电材料可以通过CVD、HDPCVD、PECVD、它们的组合或其它合适的工艺形成。为了说明的目的，在图1的背侧互连结构120中仅示出了两个背侧ILD层，但是应该理解，可以实现任何数量的背侧ILD层，并且所示的背侧ILD层仅是示例性的。
背侧互连结构120中的多个导电层提供各个电容器电极之间的互连。多个导电层包括金属线，该金属线包括金属一线122a和最顶部金属线122b。多个导电层还包括接触件124，以将金属线耦接至电容器电极。背侧互连结构120的导电层可包括通过包括PVD、CVD、它们的组合的工艺或其它合适的工艺形成的导电材料，诸如铝、铝/硅/铜合金、钛、氮化钛、钨、多晶硅、金属硅化物或它们的组合。形成背侧互连结构120的其它制造技术可以包括光刻工艺和蚀刻，以图案化用于垂直连接(例如，通孔/接触件)和水平连接(例如，金属层)的导电材料。可选地，可以使用铜多层互连来形成金属图案。铜互连结构可以包括铜、铜合金、钛、氮化钛、钽、氮化钽、钨、多晶硅、金属硅化物或它们的组合。铜互连可以通过包括介电沉积、蚀刻、沉积和平坦化的镶嵌技术形成。沉积可以包括溅射、电镀、CVD或其它合适的工艺。
图2示出了另一实施例，其中，沟槽112的最内表面112i从半导体衬底中的半导体器件110的阱区域130横向偏移并且与半导体器件110的阱区域130垂直重叠。此外，图2示出了背侧沟槽电容器包括底部电容器电极114和中间电容器电极117的实例，它们通过下部的电容器电介质116a彼此分隔开；并且上部电容器电极118通过上部的电容器介电层116b与中间电容器电极117分隔开。在一些实施例中，掺杂区域136内衬沟槽112的最内表面、沟槽侧壁和可选的半导体衬底的背侧，并且可以用作另一电容器电极。因此，在图2中，第一电容器元件101可以包括由底部的电容器介电层116c间隔开的掺杂区域136和底部电容器电极114。第二电容器元件103可以包括底部电容器电极114和中间电容器电极117，它们通过下部的电容器介电层116a间隔开。第三电容器元件105可以包括中间电容器电极117和上部电容器电极118，它们通过上部的电容器介电层116b间隔开。在一些实施例中，第一电容器元件101可以与第二电容器元件103和/或第三电容器元件105并联布置，以实现每单位面积的电容的进一步增加。图1的上部电容器电极118为立方体主体，而图2的上部电容器电极118的截面为U形。在图2的实例中，底部电容器电极114和/或中间电容器电极117的上表面低于金属一线122a的上表面，并且在一些实施例中，上电容器电极118的上表面可以与金属一线122a的上表面齐平或共面。
应该理解，尽管图1和图2示出为实例，但是这些示出的实施例是非限制性的。例如，尽管图1示出了设置在沟槽的最内表面上方的两个导电层，并且图2示出了设置在沟槽的最内表面上方的三个导电层，但是可以存在任何数量的导电层。通常，当相应的电容器电极并联耦接时，添加额外的导电层将趋于进一步增加电容。但是，这些额外的层也增加了处理时间和复杂性，因此如图1所示具有较少的导电层提供了一种流线型方法。
参考图3，提供了半导体结构300的一些实施例的截面图。半导体结构300包括堆叠在彼此上方的多个衬底，其中一个或多个衬底包括至少一个背侧沟槽电容器。
半导体结构300包括具有第一正面302f和第一背面302b的第一半导体衬底302。第二半导体衬底304具有第二正面304f和第二背面304b。第二半导体衬底304设置在第一半导体衬底302上方。第一互连结构306设置在第一半导体衬底302的第一正面302f和第二半导体衬底304的第二正面304f之间。第一互连结构306包括可操作地将设置在第一半导体衬底302的第一正面302f中或上的第一半导体器件彼此耦接的第一多个金属线和通孔。第二互连结构312设置在第一互连结构306和第二半导体衬底304的第二正面304f之间。第二互连结构312包括可操作地将设置在第二半导体衬底304的第二正面304f中或上的第二半导体器件彼此耦接的第二多个金属线和通孔。第一沟槽317设置在第一半导体衬底302的第一背面302b中。第一沟槽317填充有第一内部电容器电极314、位于第一内部电容器电极314上面的第一电容器介电层316和位于第一电容器介电层316上面的第一外部电容器电极318。因此，例如，在一些实施例中，可以将图1和/或图2中的电容器插入图3的第一沟槽317中。第二沟槽319设置在第二半导体衬底304的第二背面中。第二沟槽319填充有第二内部电容器电极344、位于第二内部电容器电极上面的第二电容器介电层346和位于第二电容器介电层上面的第二外部电容器电极348。因此，例如，在一些实施例中，可以将图1和/或图2中的电容器插入图3的第二沟槽319中。
半导体结构300还包括具有第三正面320f和第三背面320b的第三半导体衬底320。第三半导体衬底320设置在第一半导体衬底302下面。第三互连结构322设置在第一半导体衬底的第一背面302b和第三半导体衬底的第三正面320f之间。第三互连结构322包括可操作地将设置在第三半导体衬底的第三正面中或上的第三半导体器件彼此耦接的第三多个金属线和通孔。第三沟槽326设置在第三半导体衬底的第三背面中。第三沟槽326填充有第三内部电容器电极354、位于第三内部电容器电极上面的第三电容器介电层356和位于第三电容器介电层上面的第三外部电容器电极358。因此，例如，在一些实施例中，可以将图1和/或图2中的电容器插入图3的第三沟槽326中。
半导体结构300还包括：具有第四正面328f和第四背面328b的第四半导体衬底328。第四半导体衬底328设置在第三半导体衬底320下面。第四互连结构330设置在第三半导体衬底320的第三背面和第四半导体衬底328的第四正面之间。第四互连结构330包括可操作地将设置在第四半导体衬底328的第四正面中或上的第四半导体器件彼此耦接的第四多个金属线和通孔。第四半导体衬底328的第四厚度大于第一半导体衬底302第一厚度。在某些情况下，还可以存在额外的衬底(例如，350)，并且还可以包括额外的背侧沟槽电容器(例如，370)。
例如包括诸如铜或铝的金属的接合焊盘或接地焊盘372设置在钝化层374上方，并且通过再分布层(RDL)通孔376耦接至第二背侧互连结构308。接合焊盘或接地焊盘372可以通过RDL通孔376和第二背侧互连结构308可操作地耦接至3DIC上的一个或多个电容器或半导体器件。钝化层374可以包括例如树脂、环氧树脂、塑料或陶瓷材料。
在一些实施例中，第一、第二和第三半导体衬底的每个对于第一、第二和第三半导体衬底的每个具有相等的第一厚度，并且第四半导体衬底328具有大于第一厚度的第四厚度。
半导体结构300还包括延伸穿过各个衬底的衬底通孔(TSV)。例如，第一半导体衬底302包括TSV 340，以将第一互连结构306耦接至第三互连结构322。衬底通孔具有在第一前侧上间隔开第一距离并且在第一背侧上间隔开第二距离的外部侧壁，第一距离小于第二距离。其它半导体衬底也可以包括衬底通孔，在一些实施例中，最下面的衬底(例如，第四半导体衬底328)不存在衬底通孔。
半导体结构300还包括各个接合结构，以将各个衬底和互连结构彼此接合。例如，设置在第一半导体衬底302的第一前侧上的第一前侧接合结构342接合至设置在第二半导体衬底304上方的第二前侧接合结构345。第一前侧接合结构342对应于第二前侧接合结构345，并且通过混合接合而接合至第二前侧接合结构。在一些实施例中，第一前侧接合结构342包括设置在介电层347的场中的导电部件(例如，金属部件343)，而第二前侧接合结构345包括设置在介电层349的场中的导电部件(例如，金属部件351)。此外，第一前侧接合结构342的一些部件381可以电耦接至第一半导体衬底302上的半导体器件和/或电容器，而其它部件是有助于接合的“伪”结构382，但与衬底上的半导体器件和电容器电浮置或断开。
半导体衬底302、304、320、328和/或350可以是或包括例如块状半导体衬底、SOI衬底或一些其它半导体衬底。此外，半导体衬底可以是或包括例如单晶硅、一些其它硅或一些其它半导体材料。
在一些实施例中，电容器介电层316、346包括二氧化硅、高k介电材料或低k介电材料或由二氧化硅、高k介电材料或低k介电材料制成。使用高k介电材料是有利的，因为与二氧化硅或低k介电材料相比，它在给定面积上增加了电容器的电容。金属互连线和/或通孔通常由金属制成或包括金属，诸如例如铝和/或铜。
在一些实施例中，通过形成用于第一半导体衬底的半导体晶体管器件、前侧互连结构、背侧电容器结构和背侧互连结构来形成图3的半导体结构300(可选地，例如，在衬底的背侧中形成沟槽之前，可以通过使用研磨步骤来减薄半导体衬底，在这种情况中，与图1的电容器相比，背侧电容器更类似于图2的电容器)。半导体晶体管器件、前侧互连结构、背侧电容器结构和背侧互连结构也可以形成为用于其它半导体衬底。然后可以例如通过使用混合接合将一个衬底的前侧互连结构接合至另一衬底的前侧互连结构或背侧互连结构。可以以这种方式堆叠衬底以形成图3的结构。
图4至图12示出了一系列截面图，它们共同示出了根据本发明的一些实施例的制造半导体结构的一些实施例。
在图4中，提供第一半导体衬底102，并且在第一半导体衬底102的第一前侧102f上形成多个半导体器件110，诸如晶体管。在一些实施例中，第一半导体衬底102可以包括单晶硅晶圆、绝缘体上半导体(SOI)晶圆或其它半导体衬底。在第一衬底的第一前侧上方形成第一前侧互连结构104，并且还形成衬底通孔(TSV)186。在一些实施例中，可以在半导体器件110之前形成TSV 186，但是在其它实施例中，可以在半导体器件110之后形成TSV 186。通常，TSV 186包括铜或铜合金，并且可以具有内衬有例如包括钽或钛的阻挡层的侧壁。
在图5中，在第一半导体衬底102的背侧中形成第一沟槽112。第一沟槽112可以通过在第一半导体衬底102的背侧上旋涂光刻胶溶液、烘烤光刻胶，然后通过中间掩模或光掩模将光刻胶暴露于光形成，并且显影曝光的光刻胶以在第一衬底的背侧上形成图案化掩模。然后，利用位于适当的位置的图案化掩模，进行蚀刻。蚀刻可以是湿蚀刻或干蚀刻，并且如果需要高高宽比的沟槽，则可以在一些实施方式中使用博世(Bosch)蚀刻工艺。在其它实施例中，极紫外(UV)光刻和/或电子束光刻技术可用于形成第一沟槽112等。
在图6中，在第一半导体衬底102的背侧上方，包括在沟槽112的最内表面和侧壁上，形成诸如高k介电层的第一介电层116a。第一介电层116a可以通过物理汽相沉积(PVD)、化学汽相沉积(CVD)、原子层沉积(ALD)或热氧化等形成。在一些实施例中，第一介电层116a是共形层。在一些实施例中，第一介电层116a是高k电介质，并且可以包括铪和/或锆，并且可以采取硅酸铪、硅酸锆、二氧化铪和/或二氧化锆等形式。
仍然参考图6，然后在第一介电层116a上方形成第一导电层114。第一导电层114可以对应于电容器电极，并且可以包括金属或掺杂的多晶硅并且可以是共形的。例如，金属可以包括铜、铝、钨、镍、钛、锆和/或其它；并且可以通过PVD、CVD、ALD、溅射或电镀等形成。
在图7中，第一导电层114已经被图案化，例如，通过形成光掩模，然后利用位于适当的位置的光掩模来实施蚀刻。然后例如通过灰化或等离子体剥离去除光掩模，并且在沟槽112中的第一导电层114的上表面上方形成第二介电层116b，诸如高k介电层。第二介电层116b内衬沟槽的最内表面和侧壁、内衬沟槽中的第一导电层的内部侧壁，并且在衬底的背侧上的第一导电层114和第一介电层116a的上方延伸出沟槽。在一些实施例中，第二介电层116b是共形层。第二介电层116b可以通过PVD、CVD、ALD或热氧化等形成。在一些实施例中，第二介电层116b可以包括高k介电材料，包括铪和/或锆，并且可以采取硅酸铪、硅酸锆、二氧化铪和/或二氧化锆等形式。
仍然参考图7，然后在第二介电层116b上方形成第二导电层118。第二导电层118可以对应于电容器电极，并且可以包括金属或掺杂的多晶硅。例如，金属可以包括铜、铝、钨、镍、钛、锆和/或其它；并且可以通过PVD、CVD、ALD、溅射或电镀等形成。
在图8中，实施化学机械平坦化(CMP)操作。在所示的实施例中，CMP操作将第一导电层114的上表面与第二导电层118的上表面平坦化。应该理解，在其它实施例中，例如在存在额外的电容器介电层和/或额外的导电层的情况下，CMP操作可以在一个或多个导电层和/或电容器介电层上停止，而使这些层中的其它层保持在不同的台阶高度。
在图9中，形成第一背侧互连结构120。第一背侧互连结构120可以例如通过在图8的平坦化的上表面上方形成第一ILD层形成，并且然后使用光刻在第一ILD层中形成接触开口。可以在接触开口中形成例如可以包括钨、铝和/或铜的金属，并且然后可以平坦化以建立接触件。可以形成其它ILD层，并且然后可以形成通孔和线孔，并用诸如铜或铜铝合金的金属填充，并且然后可以平坦化以形成第一背侧互连结构的金属线和通孔。
在图10中，第一半导体结构100(其包括第一半导体衬底102、设置在第一半导体衬底102的前侧上的第一前侧互连结构104以及设置在第一半导体衬底102的背侧上的第一背侧互连结构120)接合至第二半导体结构200(其包括第二半导体衬底202、第二前侧互连结构204和第二背侧互连结构220)。接合工艺是混合接合工艺，由此将第一半导体结构100的介电材料接合至第二半导体结构200的介电材料；并且由此将第一半导体结构100的金属接合至第二半导体结构200的金属。
在图11中，包括第三半导体结构300、第四半导体结构400和第五半导体结构500的额外的半导体结构接合在一起以形成三维IC 1100。通常，这些额外的半导体结构使用接合结构接合在一起，其可以包括混合接合，或可以包括焊球、焊料凸块、诸如铜或铜合金柱的导电柱、微凸块或其它接合结构。
例如，具有第三正面303f和第三背面303b的第三半导体衬底303可以接合至第一背侧互连结构120。第三沟槽326设置在第三半导体衬底302的第三背面中。第三沟槽326填充有第三内部电容器电极、位于第三内部电容器电极上面的第三电容器介电层和位于第三电容器介电层上面的第三外部电容器电极。因此，例如，在一些实施例中，可以将图1和/或图2中的电容器插入第三沟槽326中。因此，在接合之后，将第三半导体衬底303设置在第一半导体衬底102下面。第一背侧互连结构120和第三前侧互连结构305设置在第一半导体衬底的第一背面102b和第三半导体衬底的第三正面303f之间。第一背侧互连结构120包括多个金属线和通孔，其第一沟槽电容器的电容器电极可操作地耦接至3DIC中的其它导电部件。第三前侧互连结构305还包括可操作地将设置在第三衬底中或上的半导体器件彼此耦接的多个金属线和通孔。
也可以将具有第四正面402f和第四背面402b的第四半导体衬底402以及具有第五正面502f和第五背面502b的第五半导体衬底502接合为3DIC 1100的一部分。存在第四前侧互连结构404。还存在第五前侧互连结构504和第五背侧互连结构520。第五前侧互连结构504接合至第三背侧互连结构321，并且第五背侧互连结构520接合至第四前侧互连结构404。
图12示出了根据本发明的一些方面的用于形成半导体结构的方法的一些实施例。应该理解，在其它实施例中，可以以不同的顺序实施所示出的步骤，在一些其它实施例中，可以省略一个或多个示出的步骤，并且在其它实施方式中可以存在未在图12中示出的额外的步骤。因此，图12仅是非限制性实例。
在1202中，在半导体衬底的前侧上形成半导体器件。
在1204中，在半导体衬底的背侧中形成沟槽。
在1206中，在半导体衬底的背侧上的沟槽中形成交替的导电层和绝缘层，以建立背侧电容器。
在1208中，在半导体衬底的背侧上形成背侧互连结构，以耦接至背侧电容器的电容器电极。
在1210中，将半导体衬底可选地接合至其它半导体衬底以形成3DIC。
因此，本发明的一些实施例涉及半导体结构。该结构包括具有正面和背面的半导体衬底。前侧互连结构设置在正面上方，并且包括可操作地将设置在半导体衬底的正面中或上的半导体器件彼此耦接的多个金属线和通孔。沟槽设置在半导体衬底的背面中。沟槽在沟槽中填充有内部电容器电极、位于沟槽中并且内部电容器电极上面的电容器介电层以及位于沟槽中和电容器介电层上面的外部电容器电极。在一些实施例中，所述沟槽的底面与所述半导体衬底中的半导体晶体管器件的阱区域的底部范围间隔开并且位于所述半导体晶体管器件的阱区域的底部范围正下方。在一些实施例中，所述沟槽的底面从所述半导体衬底中的半导体晶体管器件的阱区域横向偏移并且与所述半导体晶体管器件的阱区域垂直重叠。在一些实施例中，所述电容器介电层密封所述内部电容器电极的上表面、下表面和侧壁，并且所述外部电容器电极具有与所述沟槽中的所述电容器介电层直接接触的底面和外部侧壁。在一些实施例中，所述内部电容器电极延伸出所述沟槽，因此所述内部电容器电极的最外表面与所述电容器介电层的最外表面齐平和/或共面。在一些实施例中，半导体结构还包括：掺杂区域，内衬所述沟槽的侧壁和所述沟槽的底面，所述掺杂区域与所述外部电容器电极并联电耦接。在一些实施例中，所述外部电容器电极具有U形截面。在一些实施例中，半导体结构还包括：中间电容器电极，设置在所述内部电容器电极和所述外部电容器电极之间的沟槽中。在一些实施例中，与最靠近所述半导体衬底的所述背侧的背侧互连结构中的金属线的上表面相比，所述内部电容器电极或所述中间电容器电极中的至少一个的最外表面更靠近所述半导体衬底的所述背侧。在一些实施例中，所述外部电容器电极的最外表面与所述金属线的上表面齐平或共面。
其它实施例涉及半导体结构。该半导体结构包括具有第一正面和第一背面的第一半导体衬底。第二半导体衬底具有第二正面和第二背面。第二半导体衬底设置在第一半导体衬底上方。第一互连结构设置在第一半导体衬底的第一正面和第二半导体衬底的第二正面之间。第一互连结构包括可操作地将设置在第一半导体衬底的第一正面中或上的第一半导体器件彼此耦接的第一多个金属线和通孔。第二互连结构设置在第一互连结构和第二半导体衬底的第二正面之间。第二互连结构包括可操作地将设置在第二半导体衬底的第二正面中或上的第二半导体器件彼此耦接的第二多个金属线和通孔。第一沟槽设置在第一半导体衬底的第一背面中。第一沟槽填充有第一内部电容器电极、位于第一内部电容器电极上面的第一电容器介电层和位于第一电容器介电层上面的第一外部电容器电极。第二沟槽设置在第二半导体衬底的第二背面中。第二沟槽填充有第二内部电容器电极、位于第二内部电容器电极上面的第二电容器介电层和位于第二电容器介电层上面的第二外部电容器电极。在一些实施例中，半导体结构还包括：第三半导体衬底，具有第三正面和第三背面，所述第三半导体衬底设置在所述第一半导体衬底下面；第三互连结构，设置在所述第一半导体衬底的所述第一背面和所述第三半导体衬底的所述第三正面之间，所述第三互连结构包括可操作地将设置在所述第三半导体衬底的所述第三正面中或上的第三半导体器件彼此耦接的第三多个金属线和通孔；以及第三沟槽，设置在所述第三半导体衬底的所述第三背面中，所述第三沟槽填充有第三内部电容器电极、位于所述第三内部电容器电极上面的第三电容器介电层和位于所述第三电容器介电层上面的第三外部电容器电极。在一些实施例中，半导体结构还包括：第四半导体衬底，具有第四正面和第四背面，所述第四半导体衬底设置在所述第三半导体衬底下面；第四互连结构，设置在所述第三半导体衬底的所述第三背面和所述第四半导体衬底的所述第四正面之间，所述第四互连结构包括可操作地将设置在所述第四半导体衬底的所述第四正面中或上的第四半导体器件彼此耦接的第四多个金属线和通孔；以及其中，所述第四半导体衬底的第四厚度大于所述第一半导体衬底的第一厚度。在一些实施例中，所述第一半导体衬底、所述第二半导体衬底和所述第三半导体衬底具有所述第一厚度，并且所述第四半导体衬底具有大于所述第一厚度的所述第四厚度。在一些实施例中，半导体结构还包括：衬底通孔，延伸穿过所述第一半导体衬底以将所述第一互连结构耦接至所述第三互连结构。在一些实施例中，所述衬底通孔具有在所述第一正面上间隔开第一距离并且在所述第一背面上间隔开第二距离的外部侧壁，所述第一距离小于所述第二距离。在一些实施例中，半导体结构还包括：第一背侧接合结构，设置在所述第一半导体衬底的所述第一背面上；以及第三前侧接合结构，设置在所述第三互连结构上方，其中，所述第三前侧接合结构对应于所述第一背侧接合结构，并且通过混合接合而接合至所述第一背侧接合结构。
一些其它实施例涉及方法。在该方法中，在半导体衬底的前侧上形成半导体器件。在半导体衬底的背侧中形成沟槽。在半导体衬底的背侧上的沟槽中交替形成导电层和绝缘层，以建立背侧电容器。在半导体衬底的背侧上形成背侧互连结构以耦接至背侧电容器的电容器电极。在一些实施例中，在所述半导体衬底的所述背侧上的所述沟槽中交替形成导电层和绝缘层包括：形成内衬所述沟槽的第一共形介电层；在所述沟槽中的所述第一共形介电层上方形成第一导电层；在所述沟槽中的所述第一导电层上方形成第二共形介电层；在所述沟槽中的所述第二共形介电层上方形成第二导电层；以及形成至所述第一导电层的第一接触件并且形成至所述第二导电层的第二接触件，其中，所述第一接触件和所述第二接触件对应于背侧沟槽电容器的第一端子和第二端子。在一些实施例中，该方法还包括：将所述半导体衬底接合至至少一个其它半导体衬底以形成三维集成电路。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体结构，包括：
半导体衬底，具有正面和背面；
前侧互连结构，设置在所述正面上方，所述前侧互连结构包括可操作地将设置在所述半导体衬底的正面中或上的半导体器件彼此耦接的多个金属线和通孔；以及
沟槽，设置在所述半导体衬底的所述背面中，所述沟槽在所述沟槽中填充有内部电容器电极、位于所述沟槽中和所述内部电容器电极上面的电容器介电层以及位于所述沟槽中和所述电容器介电层上面的外部电容器电极。
2.根据权利要求1所述的半导体结构，其中，所述沟槽的底面与所述半导体衬底中的半导体晶体管器件的阱区域的底部范围间隔开并且位于所述半导体晶体管器件的阱区域的底部范围正下方。
3.根据权利要求1所述的半导体结构，其中，所述沟槽的底面从所述半导体衬底中的半导体晶体管器件的阱区域横向偏移并且与所述半导体晶体管器件的阱区域垂直重叠。
4.根据权利要求1所述的半导体结构，其中，所述电容器介电层密封所述内部电容器电极的上表面、下表面和侧壁，并且所述外部电容器电极具有与所述沟槽中的所述电容器介电层直接接触的底面和外部侧壁。
5.根据权利要求1所述的半导体结构，其中，所述内部电容器电极延伸出所述沟槽，因此所述内部电容器电极的最外表面与所述电容器介电层的最外表面齐平和/或共面。
6.根据权利要求1所述的半导体结构，还包括：
掺杂区域，内衬所述沟槽的侧壁和所述沟槽的底面，所述掺杂区域与所述外部电容器电极并联电耦接。
7.根据权利要求1所述的半导体结构，其中，所述外部电容器电极具有U形截面。
8.根据权利要求1所述的半导体结构，还包括：
中间电容器电极，设置在所述内部电容器电极和所述外部电容器电极之间的沟槽中。
9.一种半导体结构，包括：
第一半导体衬底，具有第一正面和第一背面；
第二半导体衬底，具有第二正面和第二背面，所述第二半导体衬底设置在所述第一半导体衬底上方；
第一互连结构，设置在所述第一半导体衬底的所述第一正面和所述第二半导体衬底的所述第二正面之间，所述第一互连结构包括可操作地将设置在所述第一半导体衬底的所述第一正面中或上的第一半导体器件彼此耦接的第一多个金属线和通孔；
第二互连结构，设置在所述第一互连结构和所述第二半导体衬底的所述第二正面之间，所述第二互连结构包括可操作地将设置在所述第二半导体衬底的所述第二正面中或上的第二半导体器件彼此耦接的第二多个金属线和通孔；
第一沟槽，设置在所述第一半导体衬底的所述第一背面中，所述第一沟槽填充有第一内部电容器电极、位于所述第一内部电容器电极上面的第一电容器介电层和位于所述第一电容器介电层上面的第一外部电容器电极；以及
第二沟槽，设置在所述第二半导体衬底的所述第二背面中，所述第二沟槽填充有第二内部电容器电极、位于所述第二内部电容器电极上面的第二电容器介电层和位于所述第二电容器介电层上面的第二外部电容器电极。
10.一种形成半导体结构的方法，包括：
在半导体衬底的前侧上形成半导体器件；
在所述半导体衬底的背侧中形成沟槽；
在所述半导体衬底的所述背侧上的所述沟槽中交替形成导电层和绝缘层，以建立背侧电容器；以及
在所述半导体衬底的所述背侧上形成背侧互连结构，以耦接至所述背侧电容器的电容器电极。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114400286A (zh) * 2022-01-14 2022-04-26 成都海威华芯科技有限公司 一种高可靠性通孔电容和制作方法

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109285825B (zh) * 2017-07-21 2021-02-05 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法
US11270988B2 (en) * 2020-01-20 2022-03-08 Monolithic 3D Inc. 3D semiconductor device(s) and structure(s) with electronic control units
US20240096798A1 (en) * 2020-01-20 2024-03-21 Monolithic 3D Inc. 3d semiconductor devices and structures with electronic circuit units
US11488939B2 (en) * 2020-01-20 2022-11-01 Monolithic 3D Inc. 3D semiconductor devices and structures with at least one vertical bus
US11495559B2 (en) * 2020-04-27 2022-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits
US11289455B2 (en) * 2020-06-11 2022-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Backside contact to improve thermal dissipation away from semiconductor devices
KR20220007332A (ko) * 2020-07-10 2022-01-18 삼성전자주식회사 반도체 패키지
US11791332B2 (en) * 2021-02-26 2023-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Stacked semiconductor device and method
US11587901B2 (en) * 2021-03-26 2023-02-21 Nanya Technology Corporation Semiconductor device with redistribution structure and method for fabricating the same
US11973019B2 (en) 2021-05-19 2024-04-30 Qualcomm Incorporated Deep trench capacitors in an inter-layer medium on an interconnect layer of an integrated circuit die and related methods
US11935760B2 (en) * 2021-08-30 2024-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure having thermal dissipation structure therein and manufacturing method thereof
US11676892B2 (en) * 2021-09-15 2023-06-13 International Business Machines Corporation Three-dimensional metal-insulator-metal capacitor embedded in seal structure
US20230260977A1 (en) * 2022-02-17 2023-08-17 Mediatek Inc. Semiconductor packages
JP2024044280A (ja) * 2022-09-21 2024-04-02 ソニーセミコンダクタソリューションズ株式会社 電子デバイスおよび電子デバイスの製造方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060003522A1 (en) * 2004-06-30 2006-01-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device substrate with embedded capacitor
US20070278619A1 (en) * 2006-05-30 2007-12-06 Lawrence Clevenger Semiconductor integrated circuit devices having high-Q wafer back-side capacitors
US20100230735A1 (en) * 2009-03-12 2010-09-16 International Business Machines Corporation Deep Trench Capacitor on Backside of a Semiconductor Substrate
US20110284991A1 (en) * 2010-05-19 2011-11-24 Renesas Electronics Corporation Semiconductor device and method of manufacturing semiconductor device
US20130175666A1 (en) * 2012-01-06 2013-07-11 Maxim Integrated Products, Inc. Semiconductor device having capacitor integrated therein
KR20140075566A (ko) * 2012-12-11 2014-06-19 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 자기 정렬 딥 트렌치 커패시터 및 그 제조 방법
US9331062B1 (en) * 2013-12-06 2016-05-03 Altera Corporation Integrated circuits with backside power delivery
US20170271436A1 (en) * 2016-03-17 2017-09-21 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
KR20190024541A (ko) * 2017-08-31 2019-03-08 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 상호접속 구조물 및 방법

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE427560T1 (de) * 2003-06-20 2009-04-15 Nxp Bv Elektronische vorrichtung, anordnung und verfahren zum herstellen einer elektronischen vorrichtung
AU2006262287A1 (en) * 2005-06-21 2007-01-04 Cardiomems, Inc. Method of manufacturing implantable wireless sensor for in vivo pressure measurement
TWI267190B (en) * 2005-08-29 2006-11-21 Powerchip Semiconductor Corp Semiconductor devices and method for fabricating the same
CN101341576B (zh) * 2005-11-08 2012-05-30 Nxp股份有限公司 超高电容值集成电容器结构
CN100413055C (zh) * 2005-11-30 2008-08-20 中芯国际集成电路制造(上海)有限公司 用于制造集成电路的电容器器件的方法与结构
WO2007131967A1 (en) * 2006-05-15 2007-11-22 Koninklijke Philips Electronics N.V. Integrated low-loss capacitor-arrray structure
US7531407B2 (en) * 2006-07-18 2009-05-12 International Business Machines Corporation Semiconductor integrated circuit devices having high-Q wafer backside inductors and methods of fabricating same
EP3043381B1 (en) * 2007-05-10 2019-05-22 Murata Integrated Passive Solutions Integration substrate with a ultra-high-density capacitor and a through-substrate via
US8008748B2 (en) * 2008-12-23 2011-08-30 International Business Machines Corporation Deep trench varactors
US8693163B2 (en) * 2010-09-01 2014-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Cylindrical embedded capacitors
JP5863381B2 (ja) * 2011-10-17 2016-02-16 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
US9608130B2 (en) * 2011-12-27 2017-03-28 Maxim Integrated Products, Inc. Semiconductor device having trench capacitor structure integrated therein
US9006101B2 (en) * 2012-08-31 2015-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method
US9978829B2 (en) * 2012-11-26 2018-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Low impedance high density deep trench capacitor
US9178080B2 (en) * 2012-11-26 2015-11-03 Taiwan Semiconductor Manufacturing Co., Ltd. Deep trench structure for high density capacitor
JP2014225566A (ja) * 2013-05-16 2014-12-04 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置
US9023688B1 (en) * 2013-06-09 2015-05-05 Monolithic 3D Inc. Method of processing a semiconductor device
JP2015032663A (ja) * 2013-08-01 2015-02-16 株式会社東芝 固体撮像装置
US9818637B2 (en) * 2015-12-29 2017-11-14 Globalfoundries Inc. Device layer transfer with a preserved handle wafer section
US20170186837A1 (en) * 2015-12-29 2017-06-29 Taiwan Semiconductor Manufacturing Co., Ltd. Deep trench capacitor with scallop profile
US10609813B2 (en) * 2016-06-14 2020-03-31 Intel Corporation Capacitive interconnect in a semiconductor package
CN107275315A (zh) * 2017-05-27 2017-10-20 厦门市三安集成电路有限公司 一种化合物半导体背金电容的结构及其制作方法
EP3732784A4 (en) * 2017-12-28 2021-08-11 INTEL Corporation FRONT SYSTEM WITH AN ACOUSTIC WAVE RESONATOR (AWR) ON AN INTERMEDIATE SUBSTRATE
WO2019132925A1 (en) * 2017-12-28 2019-07-04 Intel Corporation Rf front end system with co-integrated acoustic wave resonator
US10879183B2 (en) * 2018-06-22 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US10615248B1 (en) * 2018-09-26 2020-04-07 International Business Machines Corporation On-die capacitor for a VLSI chip with backside metal plates
US10811543B2 (en) * 2018-12-26 2020-10-20 Texas Instruments Incorporated Semiconductor device with deep trench isolation and trench capacitor

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060003522A1 (en) * 2004-06-30 2006-01-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device substrate with embedded capacitor
US20070278619A1 (en) * 2006-05-30 2007-12-06 Lawrence Clevenger Semiconductor integrated circuit devices having high-Q wafer back-side capacitors
US20100230735A1 (en) * 2009-03-12 2010-09-16 International Business Machines Corporation Deep Trench Capacitor on Backside of a Semiconductor Substrate
US20110284991A1 (en) * 2010-05-19 2011-11-24 Renesas Electronics Corporation Semiconductor device and method of manufacturing semiconductor device
US20130175666A1 (en) * 2012-01-06 2013-07-11 Maxim Integrated Products, Inc. Semiconductor device having capacitor integrated therein
KR20140075566A (ko) * 2012-12-11 2014-06-19 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 자기 정렬 딥 트렌치 커패시터 및 그 제조 방법
US9331062B1 (en) * 2013-12-06 2016-05-03 Altera Corporation Integrated circuits with backside power delivery
US20170271436A1 (en) * 2016-03-17 2017-09-21 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
KR20190024541A (ko) * 2017-08-31 2019-03-08 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 상호접속 구조물 및 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114400286A (zh) * 2022-01-14 2022-04-26 成都海威华芯科技有限公司 一种高可靠性通孔电容和制作方法

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