CN101587167A - Multi-functional integrated circuit chip testing machine - Google Patents
Multi-functional integrated circuit chip testing machine Download PDFInfo
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- CN101587167A CN101587167A CNA200910069645XA CN200910069645A CN101587167A CN 101587167 A CN101587167 A CN 101587167A CN A200910069645X A CNA200910069645X A CN A200910069645XA CN 200910069645 A CN200910069645 A CN 200910069645A CN 101587167 A CN101587167 A CN 101587167A
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Abstract
The present invention relates to a kind of multi-functional integrated circuit chip testing machine, comprise casing and inner test machine mainboard, AC signal card group and direct current signal card group thereof, AC signal card group and direct current signal card group interconnect and are installed in respectively on the test machine mainboard, this test machine mainboard is connected with PC controller, chip under test support plate respectively, and its major technique characteristics are: digital-to-analogue chip test card and analog-digital chip test card also are installed on the test machine mainboard.The present invention is reasonable in design, realized test function to the different types of integrated circuit chip, reduced the equipment input of integrated circuit manufacturer, and saved the operation expense of equipment, have that test specification is wide, stable performance, test speed is fast, efficient is high, characteristics such as flexible and convenient to use.
Description
Technical field
The invention belongs to the IC chip test field, especially a kind of multi-functional integrated circuit chip testing machine.
Background technology
The design of integrated circuit, manufacturer are after design, production integrated circuit (IC) chip, usually need to use special-purpose chip testing machine that integrated circuit (IC) chip is tested, to discern the bad sheet line identifier of going forward side by side, has only the integrated circuit (IC) chip sale of just dispatching from the factory by test, then can not dispatch from the factory, for later process production creates conditions by the integrated circuit (IC) chip of test.At present, domestic IC chip test mainly comprises the self testing of IC Chip Production producer and entrusts two kinds of patterns of professional test producer test.Because domestic chip production producer power of test deficiency, professional test producer is rare, makes chip testing become the bottleneck that the segment chip product is in time put on market; Simultaneously, because the chip testing technology requirement is higher relatively, cost is bigger, and the chip design enterprise of specialty generally is not inclined to the testing apparatus of investment buying costliness, makes the test machine of the independent research that cost performance is high, test integrated circuit board demand arise at the historic moment.Continuous development along with science and technology, integrated circuit (IC) chip of a great variety, existing input/output signal all is a kind of integrated circuit (IC) chip of type signal, as digital signal chip and full simulating signal chip, it is the composite signal integrated circuits chip of unlike signal type that input/output signal is also arranged, as be input as digital signal and be output as the integrated circuit (IC) chip of simulating signal, or be input as simulating signal and be output as the integrated circuit (IC) chip of digital signal.The existing chip test machine can only be tested one type integrated circuit (IC) chip usually, and can not polytype integrated circuit (IC) chip be tested, therefore, cause IC Chip Production producer need purchase polytype chip testing machine to satisfy its test needs, this certainly will strengthen the equipment investment of integrated circuit manufacturer, and has increased the operation expense of chip testing machine.
Summary of the invention
Be to overcome the deficiencies in the prior art order of the present invention, a kind of multi-functional integrated circuit chip testing machine is proposed, this chip testing machine can be tested the polytype integrated circuit (IC) chip, has reduced the equipment input of integrated circuit manufacturer, has saved the operation expense of equipment.
The present invention solves its technical matters and takes following technical scheme to realize:
A kind of multi-functional integrated circuit chip testing machine, comprise casing and inner test machine mainboard, AC signal card group and direct current signal card group thereof, AC signal card group and direct current signal card group interconnect and are installed in respectively on the test machine mainboard, this test machine mainboard is connected with PC controller, chip under test support plate respectively, it is characterized in that: digital-to-analogue chip test card and analog-digital chip test card also are installed on the test machine mainboard.
And described AC signal card group comprises main control test storage card, from control test storage card, major clock generating unit card, from the clock generation unit card; Described direct current signal card group comprises simulated cache and Power Supply Monitoring card, device power source power supply unit card, measuring unit card, precision measurement unit card, reference data card.
And described simulated cache and Power Supply Monitoring card also are connected with probe/handle on being arranged on casing by the PHI interface.
And, described digital-to-analogue chip test card is provided with chip test circuit, this circuit comprises the first mainboard interface module, first decoding module, the one FPGA processing module, first configuring chip and analog-to-digital conversion module, the first mainboard interface module is connected with a FPGA processing module by bus, first decoding module is connected between the first mainboard interface module and the FPGA processing module, first configuring chip is connected on the FPGA processing module, the one FPGA processing module is respectively by control end and analog-to-digital conversion module, the chip under test support plate is connected, be connected with the chip under test support plate by digital signal output end, the analog signal output of this chip under test support plate is connected with the input end of analog-to-digital conversion module, the data clock signal of chip under test support plate and status signal are connected with a FPGA processing module respectively, the control end of this analog-to-digital conversion module is connected with the chip under test support plate, and the output terminal of analog-to-digital conversion module is connected with the digital signal input end of a FPGA processing module.
And, described analog-to-digital conversion module is made of 2～8 analog to digital conversion submodules, wherein each analog to digital conversion submodule comprises sampling hold circuit, first differential amplifier, controllable gain amplifier, impact damper, comparer and four tunnel analog/digital signal conversion devices, the input end that the single channel simulating signal of chip under test support plate output and binary channels simulating signal are connected respectively to the sampling hold circuit and first differential amplifier, the output terminal of first differential amplifier is connected with another input end of sampling hold circuit, the gain control signal of the output terminal of sampling hold circuit and fpga chip output is connected respectively to two input ends of controllable gain amplifier, the output terminal of controllable gain amplifier is connected respectively to an input end of three comparers and the input end of impact damper, another input end of three comparers is connected with three reference voltages respectively, the output terminal of the output terminal of impact damper and three comparers is connected respectively on the input end of four tunnel analog/digital signal conversion devices, and the output terminal of this four tunnel analog/digital signal conversion device is exported four way word signals.
And, a described FPGA processing module is made of 2～8 fpga chips, wherein every fpga chip is built-in with MUX, trigger, totalizer, storer, shift register and code translator, three comparison signals that the analog to digital conversion submodule generates are connected to the input end of first MUX and second MUX simultaneously, first MUX, four way word signals of the output terminal of second MUX and the output of analog to digital conversion submodule are connected respectively to the input end of the 3rd MUX, the output terminal of first MUX and second MUX also is connected respectively on first trigger and second trigger, two scopes select signal to be connected respectively to the 3rd trigger, on the 4th trigger, two scopes select signal to be also connected on two input ends of two input ends of code translator and the 4th MUX, the output terminal of four triggers is connected on the first memory, the output terminal of the 3rd MUX is connected to the first input end of first memory and four totalizers simultaneously by shift register, another input end of four totalizers is connected with four output terminals of code translator respectively, four totalizers output terminal be connected respectively on the input end of the 4th MUX, the output terminal of this MUX is connected on the second memory.
And, described analog-digital chip test card is provided with chip test circuit, this circuit comprises the second mainboard interface module, second decoding module, the 2nd FPGA processing module, second configuring chip and D/A converter module, the second mainboard interface module is connected with the 2nd FPGA processing module by bus, second decoding module is connected between the second mainboard interface module and the 2nd FPGA processing module, second configuring chip is connected on the 2nd FPGA processing module, the 2nd FPGA processing module is connected with the input end of D/A converter module by digital signal output end, be connected with the chip under test support plate by control end, the output terminal of D/A converter module is connected with the input end of analog signal of chip under test support plate, and the digital signal output end of chip under test support plate is connected with the digital signal input end of the 2nd FPGA processing module.
And, described the 2nd FPGA processing module is made of 2～8 fpga chips, wherein every fpga chip is built-in with the FPGA interface module, periodic signal generator, memory control module, the storage address generation module, storer, the controlling of sampling module, the chip under test control module, system data is connected with the input end of periodic signal generator and controlling of sampling module respectively by the FPGA interface module, periodic signal generator also is connected with external clock and test card system clock respectively, the output terminal of periodic signal generator is connected respectively to memory control module, the storage address generation module, on the controlling of sampling module, the output terminal of memory control module is connected with the storage address generation module, the output terminal of storage address generation module respectively with the 3rd storer, the 4th storer, the 5th storer and the 6th storer are connected, the 4th storer, the 5th storer and the 6th storer be the output phase signal respectively, high tens word signal reaches low tens word signal and is connected respectively to the input end of the 3rd storer, the output terminal of controlling of sampling module, the test card system clock is connected respectively on the input end of chip under test control module, the control end of chip under test control module and data input pin are connected with the chip under test support plate respectively, and the data output end of chip under test control module is connected with the 7th memory module.
And, described D/A converter module is made of 2～8 digital-to-analog conversion submodules, wherein each digital-to-analog conversion submodule comprises the DAC conversion chip, the current/voltage modular converter, the slender acanthopanax musical instruments used in a Buddhist or Taoist mass, amplifier, eight rank low-pass filters, controllable gain is selected the circuit and second differential amplifier, the input end of two DAC conversion chips is connected with low tens word signal with the high tens word signal of the 2nd FPGA processing module output respectively, the output terminal of the one DAC conversion chip is connected to the first input end of slender acanthopanax musical instruments used in a Buddhist or Taoist mass by the first current/voltage modular converter, the output terminal of the 2nd DAC conversion chip is connected to amplifier input terminal by the second current/voltage modular converter, the output terminal of this amplifier is connected to second input end of slender acanthopanax musical instruments used in a Buddhist or Taoist mass, the output terminal of slender acanthopanax musical instruments used in a Buddhist or Taoist mass is connected with the input end of eight rank low-pass filters, the control signal of the output terminal of eight rank low-pass filters and fpga chip output is connected respectively to two input ends that controllable gain is selected circuit, controllable gain is selected circuit output single channel analog waveform signal, controllable gain selects circuit also to be connected with the input end of second differential amplifier, second differential amplifier output binary channels analog waveform signal.
And the fpga chip in a described FPGA processing module and second processing module all adopts the Virtex-5 family chip of Xilinx, and described first configuring chip and second configuring chip all adopt the XCF08P chip of Xilinx; The described first mainboard interface module and the second mainboard interface module are the interface of the connector formation of four 4 * 48 pins.
Advantage of the present invention and good effect are:
1, this chip testing machine has been installed analog-digital chip test card and digital-to-analogue chip test card in the existing chip test machine, increased test function to analog and digital mixed signal chip and digital and analog mixed signal chip, the test specification and the function of chip testing machine have been enlarged, use a chip testing machine just can finish test function, reduced the equipment input of integrated circuit manufacturer the number of different types integrated circuit (IC) chip.
2, two of this chip testing machine test cards all adopt modular design, combination by FPGA processing module and analog-to-digital conversion module or D/A converter module, realization is to the test function of digital simulation mixed signal chip and analog and digital mixed signal chip, owing to adopt processing module, have characteristics such as processing speed is fast, stable performance based on the FPGA technology.
3, this chip testing machine adopts different test cards respectively to the test function of analog and digital mixed signal chip and digital and analog mixed signal chip, therefore, can also carry out different installations as required and be configured to realize different functions, have characteristics such as reasonable in design, that flexible configuration is convenient, simultaneously, be convenient to the operation maintenance of test machine, saved the operation expense of equipment.
4, the chip test card of this chip testing machine can provide test function to a plurality of chips simultaneously, has improved the testing efficiency of chip testing machine.
5. the present invention is reasonable in design, realized test function to the different types of integrated circuit chip, reduced the equipment input of integrated circuit manufacturer, saved the operation expense of equipment, had that test specification is wide, stable performance, test speed is fast, efficient is high, characteristics such as flexible and convenient to use.
Description of drawings
Fig. 1 is the schematic block circuit diagram of test machine;
Fig. 2 is the schematic block circuit diagram of digital-to-analogue chip test card;
Fig. 3 is the schematic block circuit diagram of the analog to digital conversion submodule on the digital-to-analogue chip test card;
Fig. 4 is the built-in schematic block circuit diagram of the fpga chip on the digital-to-analogue chip test card;
Fig. 5 is the schematic block circuit diagram of analog-digital chip test card;
Fig. 6 is the built-in schematic block circuit diagram of the fpga chip on the analog-digital chip test card;
Fig. 7 is the schematic block circuit diagram of the digital-to-analog conversion submodule on the analog-digital chip test card.
Embodiment
Below in conjunction with accompanying drawing the embodiment of the invention is further described.
A kind of multi-functional integrated circuit chip testing machine, comprise a casing, test machine mainboard, AC signal card group, direct current signal card group are installed in casing, AC signal card group and direct current signal card group interconnect and are installed in respectively on the test machine mainboard, as shown in Figure 1, AC signal card group comprises main control test storage card, from control test storage card, major clock generating unit card, from the clock generation unit card, above-mentioned AC signal integrated circuit board is installed in respectively on the test machine mainboard; Direct current signal card group comprises simulated cache and Power Supply Monitoring card, device power source power supply unit card, measuring unit card, precision measurement unit card, reference data card, and above-mentioned direct current signal integrated circuit board is installed in respectively on the test machine mainboard; The test machine mainboard is connected with the PC controller by scsi interface, chip testing machine is realized the test to integrated circuit (IC) chip under the control of PC controller, the test machine mainboard also is connected with the chip under test support plate, chip under test places on the chip under test support plate and finishes test by chip testing machine, simulated cache and Power Supply Monitoring card also are connected with probe/handle on being arranged on casing by the PHI interface, are used to test the chip wafer that does not encapsulate.
Main control test storage card in the AC signal card group/from control test storage card (MCNTM/SCNTM) and major clock generating unit/from clock generation unit (MTGFR/STGFR) configuration in pairs, can form independently 32 AC signal resource, wherein main control test storage card/provide the model or the vectorial resources of 32 test positions from control test storage card (MCNTM/SCNTM), 1 main control test storage card (MCNTM) and 3 are from control test storage card (SCNTM) composition 128 bit test systems; Major clock generating unit/provide the clock resources of 32 test positions from clock generation unit (MTGFR/STGFR), 1 clock generation unit (MTGFR) and 3 are from clock generation unit (STGFR) composition 128 bit test systems.
The major function of simulated cache in the direct current signal card group and Power Supply Monitoring card (ABPTM) is that AC power is controlled, and can drive 128 or 256 relays, by the PHI interface circuit test machine and probe/handle is coupled together; Precision measurement unit card (PMUFP) major function is measuring voltage and electric current, comprises two kinds of test patterns clamping down on electric current/measuring voltage and clamp down on voltage/measurement electric current, and its voltage-measurable scope is ± 32V that range of current is ± 400mA; The circuit of device power source power supply unit card (DSPFP) and precision measurement unit card (PMUFP) are similar, and its measure portion is finished by measuring unit card (AMEFP), and its voltage-measurable scope is ± 32V that range of current is ± 1A; Measuring unit card (AMEFP) is included as normal voltage and resistance circuit, the measuring unit circuit of power supply power supply unit card (DSPFP) and the measuring unit circuit and the optional matrix relay of measuring unit card (AMEFP) that calibration provides, and it adopts 14 analog to digital converter to be used for measuring unit; Reference data card (LREF) provides the reference voltage of reference for other each integrated circuit boards.
Above-mentioned AC signal card and direct current signal card are installed in the test function that realizes chip testing machine on the test machine mainboard.This test machine course of work is: the alternating current that the direct current signal card provides the outside be converted to inner required various direct supply ± 5V, ± 12, ± 15, ± 48 etc., the order that provides by software loads each power supply, loading+5V at first, detect fan and power by simulated cache and Power Supply Monitoring card (ABPTM) to integrated circuit board, if after normal, load other power supplys and also must monitor simultaneously by simulated cache and Power Supply Monitoring card (ABPTM).All be connected under the correct situation with support plate and motherboard in detected element, the PC controller is transferred to main control test storage card chip testing machine on/from control test storage card (MCNTM/SCNTM) and major clock generating unit/from clock generation unit function cards such as (MTGFR/STGFRs) with address and data through scsi interface by software operation, carry out the test of every voltage and electric current by measuring unit and precision measurement unit card, after test is finished, test data is fed back to the PC controller carry out various processing, finally by PC controller output chart or data.
Innovative point of the present invention is: digital-to-analogue chip test card and analog-digital chip test card also are installed on the test machine mainboard, realize the test function to digital simulation mixed signal chip and analog and digital mixed signal chip respectively.Logarithmic mode chip test card and analog-digital chip test card are introduced respectively below:
1, digital-to-analogue chip test card
On the given figure core rod built-in testing card chip test circuit is installed, as shown in Figure 2, this chip test circuit comprises the first mainboard interface module, first decoding module, a FPGA processing module, first configuring chip and analog-to-digital conversion module.The first mainboard interface module is passed through data bus, control bus and address bus are connected with a FPGA processing module, first decoding module is connected between the first mainboard interface module and the FPGA processing module, first configuring chip is connected on the FPGA processing module, the one FPGA processing module is respectively by control end and analog-to-digital conversion module, the chip under test support plate is connected, realization is to the control function of analog-to-digital conversion module and chip under test support plate, the one FPGA processing module is connected with the chip under test support plate by digital signal output end, and a FPGA processing module produces the needed digital signal of chip under test automatically and outputs on the chip under test; The analog signal output of chip under test support plate is connected with the input end of analog-to-digital conversion module, chip under test is handled back output simulating signal to the digital signal of FPGA input, this simulating signal is fed on the analog-to-digital conversion module, the data clock signal of chip under test support plate and status signal are connected with a FPGA processing module respectively, satisfy the needs that a FPGA processing module is handled; The control end of analog-to-digital conversion module is connected with the chip under test support plate, the digital signal of analog-to-digital conversion module output is connected with the digital signal input end of a FPGA processing module, the analog signal conversion that analog-to-digital conversion module transmits chip under test is that digital signal is sent into a FPGA processing module, the one FPGA processing module is handled and is stored the digital signal that receives, at last send into to judge on the test machine mainboard whether its signal is correct output signal, thereby realized the test of digital and analog mixed signal chip by the first mainboard interface module.
FPGA processing module in the chip test circuit comprises one group of fpga chip, and the quantity of this group fpga chip can be 2～8, and simultaneously, analog-to-digital conversion module is made of 2～8 analog to digital conversion submodules.Owing to there is a polylith fpga chip, therefore link address first decoding module between the fpga chip and the first mainboard interface module is to select fpga chip.In the present embodiment, in the present embodiment, fpga chip is 4, the quantity of analog to digital conversion submodule is 4, what fpga chip adopted is the XC5VLX30 chip of the Virtex-5 of Xilinx company family chip, and that first configuring chip adopts is the personality PROM chip XCF08P of Xilinx company, can be with 4 fpga chips and its parallel linking together by this first configuring chip, be provided with programming data in first configuring chip, the back of having realized powering on is the function of fpga chip loading procedure.
The first mainboard interface module in the chip test circuit adopts the connector of four 4X48 (each is 192 pins) as connecting interface, and the digital-to-analogue chip test card adopts is that the male and female connector of 4 pairs 192 pins is as interface.The effect of this first mainboard interface module is that test machine mainboard and chip test card are set up a kind of connected mode, can will be incorporated into data, address and control signal on the corresponding module of this chip test circuit from the test machine mainboard by this first mainboard interface module.First decoding module is to select corresponding fpga chip according to address signal, this first mainboard interface module on the one hand can be with data transfer to test card and FPGA inside thereof, can be delivered to the digital signal that test card returns again on the test machine mainboard by the first mainboard interface module on the other hand, finish the transmitted in both directions of data.Control signal changes read-write and the function of reset that goes to control each module through corresponding logic on test card.
Analog to digital conversion submodule in the analog-to-digital conversion module comprises sampling hold circuit, first differential amplifier, controllable gain amplifier, impact damper, comparer and four tunnel analog/digital signal conversion devices, as shown in Figure 3, the input end that the single channel simulating signal of chip under test support plate output and binary channels simulating signal are connected respectively to the sampling hold circuit and first differential amplifier, the output terminal of first differential amplifier is connected with another input end of sampling hold circuit, the gain control signal of the output terminal of sampling hold circuit and fpga chip output is connected respectively to two input ends of controllable gain amplifier, the output terminal of controllable gain amplifier is connected respectively to an input end of three comparers and the input end of impact damper, another input end of three comparers is connected with three reference voltages respectively, and three reference voltages are respectively 1.25V, 3.75V, 5V.The output terminal of the output terminal of impact damper and three comparers is connected respectively on the input end of four tunnel analog/digital signal conversion devices that are made of the AD7980 chip, and four way word signals of this four tunnel analog/digital signal conversion device output are imported as fpga chip.Analog-to-digital conversion module receives single channel simulating signal and the binary channels simulating signal (differential signal) that comes from the output of chip under test support plate, samples, keeps, relatively amplifies and analog to digital conversion a series of processing such as (A/D).Wherein the effect of sampling hold circuit is to be used for grasping analog voltage signal, and this voltage is kept a period of time, can move normally so that guarantee follow-up signal processing.Three comparers are used to receive the resulting voltage signal of sampling hold circuit, reference voltage according to three comparers carries out the judgement of voltage range to this voltage signal, and according to voltage range generation comparison signal 1, comparison signal 2, comparison signal 3, these three comparison signals connect four tunnel analog/digital signal conversion devices of back, be used for controlling the analog/digital signal conversion device path operate as normal of relevant voltage scope, and read back into fpga chip.The function of four tunnel analog/digital signal conversion devices is that the voltage signal that will obtain before this carries out digitizing, and sends the digital signal that obtains to fpga chip.
Fpga chip in the one FPGA processing module is built-in with MUX, trigger, totalizer, storer, shift register and code translator, as shown in Figure 4, three comparison signals that the analog to digital conversion submodule generates are connected to the input end of first MUX and second MUX simultaneously, first MUX, four way word signals of the output terminal of second MUX and the output of analog to digital conversion submodule are connected respectively to the input end of the 3rd MUX, the output terminal of first MUX and second MUX also is connected respectively on first trigger and second trigger, two scopes select signal to be connected respectively to the 3rd trigger, on the 4th trigger, two scopes select signal to be also connected on two input ends of two input ends of code translator and the 4th MUX, the output terminal of four triggers is connected on the first memory, the output terminal of the 3rd MUX is connected to the first input end of first memory and four totalizers simultaneously by shift register, another input end of four totalizers is connected with four output terminals of code translator respectively, four totalizers output terminal be connected respectively on the input end of the 4th MUX, the output terminal of this MUX is connected on the second memory.Fpga chip is connected with the analog to digital conversion submodule, three comparison signals by analog-to-digital conversion module output: comparison signal 1, comparison signal 2, comparison signal 3 are as the selection input signal of first via MUX, second MUX, the output signal of above-mentioned two MUX and four tunnel output digital signals are used to select wherein one tunnel digital input signals as fpga chip respectively as the selection signal and the data input signal of the 3rd MUX.The output signal of the 3rd MUX is the digital signal of 1bit, this signal is saved in the first memory through the string of shift register and the digital signal that is converted to 16bit, and the output signal of first MUX and second MUX is saved in the first memory in the lump with two scopes selection signals.The data area that store in the first memory this moment is 0～5V, and the range of waveforms of our reality is 0～10V, needs to realize real level value through addition.We need four totalizers, the level range of representative is respectively 0～2.5V, 2.5V～5.0V, 5.0V～7.5V, 7.5V～10V, and one tunnel input of four totalizers is the data-signal of reading in the shift register, another road is respectively the 0V level of binary data representative, 2.5V level, 5.0V level, 7.5V level.Scope selects signal 1, scope to select signal 2 to select output by code translator, enables the totalizer work of relevant voltage scope thus, makes the data and the relevant voltage addition of shift register output.The output signal of each totalizer is all as the data input signal of the 4th MUX, and by scope selection signal 1,2 selection positions as the 4th MUX, make it be output as the output data of the totalizer of corresponding voltage scope, and be saved in second memory, such as: when scope is selected signal 1, it is 00 o'clock that scope is selected signal 2, promptly selected the scope of 0～2.5V, then first adder work, will be from the data of shift register input and the digitalized data addition of reference voltage, and the output of the 4th MUX is the output data of first adder, and preserve these data in second memory, by that analogy.Realized that finally a series of 1bit digital signals by mimic channel output are converted to the voltage digital signal of parallel representative reality.Digital signal in the storer can be sent on the test machine mainboard by the first mainboard interface module, is used to verify whether chip under test work is normal.
The principle of work of digital and analog mixed signal chip test card is: after certain piece fpga chip or the selected work simultaneously of 4 fpga chips, the test machine mainboard by the first mainboard interface module to relevant data, address of fpga chip input and control signal such as reset.Fpga chip begins computing work, and to chip under test input control signal and digital signal, chip under test is worked under the control of control signal, and chip under test is converted to the corresponding simulating signal with the digital signal that receives, and outputs to analog-to-digital conversion module.Fpga chip sends control signal to analog-to-digital conversion module, makes analog-to-digital conversion module work, and the ADC chip of analog-to-digital conversion module is imported required control signal simultaneously.Analog-to-digital conversion module is realized analog-digital conversion function, the analog waveform of chip under test output is converted to digital signal and sends fpga chip to, inter-process through fpga chip transfers back to the test machine mainboard to corresponding parallel data, this test machine mainboard compares computing to digital signal of reading back and the initial digital signal that sends, judge whether chip under test works correctly, and whether chip performance meets the demands.
2, analog-digital chip test card
On this analog-digital chip test card chip test circuit is installed, as shown in Figure 5, this chip test circuit comprises the second mainboard interface module, second decoding module, the 2nd FPGA processing module, second configuring chip and D/A converter module.The second mainboard interface module is connected with the 2nd FPGA processing module by data bus, control bus and address bus, second decoding module is connected between the second mainboard interface module and the 2nd FPGA processing module, second configuring chip is connected on the 2nd FPGA processing module, and the second mainboard interface module is connected with the 2nd FPGA processing module by data bus, control bus and address bus; The 2nd FPGA processing module is connected with the input end of D/A converter module by digital signal output end, can send the digital signal that the 2nd FPGA processing module produces to D/A converter module, the 2nd FPGA processing module is connected with the chip under test support plate by control end, the output terminal of D/A converter module is connected with the input end of analog signal of chip under test support plate, the analog signal waveform of its generation can be sent on the chip under test on the chip under test support plate, chip under test is carried out function corresponding and is handled under the control of the control signal of the 2nd FPGA processing module; The digital signal output end of chip under test support plate is connected with the digital signal input end of the 2nd FPGA processing module, the chip under test support plate can feed back to the chip under test execution result the 2nd FPGA processing module, the 2nd FPGA processing module is handled the digital signal that receives and store, at last send into to judge on the test machine mainboard whether its signal is correct output signal, thereby realized test the analog and digital mixed signal chip by the second mainboard interface module.
The 2nd FPGA processing module in the chip test circuit comprises one group of fpga chip, and the quantity of this group fpga chip is 2～8, and simultaneously, D/A converter module is made of 2～8 digital-to-analog conversion submodules.Owing to there is a polylith fpga chip, therefore between fpga chip and the second mainboard interface module, be connected second address, second decoding module, fpga chip is selected.In the present embodiment, fpga chip is 4, and the quantity of digital-to-analog conversion submodule is 4.What fpga chip adopted is the XC5VLX30 chip of the Virtex-5 of Xilinx company family chip, that described second configuring chip adopts is the personality PROM chip XCF08P of Xilinx company, can be by this second configuring chip with 4 FPGA and its parallel linking together, be provided with programming data in second configuring chip, the back of having realized powering on is the function of fpga chip loading procedure.
The second mainboard interface module in the chip test circuit adopts the connector of four 4X48 (each is 192 pins) as connecting interface, and this chip test card adopts is that the male and female connector of 4 pairs 192 pins is as interface.The effect of the second mainboard interface module is that test machine mainboard and analog-digital chip test card are set up a kind of connected mode, can be incorporated into data, address and control signal on the corresponding module of this chip test circuit from the test machine mainboard by this second mainboard interface module.Second decoding module is to select corresponding fpga chip according to address signal, this second mainboard interface module on the one hand can be with data transfer to test card and fpga chip inside thereof, on the other hand the data that can return the analog-digital chip test card by the second mainboard interface module again loopback give on the test machine mainboard, finish the transmitted in both directions of data.Control signal changes read-write and the function of reset that goes to control each module through corresponding logic on chip test card.
Fpga chip in the 2nd FPGA processing module adopts modular design, and its function is to make the waveform of user with the numerical coding formal definition, and in a programmable time interval it is outputed on the D/A converter module.This fpga chip is built-in with the FPGA interface module, periodic signal generator, memory control module, the storage address generation module, storer, the controlling of sampling module, the chip under test control module, as shown in Figure 6, system data is connected with the input end of periodic signal generator and controlling of sampling module respectively by the FPGA interface module, periodic signal generator also is connected with external clock and test card system clock respectively, the output terminal of periodic signal generator is connected respectively to memory control module, the storage address generation module, on the controlling of sampling module, the output terminal of memory control module is connected with the storage address generation module, the output terminal of storage address generation module respectively with the 3rd storer, the 4th storer, the 5th storer and the 6th storer are connected, the 4th storer, the 5th storer and the 6th storer output phase signal (phase place indicates and the phasing degree) and high tens word signal, low tens word signal, high tens word signal is the high position data of two tens word signals, low tens word signal is the low data of two tens word signals, the 4th, five, the output terminal of six storeies is connected with the input end of the 3rd storer, by the 3rd memory recording picture recording position signal and high tens word signal, low tens word signal, the output terminal of controlling of sampling module, the test card system clock is connected respectively on the input end of chip under test control module, the control end of chip under test control module and data input pin are connected with the chip under test support plate respectively, and the data output end of chip under test control module is connected with the 7th memory module.
In the present embodiment, the system clock frequency of fpga chip is 100MHz, and maximum sampled point is 3600.Fpga chip to the requirement of output waveform is: the audio frequency coverage is 50Hz to 20KHz, the signal amplitude scope is 0～+ 10V or-5V～+ waveform able to programme of 5V, the user can (sine wave, triangular wave, square wave) select one or a self-defined waveform from three predetermined waveform.Periodic signal generation module comprises one 12 register, storing the cycle that in system's allowed band, defines by the user, the reference clock of periodic signal generator input can be the system clock of test card, it also can be the clock that system's external clock reference provides, as the clock signal of storage address maker and controlling of sampling module, its clock is 50MHz to the maximum.The controlling of sampling module is made up of the register sum counter of several 12bits, stored the sampling number of user-defined phase weekly in the above-mentioned register, in the present embodiment, the maximum sampling number that allows is 3600 sampled points, the user can also select the periodicity of sampling, and stops sampling behind the one-period of promptly sampling or stops at several all after dates.Because the stability that D/A changes is considered in the delay of linear circuit, the duration between the sampled point is greater than 500ns, and therefore maximum sampling rate is 2MS/s.Fpga chip is except 20 position digital signals of D/A converter module are sent in generation, also export the control signal of a series of control chip under test operations simultaneously to the chip under test support plate, for example TRIG, SCLK, CNV, N_CS, wherein CNV can programme according to the difference of test chip, breadth extreme is 327.68us, SCLK is 20ns, and TRIG is 10ns, and N_CS (chip selection signal) can programme according to the dissimilar of test chip; Fpga chip is exported 20 position digital signals by the 5th, the 6th storer, is sent to D/A converter module conversion; The marking signal (PHASE MKR) of the 4th storer output can be used as the trigger pip of external digital logic, and the 4th storer is also exported the phase angles data of 15bits.Fpga chip can be stored to the chip under test feedback data in the 7th storer by the chip under test control module, at last send into to judge on the test machine mainboard whether its signal is correct output signal, thereby realized the test of analog and digital mixed signal chip by the second mainboard interface module.
Digital-to-analog conversion submodule in the D/A converter module comprises the DAC conversion chip, the current/voltage modular converter, the slender acanthopanax musical instruments used in a Buddhist or Taoist mass, amplifier, eight rank low-pass filters, controllable gain is selected the circuit and second differential amplifier, as shown in Figure 7, in the present embodiment, the DAC conversion chip is 16 figure place mould conversion chip DAC16, in order to realize 20 digital-to-analog conversion, therefore need two DAC16 chips, the input end of the one DAC conversion chip and the 2nd DAC conversion chip is connected with low tens word signal (PLSB) with the high tens word signal (PMSB) of fpga chip output respectively, the output terminal of the one DAC conversion chip is connected to the first input end of slender acanthopanax musical instruments used in a Buddhist or Taoist mass by the first current/voltage modular converter, the output terminal of the 2nd DAC conversion chip is connected to the second current/voltage modular converter, above-mentioned two current/voltage modular converters are formed by the AD829 chip, the output terminal of the second current/voltage modular converter is connected to amplifier input terminal, the output terminal of this amplifier is connected to second input end of slender acanthopanax musical instruments used in a Buddhist or Taoist mass, the output terminal of this slender acanthopanax musical instruments used in a Buddhist or Taoist mass is connected with the input end of eight rank low-pass filters, the control signal of the output terminal of eight rank low-pass filters and fpga chip output is connected respectively to two input ends that controllable gain is selected circuit, controllable gain is selected the adjustable single channel analog waveform signal of circuit output gain, and this controllable gain selects circuit also to be connected the binary channels analog waveform signal that output gain is adjustable with the input end of second differential amplifier.
In the present embodiment, the digital-to-analog conversion submodule has used two DAC16 chips in order to realize 20 digital-to-analog conversion, among every DAC16 10 respectively as the Gao Shiwei of data with low ten, wherein low 10 transformation result needs to dwindle circuit through one by what amplifier was formed, 10 voltages that obtain dwindle suitable multiple and high 10 voltages that obtain carry out addition with hanging down, and form 20 complete D/A change-over circuits.From the simulating signal of slender acanthopanax musical instruments used in a Buddhist or Taoist mass output is not level and smooth waveform signal, has wherein carried a lot of high-frequency harmonics secretly, for maximum filtering higher hamonic wave, has added one group of eight rank low-pass filter in the back of slender acanthopanax musical instruments used in a Buddhist or Taoist mass.It is the amplitude that is used for controlling output waveform that controllable gain is selected circuit, to reach the requirement of chip under test to the input waveform signal.Along with the high speed of signal, disturb increasing chip under test to select the difference input pattern in order to reduce, so added one second differential amplifier module in circuit, this module can convert mono signal to differential signal.Waveform signal is through after the above a series of processing, can export the static direct current error for+/-2LSB, THD (total harmonic distortion) be less than the accurate analog waveform of-100dB, afterwards as the reference waveform input of chip under test.
The principle of work of analog-digital chip test card is: this chip test circuit inputs to corresponding the 2nd FPGA processing module by address, data and control signal on the second mainboard interface module acceptance test machine mainboard respectively again by second decoding module.The independently crystal oscillating circuit that this chip test card is provided with can produce the test card system clock respectively, according to the requirement that produces waveform, need earlier the data-carrier store inside the fpga chip to be carried out write operation, level numerical value and corresponding phase data after making it store required waveform quantization, promptly in the amplitude of known expection waveform, under the prerequisites such as frequency, waveform is quantized, point of quantification is 3600, the waveform of one-period is divided into 3600 parts by frequency, each some corresponding quantitative amplitude and phase place is stored in the data-carrier store of fpga chip (the 5th storer and the 6th storer).After the work that writes of fpga chip is finished, sampling and output continuous wave can have been begun, by the controlling of sampling circuit output sampling control signal of fpga chip (the phase sampled point is no more than 3600 weekly, and sampling interval is greater than 500ns).The chip under test control circuit of fpga chip can produce control signal and clock, be used to control the chip under test work on the chip under test support plate, and produce the read back clock signal and the control signal of reading back, the digital signal of chip under test output is used to read back, at last by the second mainboard interface module this digital signal being sent on the test machine mainboard numerical coding value that the sampled point with the first calculated waveform obtains compares, if judge consistent, illustrate that chip under test is specification product, if inconsistent, thereby illustrate that chip under test is that substandard product has been realized the test to the analog and digital mixed signal chip.
It is emphasized that; embodiment of the present invention is illustrative; rather than it is determinate; therefore the present invention is not limited to the embodiment described in the embodiment; every other embodiments that drawn by those skilled in the art's technical scheme according to the present invention belong to the scope of protection of the invention equally.
Claims (10)
1, a kind of multi-functional integrated circuit chip testing machine, comprise casing and inner test machine mainboard, AC signal card group and direct current signal card group thereof, AC signal card group and direct current signal card group interconnect and are installed in respectively on the test machine mainboard, this test machine mainboard is connected with PC controller, chip under test support plate respectively, it is characterized in that: digital-to-analogue chip test card and analog-digital chip test card also are installed on the test machine mainboard.
2, multi-functional integrated circuit chip testing machine according to claim 1 is characterized in that: described AC signal card group comprises main control test storage card, from control test storage card, major clock generating unit card, from the clock generation unit card; Described direct current signal card group comprises simulated cache and Power Supply Monitoring card, device power source power supply unit card, measuring unit card, precision measurement unit card, reference data card.
3. multi-functional integrated circuit chip testing machine according to claim 2 is characterized in that: described simulated cache and Power Supply Monitoring card also are connected with probe/handle on being arranged on casing by the PHI interface.
4, multi-functional integrated circuit chip testing machine according to claim 1, it is characterized in that: described digital-to-analogue chip test card is provided with chip test circuit, this circuit comprises the first mainboard interface module, first decoding module, the one FPGA processing module, first configuring chip and analog-to-digital conversion module, the first mainboard interface module is connected with a FPGA processing module by bus, first decoding module is connected between the first mainboard interface module and the FPGA processing module, first configuring chip is connected on the FPGA processing module, the one FPGA processing module is respectively by control end and analog-to-digital conversion module, the chip under test support plate is connected, be connected with the chip under test support plate by digital signal output end, the analog signal output of this chip under test support plate is connected with the input end of analog-to-digital conversion module, the data clock signal of chip under test support plate and status signal are connected with a FPGA processing module respectively, the control end of this analog-to-digital conversion module is connected with the chip under test support plate, and the output terminal of analog-to-digital conversion module is connected with the digital signal input end of a FPGA processing module.
5, multi-functional integrated circuit chip testing machine according to claim 4, it is characterized in that: described analog-to-digital conversion module is made of 2～8 analog to digital conversion submodules, wherein each analog to digital conversion submodule comprises sampling hold circuit, first differential amplifier, controllable gain amplifier, impact damper, comparer and four tunnel analog/digital signal conversion devices, the input end that the single channel simulating signal of chip under test support plate output and binary channels simulating signal are connected respectively to the sampling hold circuit and first differential amplifier, the output terminal of first differential amplifier is connected with another input end of sampling hold circuit, the gain control signal of the output terminal of sampling hold circuit and fpga chip output is connected respectively to two input ends of controllable gain amplifier, the output terminal of controllable gain amplifier is connected respectively to an input end of three comparers and the input end of impact damper, another input end of three comparers is connected with three reference voltages respectively, the output terminal of the output terminal of impact damper and three comparers is connected respectively on the input end of four tunnel analog/digital signal conversion devices, and the output terminal of this four tunnel analog/digital signal conversion device is exported four way word signals.
6, multi-functional integrated circuit chip testing machine according to claim 4, it is characterized in that: a described FPGA processing module is made of 2～8 fpga chips, wherein every fpga chip is built-in with MUX, trigger, totalizer, storer, shift register and code translator, three comparison signals that the analog to digital conversion submodule generates are connected to the input end of first MUX and second MUX simultaneously, first MUX, four way word signals of the output terminal of second MUX and the output of analog to digital conversion submodule are connected respectively to the input end of the 3rd MUX, the output terminal of first MUX and second MUX also is connected respectively on first trigger and second trigger, two scopes select signal to be connected respectively to the 3rd trigger, on the 4th trigger, two scopes select signal to be also connected on two input ends of two input ends of code translator and the 4th MUX, the output terminal of four triggers is connected on the first memory, the output terminal of the 3rd MUX is connected to the first input end of first memory and four totalizers simultaneously by shift register, another input end of four totalizers is connected with four output terminals of code translator respectively, four totalizers output terminal be connected respectively on the input end of the 4th MUX, the output terminal of this MUX is connected on the second memory.
7, multi-functional integrated circuit chip testing machine according to claim 1, it is characterized in that: described analog-digital chip test card is provided with chip test circuit, this circuit comprises the second mainboard interface module, second decoding module, the 2nd FPGA processing module, second configuring chip and D/A converter module, the second mainboard interface module is connected with the 2nd FPGA processing module by bus, second decoding module is connected between the second mainboard interface module and the 2nd FPGA processing module, second configuring chip is connected on the 2nd FPGA processing module, the 2nd FPGA processing module is connected with the input end of D/A converter module by digital signal output end, be connected with the chip under test support plate by control end, the output terminal of D/A converter module is connected with the input end of analog signal of chip under test support plate, and the digital signal output end of chip under test support plate is connected with the digital signal input end of the 2nd FPGA processing module.
8, multi-functional integrated circuit chip testing machine according to claim 7, it is characterized in that: described the 2nd FPGA processing module is made of 2～8 fpga chips, wherein every fpga chip is built-in with the FPGA interface module, periodic signal generator, memory control module, the storage address generation module, storer, the controlling of sampling module, the chip under test control module, system data is connected with the input end of periodic signal generator and controlling of sampling module respectively by the FPGA interface module, periodic signal generator also is connected with external clock and test card system clock respectively, the output terminal of periodic signal generator is connected respectively to memory control module, the storage address generation module, on the controlling of sampling module, the output terminal of memory control module is connected with the storage address generation module, the output terminal of storage address generation module respectively with the 3rd storer, the 4th storer, the 5th storer and the 6th storer are connected, the 4th storer, the 5th storer and the 6th storer be the output phase signal respectively, high tens word signal reaches low tens word signal and is connected respectively to the input end of the 3rd storer, the output terminal of controlling of sampling module, the test card system clock is connected respectively on the input end of chip under test control module, the control end of chip under test control module and data input pin are connected with the chip under test support plate respectively, and the data output end of chip under test control module is connected with the 7th memory module.
9, multi-functional integrated circuit chip testing machine according to claim 7, it is characterized in that: described D/A converter module is made of 2～8 digital-to-analog conversion submodules, wherein each digital-to-analog conversion submodule comprises the DAC conversion chip, the current/voltage modular converter, the slender acanthopanax musical instruments used in a Buddhist or Taoist mass, amplifier, eight rank low-pass filters, controllable gain is selected the circuit and second differential amplifier, the input end of two DAC conversion chips is connected with low tens word signal with the high tens word signal of the 2nd FPGA processing module output respectively, the output terminal of the one DAC conversion chip is connected to the first input end of slender acanthopanax musical instruments used in a Buddhist or Taoist mass by the first current/voltage modular converter, the output terminal of the 2nd DAC conversion chip is connected to amplifier input terminal by the second current/voltage modular converter, the output terminal of this amplifier is connected to second input end of slender acanthopanax musical instruments used in a Buddhist or Taoist mass, the output terminal of slender acanthopanax musical instruments used in a Buddhist or Taoist mass is connected with the input end of eight rank low-pass filters, the control signal of the output terminal of eight rank low-pass filters and fpga chip output is connected respectively to two input ends that controllable gain is selected circuit, controllable gain is selected circuit output single channel analog waveform signal, controllable gain selects circuit also to be connected with the input end of second differential amplifier, second differential amplifier output binary channels analog waveform signal.
10, according to claim 6 or 8 described multi-functional integrated circuit chip testing machines, it is characterized in that: the fpga chip in a described FPGA processing module and second processing module all adopts the Virtex-5 family chip of Xilinx, and described first configuring chip and second configuring chip all adopt the XCF08P chip of Xilinx; The described first mainboard interface module and the second mainboard interface module are the interface of the connector formation of four 4 * 48 pins.
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