CN110658447A - A kind of relay life detection method - Google Patents

Abstract

A relay life detection method is realized by a device including a controller unit, L on-off counting units, a man-machine interface unit, a relay drive unit, and an oscillator unit, and can simultaneously count the on-off times of a plurality of relay switches. Obtain the on-off count value, and judge whether the relay and its switch fail according to the on-off count value; the anti-pulse interference circuit in the on-off count unit can filter out the edge jitter interference and narrow pulse interference in the count pulse, ensuring the life of the relay. Accuracy of detection; multiple counters are set outside the controller unit to count the on-off times of the relay switches respectively. At the same time, the number of relay switches to detect the life of the relay is not limited by the number of counters inside the controller unit.

Description

A kind of relay life detection method

The patent application of the present invention is a divisional application, the original application number is 201711133937.6, the application date is November 16, 2017, and the name of the invention is a relay life detection device.

technical field

The invention relates to the field of testing methods and devices, in particular to a relay life detection method.

Background technique

The life of the relay is generally tens of thousands to hundreds of thousands of times. Simulate the use conditions of the relay, by controlling the action of the relay to make the switch on and off to generate electric pulses, and then counting the electric pulses, the life of the relay can be tested. The electrical pulses generated by the relay action contain edge jitter, and directly counting the unprocessed pulses will cause great errors. Use the MCU software delay method to remove the influence of the jitter pulse. When the MCU needs to test the life of multiple relay switches at the same time, the MCU software delay method will make the MCU powerless.

SUMMARY OF THE INVENTION

In order to solve the above problems, the present invention provides a relay life detection method, including:

Step 1, initialization, including setting the detection flags of the L relay switches to the detection state, clearing the life counter to 0, and sending a clearing signal to clear all the L on-off count values to 0;

Step 2: Control the on-off times of the L relay switches once, and simultaneously count the on-off times of the L relay switches to obtain L on-off count values; the life counter adds 1 to count;

Step 3, read the current L on-off count values;

Step 4: Judging whether the relay switch whose detection flag is in the state of inspection is invalid one by one; the detection flag of the relay switch which is judged to be invalid this time is set to the state of being stopped, and the count value of the current life counter is used as the judgment this time. is the life value of the fail relay switch;

Step 5, if the detection flags of the L relay switches are still in the detection state, go back to Step 2, otherwise stop the detection.

The method is to judge whether the relay switch whose detection flag is in the state of inspection is invalid. The method is to judge whether the current on-off count value of the accumulated W times of the relay switch and the previous on-off count value are not in the relationship of increasing by 1, then the relay switch is invalid. , otherwise it does not fail; the W is an integer greater than or equal to 2.

The on-off times of the L relay switches are counted respectively, which is realized by L on-off counting units with the same structure and composition; the on-off counting unit includes a pulse generating circuit, an anti-pulse interference circuit and a tri-state output counting circuit. The pulse generation circuit outputs the initial pulse generated by the relay switch on and off to the anti-pulse interference circuit; the anti-pulse interference circuit performs pulse filtering on the initial pulse and outputs the counting pulse; the tri-state output counting circuit counts the counting pulse and outputs the on-off count value.

The anti-pulse interference circuit includes a reversible limiter counter, a comparison threshold value setter, an upper limit value comparator, a lower limit value comparator, and an RS flip-flop. The input of the reversible limiter counter is the initial pulse and the sampling clock pulse, and the output is the limiter accumulated count value that counts the sampling clock pulse; the output of the comparison threshold setter is the upper limit comparison threshold and the lower limit comparison threshold; the upper limit comparator The input of the limiter is the cumulative count value and the upper limit comparison threshold, and the output is the first set signal; the input of the lower limit comparator is the limiter cumulative count value and the lower limit comparison threshold, and the output is the second set signal; RS flip-flop The input is the first set signal and the second set signal, and the output is a count pulse; the lower limit amplitude of the limit accumulated count value is 0, and the upper limit amplitude value is N; the N is an integer greater than or equal to 2; The upper limit comparison threshold is an integer greater than N/2 and less than or equal to N, and the lower limit comparison threshold is an integer greater than or equal to 0 and less than N/2.

The function of the reversible clipping counter is to control whether the reversible clipping counter is in an up-counting state or a down-counting state by the level state of the initial pulse; the reversible clipping counter is in an up-counting state and the clipped cumulative count value is greater than or equal to the upper limit amplitude value. When N, the sampling clock pulse is not counted up; when the reversible limiter counter is in the down count state and the limiter cumulative count value is equal to the lower limit value of 0, the sampling clock pulse is not counted down.

The function of the upper limit value comparator is to make the first set signal valid when the input limiter cumulative count value is greater than or equal to the upper limit comparison threshold, otherwise the first set signal is invalid; the function of the lower limit value comparator is to make the first set signal valid when When the input limiter cumulative count value is less than or equal to the lower limit comparison threshold, the second set signal is made valid, otherwise the second set signal is invalid.

The first set signal is the set signal of the RS flip-flop, and the second set signal is the reset signal of the RS flip-flop; Phase output terminal output.

The reversible limiter counter is composed of a reversible counter with a single clock input and a limiter and an addition and subtraction control circuit; the reversible counter has an addition and subtraction control input end and an enable input end.

The relay life detection method is realized by a relay life detection device comprising a controller unit, L on-off counting units, a man-machine interface unit, a relay driving unit, and an oscillator unit. The man-machine interface unit is electrically connected to the controller unit for issuing detection commands and displaying the lifespan of the L relay switches; the controller unit is electrically connected to the relay driving unit, and sends a relay driving signal to the relay driving unit to control the L relays The on-off of the switch; the oscillator unit outputs the sampling clock pulse to the L on-off count units; the L on-off count units respectively count the on-off of the L relay switches to obtain L on-off count values; It is connected to the controller unit, and is used for the controller unit to read in the on-off count values of the L on-off count units and control the clearing of the on-off count values of the L on-off count units.

The on-off counting unit is electrically connected to the controller unit, and the method for the controller unit to read in the on-off count values of the L on-off count units respectively is that the on-off count values of the L on-off count units are all tri-state Buffer mode output; all the three-state buffer output ports of all on-off counting units are connected in parallel to the counting data input port of the controller unit; the controller unit sends a gating control signal to enable the three-state buffer output ports of each on-off counting unit one by one, Read the corresponding on-off count value from the count data input port.

The relay life detection device also includes a gating control unit; the controller unit sends an on-off counting unit address code signal to the gating control unit, and the gating control unit decodes the on-off counting unit address code signal to obtain the gating control unit. control signal.

The beneficial effects of the invention are as follows: the method can detect the lifespan of a plurality of relay switches at the same time; an anti-pulse interference circuit is used to automatically filter out edge jitter interference and narrow pulse interference in the electrical pulses generated by the on-off of the relay switches, and filter The effect of eliminating pulse interference can be adjusted by changing the size of the upper limit amplitude of the limiter cumulative count value or changing the size of the upper limit comparison threshold and the lower limit comparison threshold; it ensures the accuracy of the life detection of relays and switches; it is used in the controller unit The method of setting up multiple counters outside to count the on-off times of the relay switches respectively, and the number of relay switches for detecting the life of the relays is not limited by the number of counters inside the controller unit.

Description of drawings

1 is a block diagram of an embodiment of a relay life detection device when L=4;

Fig. 2 is an embodiment of an on-off counting unit;

Fig. 3 is an embodiment of a reversible limiter counter when N=6;

Fig. 4 compares the threshold value setter embodiment when N=6;

Fig. 5 is the embodiment of the upper limit comparator when N=6;

6 is an embodiment of a lower limit comparator when N=6;

Fig. 7 is an RS trigger embodiment;

Fig. 8 is 1# pulse generation circuit embodiment;

FIG. 9 is a schematic diagram of the anti-interference effect of the anti-pulse interference circuit when N=6;

10 is an embodiment of a three-state output counting circuit;

FIG. 11 is an embodiment of a relay driving unit.

Detailed ways

The present invention will be further described below with reference to the accompanying drawings.

1 is a block diagram of an embodiment of a relay life detection device when L=4, including a controller unit 10, 1# on-off counting unit 11, 2# on-off counting unit 12, 3# on-off counting unit 13, 4# on-off counting unit unit 14 , man-machine interface unit 15 , gating control unit 16 , relay driving unit 17 , oscillator unit 18 .

The man-machine interface unit 15 communicates with the controller unit 10 through the interface I/O1 of the controller unit 10, and is used to detect the issue of commands, parameter modification and display of the switch life of each relay, etc.; the controller unit 10 communicates with the relay through the output port OUT2 The drive unit 17 sends a relay drive signal to control the on-off of the 1# to 4# relay switches; the oscillator unit 18 outputs the sampling clock pulse CP1 to the 1# on-off count unit 11, 2# on-off count unit 12, 3# on-off Counting unit 13 and 4# on-off count unit 14; 1# on-off count unit 11, 2# on-off count unit 12, 3# on-off count unit 13, 4# on-off count unit 14 respectively On-off performs pulse generation, pulse filtering and on-off count; the controller unit 10 sends the on-off counting unit address code signal to be gated to the gating control unit 16 through the output port OUT1, and the gating control unit 16 counts the on-off count The unit address coding signal is decoded to obtain the gating control signals CS1, CS2, CS3, CS4, which respectively control 1# on-off counting unit 11, 2# on-off counting unit 12, 3# on-off counting unit 13, 4# on The on-off count values CV1, CV2, CV3, CV4 of the off-counting unit are sent to the controller unit 10 through the input port IN1, and IN1 is the count data input port of the controller unit; the controller unit 10 is on and off to 1# through the output port OUT3 Counting unit 11, 2# on-off count unit 12, 3# on-off count unit 13, 4# on-off count unit 14 send clear signal CLR; when clear 0 signal CLR is valid, the on-off count of 4 on-off count units values are cleared to 0.

Figure 2 is a block diagram of an embodiment of the 1# on-off counting unit. In FIG. 2, the 1# pulse generation circuit 100 outputs the initial pulse P1 generated by the ON/OFF of the 1# relay switch; the reversible limiter counter 101, the comparison threshold value setter 102, the upper limit value comparator 103, the lower limit value comparator 104. The RS flip-flop 105 forms an interference pulse filtering circuit, performs pulse filtering on the initial pulse P1, and outputs the counting pulse P2; the tri-state output counting circuit 106 counts the counting pulse P2, and is controlled by the gating control signal CS1, and outputs 1# The on-off count value CV1 of the relay switch; the three-state output count circuit 106 is simultaneously controlled by the clearing signal CLR, when the clearing signal CLR is valid, the on-off count value in the three-state output counting circuit 106 is cleared to 0.

In the anti-pulse interference circuit of FIG. 2, the input of the reversible limiter counter 101 is the initial pulse P1 and the sampling clock pulse CP1, and the output is the limiter accumulated count value X1. The upper limit of the limiter accumulated count value X1 is N and the lower limit The value is 0; the output of the comparison threshold value setter 102 is the upper limit comparison threshold value Y1 and the lower limit comparison threshold value Y2; the input of the upper limit value comparator 103 is the limiter cumulative count value X1 and the upper limit comparison threshold value Y1, and the output is the first set Signal SE1; the input of the lower limit value comparator 104 is the limit accumulation count value X1 and the lower limit comparison threshold value Y2, and the output is the second set signal RE1; the input of the RS flip-flop 105 is the first set signal SE1 and the second set signal SE1 Bit signal RE1, the output is count pulse P2.

In the following embodiments of the anti-pulse interference circuit, N=6.

FIG. 3 is an embodiment of a reversible slice counter when N=6. In Figure 3, FC1 is a 4-bit binary reversible counter 74HC191, the set control input terminal of FC1 is input 1 to LD, and FC1 works in a controllable reversible counting state, which is an up and down counter with a single clock input; the M input terminal of FC1 is a plus Minus control input, CE input is enable control input. The NAND gates FA1, FA2, FA3, and FA4 form a limiter and an addition and subtraction control circuit. The level state of the initial pulse includes high level and low level. In the embodiment of FIG. 3, P1 is connected to the addition and subtraction control input terminal M through the NAND gate FA4, and the high level and low level states of the initial pulse P1 are respectively controlled to be reversible. The limiter counter is in an up-counting state and a down-counting state. P1 can also be directly connected to the addition and subtraction control input terminal M, so that the high level and the low level of the initial pulse P1 respectively control the reversible limiter counter to be in a down-counting state and an up-counting state.

When P1 is 1, x13 and x12 are 1 at the same time, the NAND gate FA1 outputs a low level, the NAND gate FA3 outputs a high level, the enable control terminal CE of FC1 inputs a high level, and the 74HC191 works in the hold state, that is The reversible limiter counter keeps the output state unchanged at the rising edge of the sampling clock pulse CP1, and the reversible limiter counter is in the upper limit limit state and does not count up; x13 and x12 are 1 at the same time, including two cases, x13, x12, When x11 is 1, 1, and 0, the output of the reversible limiter counter is equal to the upper limit value of 6; when x13, x12, and x11 are 1, 1, and 1, the output of the reversible limiter counter is equal to 7, and it is in an over-limit state. Only the initial state when the system is started may appear. After the reversible limiter counts down and enters the normal limiter count range, the over-limit state of the output will not appear again. When P1 is 0, x13, x12, and x11 are 0 at the same time, the NAND gate FA2 outputs a low level, the NAND gate FA3 outputs a high level, the enable control terminal CE of FC1 inputs a high level, and the 74HC191 works in the hold state , that is, the reversible slice counter keeps the output state unchanged at the rising edge of the sampling clock pulse CP1, and the reversible slice counter is in the lower limit slice state and does not count down. The initial pulse P1 has two states of high level and low level, that is, the initial pulse P1 has two states of 1 and 0. The two states of the initial pulse P1 control the reversible limiter counter to count up or down the sampling clock pulse CP1 respectively. count. When P1 is 1, and x13 and x12 are not 1 at the same time, NAND gates FA1 and FA2 both output high level, NAND gate FA3 outputs low level, the enable control terminal CE of FC1 inputs low level, and P1 passes the AND The non-gate FA4 makes the addition and subtraction control terminal M input low level, 74HC191 works in the counting state, and the reversible limiter counts up on the rising edge of the sampling clock pulse CP1. When P1 is 0, and x13, x12, and x11 are not 0 at the same time, NAND gates FA1 and FA2 both output high level, NAND gate FA3 outputs low level, and the enable control terminal CE of FC1 inputs low level, plus Minus control terminal M inputs a high level, 74HC191 works in a down counting state, and the reversible limiter counts down on the rising edge of the sampling clock pulse CP1. 74HC191 is a synchronous binary counter, and it is only controlled by the state of P1 at the rising edge of the sampling clock pulse CP1 input from its clock input terminal CP to control whether it counts and counts up or down; at the non-rising edge of CP1, P1 causes The changes of the enable control terminal CE and the addition and subtraction control terminal M do not affect the x13, x12, and x11 output by the 74HC191. During the low level period of the clock input terminal CP, the change of the enable control terminal CE and the addition and subtraction control terminal M caused by P1 will affect the carry/borrow signal of the 74HC191. In the embodiment of Figure 3, the carry/borrow signal of the 74HC191 is not used. Borrow signal and therefore have no effect. The output of the reversible limiter counter is controlled and changed by the value of P1 at the rising edge of the sampling clock pulse, that is, the output of the reverse limiter counter is related to the sampling value at the rising edge of the sampling clock pulse P1, and is subject to the sampling of the rising edge of the sampling clock. value control. The output of the reversible limiter counter can also be controlled and changed by the value of P1 at the falling edge of the sampling clock pulse.

When N is other values, it can be realized by increasing or decreasing the number of NAND gates for counting and limiting control in Figure 3, and by increasing or decreasing the number of input signals of each NAND gate. The function of the reversible limiter counter can also be realized by other devices or circuits. For example, 74HC191 can be replaced by 74HC190, CD4516, etc., or a synchronous reversible counter can be composed of flip-flops and gate circuits.

FIG. 4 is an embodiment of a comparison threshold setter when N=6. In Figure 4, +VCC is the power supply, GND is the common ground, resistors R91, R92, R93 and switches K91, K92, K93 form the upper limit comparison threshold Y1 setting circuit; In the off state, the upper limit comparison threshold Y1 output by the comparison threshold setter is 5, and its 3-bit binary outputs y13, y12, and y11 are 1, 0, and 1. Resistors R94, R95, R96 and switches K94, K95, K96 form a lower limit comparison threshold Y2 setting circuit; when K94, K95, K96 are in the closed, closed, and open states respectively, the lower limit comparison threshold Y2 output by the comparison threshold setter is 1, its 3-bit binary output y23, y22, y21 is 0, 0, 1. The comparison threshold setter can also be a binary DIP switch, or a BCD DIP switch, or multiple pull-up resistors and circuit short contacts that control the output of 0 and 1, and other circuits that can output multi-bit binary setting values. composition.

The function of the upper limit comparator is to make the first set signal valid when the input limiter cumulative count value is greater than or equal to the upper limit comparison threshold, otherwise the first set signal is invalid. Fig. 5 is an embodiment of the upper limit comparator when N=6. The upper limit comparator is composed of a four-bit binary value comparator FC2 and an OR gate FO1, and the model of FC2 is 74HC85. The 3-bit binary outputs x13, x12, and x11 of the limiter cumulative count value X1 are respectively connected to the A2, A1, and A0 input terminals of FC2, and the 3-bit binary outputs y13, y12, and y11 of the upper limit comparison threshold Y1 are respectively connected to the B2, A1, and A0 terminals of FC2. B1, B0 input terminal, input terminal A3, B3 input 0. The input terminals A>B IN and A<B IN of FC2 both input 0, and the input terminal A=B IN input 1. The output terminals A>B OUT and A=B OUT of FC2 are respectively connected to the input terminals of the OR gate FO1, and the output terminal of the OR gate FO1 is the first set signal SE1. The function implemented by the upper limit comparator in FIG. 5 is that when the limiter accumulated count value X1 is greater than or equal to the upper limit comparison threshold Y1, the output SE1 is high, otherwise SE1 is low. In Figure 5, SE1 is active at high level; if the OR gate FO1 is changed to a NOR gate, SE1 is active at low level.

The function of the lower limit comparator is to make the second set signal valid when the input limiter cumulative count value is less than or equal to the lower limit comparison threshold, otherwise the second set signal is invalid. Fig. 6 is an embodiment of the lower limit value comparator when N=6, the lower limit value comparator is composed of a four-bit binary value comparator FC3 and an OR gate FO2, and the model of FC3 is 74HC85. The 3-bit binary outputs x13, x12, and x11 of the limiter cumulative count value X1 are respectively connected to the A2, A1, and A0 input terminals of FC3, and the 3-bit binary outputs y23, y22, and y21 of the lower limit comparison threshold Y2 are respectively connected to the B2, A1, and A0 terminals of FC2. B1, B0 input terminals, input terminals A3, B3 are connected to 0. The input terminals A>B IN and A<B IN of FC3 are both connected to 0, and the input terminal A=B IN is connected to 1. The output terminals A<B OUT and A=B OUT of FC3 are respectively connected to the input terminals of the OR gate FO2, and the output terminal of the OR gate FO2 is the second set signal RE1. The function implemented by the lower limit comparator in FIG. 6 is that when the limiter accumulated count value X1 is less than or equal to the lower limit comparison threshold Y2, the output RE1 is high, otherwise SE1 is low. In Figure 6, RE1 is active high; if the OR gate FO2 is changed to a NOR gate, RE1 is active low.

When the N value is large, two or more pieces of 74HC85 can be selected to form a multi-bit binary value comparator to realize the function of the upper limit value comparator or the lower limit value comparator; one or more pieces of four-bit binary value comparison can also be used. The CD4063 implements the function of the upper limit value comparator or the lower limit value comparator, or uses other combinational logic circuits to realize the function of the upper limit value comparator or the lower limit value comparator.

FIG. 7 is an embodiment of an RS flip-flop. In Figure 7, the NOR gates FO3 and FO4 form an RS flip-flop, the first set signal SE1 is the set signal of the RS flip-flop, and the second set signal RE1 is the reset signal of the RS flip-flop, both of which are active high; The count pulse P2 is output from the non-inverting output terminal of the RS flip-flop, that is, the output terminal of FO4. The count pulse P2 can also be output from the inverting output terminal of the RS flip-flop, that is, the output terminal of the NOR gate FO3. RS flip-flops may also adopt other forms of RS flip-flops.

In the above-mentioned embodiment of N=6, the upper limit comparison threshold Y1 takes a value of 5, and the lower limit comparison threshold Y2 takes a value of 1. When the limiter cumulative count value X1 is greater than or equal to 5, the output SE1 is high level, and the count pulse P2 is set to 1; when the limiter cumulative count value X1 is less than or equal to 1, the output RE1 is high level, and the count pulse P2 is set to 0.

FIG. 8 is an embodiment of a 1# pulse generating circuit. 1# Relay switch KA1 is connected in series with the load resistor RA1, and then connected to the power supply V1 and V2; the step-down resistor R11 is connected in series with the bidirectional voltage regulator tube VD1, and then connected in parallel to both ends of the load resistor RA1; U11 is a bidirectional input optocoupler, The current limiting resistor R12 is connected in series with the bidirectional light-emitting diode at the input end of U11 and then connected in parallel to both ends of the bidirectional voltage regulator tube VD1; the pull-up resistor R13 is the collector load resistance of the output triode of U11; the initial pulse P1 is output from the collector of the output triode of U11. The AC/DC switch K11 is connected in series with the step-down capacitor C11 and then connected in parallel to both ends of the step-down resistor R11. In the embodiment of FIG. 8 , the relay switch KA1 is a normally open switch; the relay switch can also be a normally closed switch. For example, the KA1 in the embodiment of FIG. 8 can be replaced with a normally closed switch, and other parts of the circuit remain unchanged.

In Figure 8, when the test power supplies V1 and V2 are DC power supplies, V1 is positive and V2 is negative, or V1 is negative and V2 is positive. At this time, the AC-DC switch K11 is turned off. When KA1 is disconnected, there is no voltage on the load resistor RA1, the output transistor of U11 is turned off, and the initial pulse P1 is high. When KA1 is turned on, after the voltage on the load resistor RA1 is stepped down by R11 and stabilized by VD1, the input diode of U11 is controlled by R12 to emit light, the output transistor of U11 is saturated and turned on, and the initial pulse P1 is low level. KA1 is switched on and off once, and the initial pulse P1 outputs a pulse with edge jitter and narrow pulse interference.

In Fig. 8, when the test power supply V1 and V2 are AC power, the positive and negative of V1 and V2 change alternately, and the AC-DC switch K11 is turned on at this time. When KA1 is disconnected, there is no voltage on the load resistor RA1, the output transistor of U11 is turned off, and the initial pulse P1 is high. When KA1 is turned on, the AC voltage of the non-zero-crossing point on the load resistor RA1 is stepped down by R11 and stabilized by VD1, and then the input diode of U11 is controlled by R12 to emit light, the output transistor of U11 is saturated and turned on, and the initial pulse P1 is low level; When the AC voltage on the load resistor RA1 crosses zero, its voltage is low enough to drive the input diode of U11 to emit light, the output transistor of U11 is turned off, and the initial pulse P1 is high; therefore, when KA1 is turned on, the initial pulse P1 is low A pulse with a large proportion of level and a small proportion of high level, or the initial pulse P1 is a low level at this time, but there is positive narrow pulse interference; KA1 is turned on and off once, and the initial pulse P1 outputs a narrow pulse with edge jitter Pulses of interference and positive narrow pulse interference.

By changing the size of the load resistance RA1, the magnitude of the resistive load current of the relay switch KA1 to be detected can be adjusted. When the test power supply V1 and V2 in FIG. 8 are AC power, the load resistance RA1 can also be changed to an inductive load or a capacitive load. VD1 in Figure 8 can also choose a bidirectional TVS tube. When the test power supply V1 and V2 are always DC, the AC/DC switch K11 and the step-down capacitor C11 in Figure 8 can be removed, VD1 selects a one-way voltage regulator or one-way TVS tube, and U11 selects a one-way input optocoupler . When the test power supplies V1 and V2 are always AC, the AC/DC switch K11 in Figure 8 can be removed, and the step-down capacitor C11 is directly connected in parallel to both ends of the step-down resistor R11. The pulse generating circuit can also use circuits other than those shown in FIG. 8 .

FIG. 9 is a schematic diagram of the anti-interference effect of the anti-pulse interference circuit when N=6. Fig. 9 shows the sampling value P1* of the initial pulse P1 by the 15 sampling clock pulses CP1, the limit accumulated count value X1 of each sampling point, and the obtained count pulse P2. The sampling value P1* is the value of the initial pulse P1 when the sampling clock pulse CP1 counts the edge; the two states of the initial pulse P1 respectively control the reversible limiter counter to count up or down the sampling clock pulse CP1. When CP1 counts the edge, the value of the initial pulse P1 respectively controls the reversible limiter counter to count up or down the sampling clock pulse CP1. It is assumed that the limiter accumulation count value X1 before the sampling point 1 of CP1 in FIG. 9 is 0, and the count pulse P2 is 0. In Figure 9, the initial pulse P1 has positive pulse interference at sampling point 2 of CP1, which causes X1 to sample the interference value 1 of P1* at sampling point 2; the initial pulse P1 appears between sampling point 4 and sampling point 5 of CP1 The positive narrow pulse interference is detected, but the positive narrow pulse width is smaller than the sampling period and between two sampling points, which does not affect the sampling result P1*, that is, the sampling process automatically filters out the positive narrow pulse interference. The initial pulse P1 starts to change from 0 to 1 after the sampling point 6 of CP1. During the process of changing from 0 to 1, there are 2 edge jitters (or include positive narrow pulse interference and edge jitter). The second positive narrow pulse The jitter interference is automatically filtered out by the sampling process, and the values of sampling point 7 and sampling point 8 are 1 and 0, respectively. In FIG. 9 , the sampled value P1*, the count pulse P2 and the limit accumulated count value X1 obtained from the sampling point 1 to the sampling point 15 of the clock pulse CP1 are shown in Table 1.

Table 1 Sampling value P1*, limit accumulated count value X1 and count pulse P2 of sampling point 1-15

Observe the situation of the sampling points in Table 1. At sampling points 1-9, X1 is less than or equal to Y2, RE1 is valid, SE1 is invalid, and P2 is set to 0; at sampling points 10-12, X1 is greater than Y2 and less than Y1, SE1, RE1 are invalid, and P2 remains 0; at sampling points 13-15, when X1 is greater than or equal to Y1, SE1 is valid, RE1 is invalid, and P2 is set to 1. When N=6, the count interval of the reversible limiter counter is 0-N; at sampling point 3 in Table 1, X1 has reached the lower limit value 0, and at sampling point 4-6, P1*=0 (that is, at this time If P1=0), X1 no longer counts down, and X1 remains at the lower limit value of 0; at sampling point 14, X1 has reached the upper limit amplitude of 6, at sampling point 15, P1*=1 (that is, at this time P1=1), X1 no longer counts up, and X1 maintains the upper limit amplitude 6. At sampling points 1-8, the initial pulse P1 is the low-level state output by the pulse generating circuit, which is a pulse with a large proportion of low-level and a small proportion of high-level, that is, some positive narrow pulse interference is included in the middle, but due to In this interval, the low level holding time of the initial pulse P1 is much longer than the time occupied by the positive narrow pulse interference. These positive narrow pulse disturbances do not affect the change interval of the limiter cumulative count value X1 as a whole, and X1 remains between 0 and 1. ; Even if the influence of the positive narrow pulse interference is greater, as long as the time occupied by the positive narrow pulse interference is smaller than the holding time of the low level, the limiter cumulative count value X1 will not exceed N/2, and it is more difficult to achieve greater than or equal to Y1, The state of count pulse P2 is not changed. Figure 9 shows the anti-positive pulse interference effect of the interference pulse filtering circuit when the initial pulse P1 is 0, and the conditions and process for the initial pulse P1 to change from 0 to 1. The anti-negative pulse interference effect of the interference pulse filter circuit when the initial pulse P1 is 1, and the conditions and process of the initial pulse P1 changing from 1 to 0, and the anti-positive pulse interference effect when the initial pulse P1 is 0, and the initial pulse P1 The conditions for changing from 0 to 1 are the same as the process. Similarly, when some negative narrow pulse interference is included in the high level state of the initial pulse P1, during this period, the high level holding time of the initial pulse P1 is longer than the time occupied by the negative narrow pulse interference, the limit accumulation count The value X1 will not be less than N/2, it is more difficult to reach less than or equal to Y2, and the state of the count pulse P2 will not be changed.

It is assumed that the slice accumulated count value X1 before the sampling point 31 of the clock pulse CP1 is 6, and the count pulse P2 is 1. See Table 2 for the sampling value P1*, the limit accumulated count value X1 and the count pulse P2 obtained from the sampling point 31 to the sampling point 45.

Table 2 Sampling value P1*, limit accumulated count value X1 and count pulse P2 of sampling points 31-45

Observe the sampling points in Table 2. At sampling points 31-32, X1 is greater than or equal to Y1, SE1 is valid, RE1 is invalid, and P2 is set to 1; at sampling point 33, X1 is greater than Y2 and less than Y1, SE1 and RE1 are invalid, P2 remains 1; at sampling point 34, X1 is greater than or equal to Y1, SE1 is valid, RE1 is invalid, and P2 is set to 1; at sampling points 35-39, X1 is greater than Y2 and less than Y1, SE1 and RE1 are invalid, and P2 remains at 1 ;Because between the sampling points 31-40, the sampling value P1* is in the state of 0 more than 1 Y2, RE1 is valid, SE1 is invalid, P2 is set to 0; at sampling point 41, X1 is greater than Y2 and less than Y1, SE1 and RE1 are invalid, P2 remains at 0; at sampling points 42-45, X1 is less than or equal to Y2, RE1 is valid , SE1 is invalid, and P2 is set to 0. At the sampling point 43 in Table 2, X1 has reached the lower limit value of 0. At the sampling points 44-45, P1*=0 (that is, P1=0 at this time), X1 is no longer counted down, and X1 remains as The lower limit value is 0.

In this embodiment of N=6, the count pulse P2 and the initial pulse P1 are in an in-phase relationship. If the function of the reversible limiter counter is changed to: when P1=1, the reversible limiter counter will count down; when P1=0, the reversible limiter counter will count up, and the phase between the count pulse P2 and the initial pulse P1 will be reversed. relation. Or in FIG. 7 , the count pulse P2 is changed to be output from the NOR gate FO3, and the count pulse P2 and the initial pulse P1 are in an inverse relationship. If the above modification is carried out at the same time, the relationship between the count pulse P2 and the initial pulse P1 is in phase again.

Taking the in-phase relationship between the counting pulse P2 and the initial pulse P1 as an example, it can be concluded from Table 1, Table 2 and the working principle of the circuit that due to the cumulative effect of the reversible limiter counter, when the sampling value of the initial pulse P1 is in the When the number of 1s is more than the number of 0s within a period of time, the limiter cumulative count value X1 will tend to increase, so that X1 is greater than or equal to Y1 and the count pulse P2 is set to 1; when the sampling value of the initial pulse P1 is within a period of time. When the number of 0s is greater than the number of 1s, the limiter cumulative count value X1 will tend to decrease, so that X1 is less than or equal to Y2 and the count pulse P2 is set to 0; this feature enables the limiter counting unit of the circuit of the present invention to have self-start Capability, limit function and 0 in the initial pulse P1 sampling value P1* will cause the limiter counting unit to enter the normal limiter count interval to perform limiter addition and subtraction counting. When the initial limiter accumulative count value X1 is greater than N and is in the over-limit state, X1 is greater than or equal to the upper limit comparison threshold Y1, the SE1 output by the upper limit comparator is valid, the lower limit comparator output RE1 is invalid, and P2 is set to 1.

Since the upper limit comparison threshold Y1 is an integer greater than N/2 and less than or equal to N, and the lower limit comparison threshold Y2 is an integer greater than or equal to 0 and less than N/2, the first set signal SE1 and the second set signal RE1 cannot be active at the same time , therefore, the output of the RS flip-flop will not have an indeterminate logic state.

Further description is given by taking the in-phase relationship between the count pulse P2 and the initial pulse P1 as an example. When the initial pulse P1 makes the limiter cumulative count value X1 less than or equal to the lower limit comparison threshold Y2, and the count pulse P2 is set to 0, as long as the limiter cumulative count value X1 is always smaller than the upper limit comparison threshold Y1, the count pulse P2 will not become 1; When the initial pulse P1 makes the limiter cumulative count value X1 greater than or equal to the upper limit comparison threshold Y1, and the count pulse P2 is set to 1, as long as the limiter cumulative count value X1 is always greater than the lower limit comparison threshold Y2, the count pulse P2 will not become 0. When both P1 and P2 are at low level, as long as the positive pulse that appears in P1 makes P1 sampling values greater than or equal to Y1 values of 1 continuously appear, or, Y1+ appears in successive Y1+2 P1 sampling values A value of 1, etc., can output a positive pulse corresponding to the positive pulse in the P1 from P2; when both P1 and P2 are high, as long as the negative pulse that appears in P1 makes the P1 sampling value continuous If there are more than or equal to N-Y2 values of 0, or, N-Y2+1 values of 0 appear in consecutive N-Y2+2 P1 sampling values, etc., it can output from P2 and the P1 Negative pulse corresponding to the negative pulse in the middle. When the initial pulse P1 changes from 0 to 1, the count pulse P2 needs to limit the accumulated count value X1 after several sampling pulse cycles to count up and delay, so that the limiter accumulated count value X1 is greater than or equal to the upper limit comparison threshold Y1, and P2 is set to 1; When the initial pulse P1 changes from 1 to 0, the count pulse P2 needs to limit the accumulated count value X1 after several sampling pulse cycles down-counting delay, so that the limiter accumulated count value X1 is less than or equal to the lower limit comparison threshold Y2, Set P2 to 0. When the value of the upper limit comparison threshold Y1 is larger, the condition for the counting pulse P2 to change from 0 to 1 is more severe, and the low-level anti-positive pulse interference effect of the circuit is better; the smaller the value of the lower limit comparison threshold Y2 is, the counting pulse The condition for P2 to change from 1 to 0 is more severe, and the high level of the circuit has better anti-negative pulse interference effect. When the value of N becomes larger, the interference pulse filtering circuit changes the counting pulse P2 from 0 to 1, and the conditions for changing from 1 to 0 become stricter, and the anti-interference effect becomes better, but the delay time of the counting pulse P2 relative to the initial pulse P1 becomes larger; when the value of N becomes smaller, the interference pulse filtering circuit will change the counting pulse P2 from 0 to 1, and the conditions of changing from 1 to 0 will become wider, and the anti-interference effect will become smaller, but the count pulse P2 is relative to the initial pulse P1. The delay time becomes smaller.

FIG. 10 is an embodiment of a three-state output counting circuit. Figure 10 (a) is the first embodiment of the tri-state output counting circuit, which is composed of a counter FC4 and a non-gate FN1, and FC4 is an 8-bit binary counter 74HC590 with tri-state output. FC4's counting enable terminal CCKEN inputs 0, and the clearing control terminal CCLR is the input terminal of the clearing signal CLR of the tri-state output counting circuit; the clearing signal CLR is active at low level, that is, the clearing signal CLR output by the controller unit is low power Usually, the on-off count value in the counter FC4 is cleared to 0; when the clear signal CLR output by the controller unit is at a high level, FC4 works in the counting state, and the counting pulse P2 is directly connected to the counting pulse input terminal CCK of FC4, FC4 Add 1 count on the rising edge of count pulse P2 to get the on-off count value. The count pulse P2 is connected to the data latch terminal RCK of FC4 through the NOT gate FN1, and the content of the internal counter of FC4 is latched to the output latch at the falling edge of the count pulse P2. The strobe control signal CS1 is connected to the output enable control terminal G of FC4. When CS1 is low, FC4 outputs the on-off count value CV1 in the output latch from Q7-Q0; when CS1 is high, Q7 of FC4 -Q0 is in high impedance state. The on-off count value output by the three-state output counting circuit Embodiment 1 is an 8-bit binary count value.

Figure 10(b) shows the second embodiment of the tri-state output counting circuit, which is composed of a counter FC5 and a tri-state buffer FB1, FC5 is a 4-bit binary counter 74HC161, and FB1 is a tri-state buffer 74HC244. The counting control terminals CTP and CTR of FC5, and the number setting control terminal LD are connected to 1, and the clearing control terminal CR is the input terminal of the clearing signal CLR of the three-state output counting circuit; the clearing signal CLR is active at a low level, that is, the control When the clear signal CLR output by the controller unit is low level, the on-off count value in the counter FC5 is cleared to 0; when the clear signal CLR output by the controller unit is high level, FC5 works in the counting state, and the counting pulse P2 directly Connected to the count pulse input terminal CP of FC5, FC5 adds 1 to count on the rising edge of count pulse P2 to obtain the on-off count value. The 4-bit data input terminals A3-A0 of the tri-state buffer FB1 are respectively connected to the 4-bit count value output terminals Q3-Q0 of the counter FC5, the gating control signal CS1 is connected to the output enable control terminal 1G of FB1, and CS1 is low power Usually, FB1 outputs the on-off count value CV1 output by counter FC5 from Y3-Y0; when CS1 is high, Y3-Y0 of FB1 is in a high-impedance state. The on-off count value output by the three-state output count circuit embodiment 2 is a 4-bit binary count value.

In the embodiment of the relay life detection device when L=4, the 2# on-off counting unit, the 3# on-off counting unit and the 4# on-off counting unit adopt the same circuit composition and structure as the 1# on-off counting unit, that is, all on-off counting units The off-counting unit includes a pulse generating circuit, an anti-pulse interference circuit and a tri-state output counting circuit; all pulse generating circuits, anti-pulse interference circuits, and tri-state output counting circuits have the same composition and structure.

FIG. 11 is an embodiment of a relay driving unit. Figure 11(a) is an embodiment when the relay coil is powered by a DC power supply, which is composed of a triode VT, a freewheeling diode VD, and a base resistor R61; the coil of the relay to be detected is connected in parallel to nodes A1 and A2, and the DC power supply of the relay coil The power supply is +V. Assuming that the four relay switches in the embodiment of FIG. 1 are included in two relays, in FIG. 11( a ), only two relay coils J1 and J2 are connected in parallel. When the relay drive signal C1 sent by the controller unit is at a high level, all the relay coils connected in parallel to nodes A1 and A2 are energized; when the relay drive signal C1 sent by the controller unit is at a low level, the parallel connection between nodes A1 and A2 All relay coils on the switch are de-energized; the relay drive signal C1 sent by the controller unit changes for one pulse period, and the relay switches in all the relays on the nodes A1 and A2 are connected in parallel with the coils on and off once. When the number of relay coils is large and the triode VT in Fig. 11(a) is not enough to drive all of them, the same or similar drive circuit can be added to expand the drive capability.

Figure 11(b) is an embodiment when the relay coil is powered by an AC power supply, which consists of a current-driven solid state relay SSR1, a varistor RU1, and a current limiting resistor R62; the coils of the relays to be detected are connected in parallel to nodes B1 and B2, and the relay The AC power supply of the coil is AC0; +VCC is the current drive power supply of SSR1. Assuming that the four relay switches in the embodiment of FIG. 1 are included in two relays, in FIG. 11( b ), only two relay coils J3 and J4 are connected in parallel. When the relay drive signal C2 sent by the controller unit is at low level, all the relay coils connected in parallel on nodes B1 and B2 are energized; when the relay drive signal C2 sent by the controller unit is at high level, they are connected in parallel at nodes B1 and B2. All the relay coils on the switch are de-energized; the relay drive signal C2 sent by the controller unit changes for one pulse period, and the relay switches in all the relays on the nodes B1 and B2 connected in parallel with the coils are turned on and off once. When the number of relay coils is large and the solid state relay SSR1 in Figure 11(b) is not enough to drive all of them, the same or similar drive circuit can be added to expand the drive capability.

When there are relay coils powered by DC power supply and relay coils powered by AC power supply in the relay where the L relay switches are located, the circuits of Figure 11(a) and Figure 11(b) can be used to classify and drive at the same time. The relay drive unit can also use other circuits as required.

The oscillator unit is used to output the sampling clock pulse CP1, and any one of various multivibrators can be selected to form the oscillator unit. During the test, the on-off frequency of the relay switch is usually between 10 times/min and 30 times/min. The initial pulse comes from the on-off control output of the relay switch. 1000ms, therefore, the period of the sampling clock pulse CP1 can be selected between 8ms and 48ms, and because the period of the positive narrow pulse interference in P1 is 10ms, the sampling clock pulse CP1 should be avoided to be an integer multiple of 10ms, and N is in the range of 5 to 10 internal value.

The human-machine interface unit preferably uses a touch screen, and uses RS485 or RS232 to communicate with the controller unit. The man-machine interface unit can also be composed of a key circuit and a liquid crystal display.

The on-off count values of all on-off count units are output in tri-state buffer mode; the tri-state buffer output ports of all on-off count units are all connected in parallel to the count data input port of the controller unit, and the controller unit sends out gating control signals respectively The tri-state buffer output port of each on-off count unit is enabled, and the on-off count value output by the enabled tri-state buffer output port is read from the count data input port. The on-off count value in Embodiment 1 of the tri-state output counting circuit is 8-bit binary data, and the tri-state buffer output port of the on-off counting unit and the count data input port of the controller unit are both 8-bit parallel ports; the tri-state output count The on-off count value in the circuit embodiment 2 is 4-bit binary data, and the tri-state buffer output port of the on-off count unit and the count data input port of the controller unit are both 4-bit parallel ports. When the L value is small and the number of digits of the on-off count value is small, the on-off count value of the on-off count unit may not be output in the three-state buffer mode, but the on-off count value output port of each on-off count unit is directly output. Connect to different parallel ports of the controller unit; for example, when L=4 and the on-off count value is a 4-bit binary value, directly connect the on-off count value output ports of the 4 on-off count units to different parallel ports of the controller unit port, only need to consume a total of 16-bit I/O port lines of the controller unit, that is, 2 8-bit input ports.

The controller unit sends a gating control signal through the gating control unit. The gating control unit is a decoder circuit, which decodes the address coding signal of the on-off counting unit sent by the controller unit to obtain the gating control signal. In the embodiment of FIG. 1, the on-off counting unit address coding signals corresponding to 1# on-off counting unit 11, 2# on-off counting unit 12, 3# on-off counting unit 13, 4# on-off counting unit are respectively binary 00, 01, 10, 11, the decoding output is CS1, CS2, CS3, CS4; the controller unit enables CS1, CS2, CS3, CS4 one by one, enables the three-state buffer output port of each on-off counting unit, and then from the The count data input port IN1 reads the corresponding on-off count value. In the embodiment, the decoder circuit of the gating control unit may select 74HC139, or 74HC138, or be composed of gate circuits. When the L value is large, the decoder circuit can be composed of multiple pieces of 74HC139, or a multi-level cascade circuit composed of 74HC138, etc., or composed of multiple gate circuits. When the value of L is small, the gating control unit can also be omitted, and the gating control signal is directly sent by the controller unit to each on-off counting unit through the output port. For example, in the embodiment of FIG. 1, the gating control signals CS1, CS2, CS3 and CS4 can be directly issued by the controller unit 10 without using a gating control unit.

The controller unit is used to control the entire relay life detection device, and is preferably composed of a single-chip microcomputer as the core. The core of the controller unit can also choose ARM, or DSP, or programmable controller. The detection and control process of the relay life detection device includes the following steps:

Step 1, initialization, including setting the detection flags of the L relay switches to the detection state, clearing the life counter to 0, and sending a clearing signal to clear all the L on-off count values to 0;

Step 2: Control the on-off times of the L relay switches once, and simultaneously count the on-off times of the L relay switches to obtain L on-off count values; the life counter adds 1 to count;

Step 3, read the current L on-off count values;

Step 4: Judging whether the relay switch whose detection flag is in the state of inspection is invalid one by one; the detection flag of the relay switch which is judged to be invalid this time is set to the state of being stopped, and the count value of the current life counter is used as the judgment this time. is the life value of the fail relay switch;

Step 5, if the detection flags of the L relay switches are still in the detection state, go back to Step 2, otherwise stop the detection.

Controlling L relay switches on and off once means that the controller unit sends a relay drive signal, and the relay switches are turned on and off once through the relay drive unit. For example, the relay drive signal C1 sent by the controller unit in Figure 11(a) changes by one The pulse period, or the relay drive signal C2 sent by the controller unit in FIG. 11(b) changes by one pulse period. The life counter is a software counter in the controller unit. The controller unit sends a relay drive signal to make the relay switch on and off once, and the count value of the life counter is incremented by 1. At the same time, the on-off times of the L relay switches are respectively counted to obtain L on-off count values, which are respectively performed by the on-off count units other than the controller unit.

The method of judging whether the relay switch whose detection flag is in the state of inspection is invalid is that the error between the number of times the relay switch is controlled to be turned on and off and its on-off count value is less than E, then the relay switch is not invalid, otherwise it is invalid. The count value of the current life counter is the number of times the relay switch to be judged is controlled on and off. The specific judgment method is to set the maximum count value of the on-off count value to G, and take the count value of the current life counter modulo G to obtain the remainder Q; the read on-off count value of the relay switch to be judged is K, then when When either |K-Q|<E, or |K-(Q-G)|<E, or |K-(Q+G)|<E is satisfied, the relay switch does not fail, otherwise it fails. The on-off count value adopts the cyclic counting method. After the on-off count value reaches the maximum count value G of the tri-state output counting circuit, it will overflow and become 0; Take the binary on-off count value as an example, the maximum value is 1111, and the next on-off count value is 0; in the above judgment expression, comparing K with Q-G is to offset the K value plus the count overflow and the smaller value, and the Q value Larger influence; comparing K with Q+G is to offset the larger K value and the smaller effect of the Q value on G modulo. Since E is an integer greater than or equal to 1 and less than or equal to G/2 (G divided by 2), after determining the error E, the maximum count value G of the on-off count value must be greater than 2 times of E; for example, if E is determined to be 3, Then the maximum count value G of the on-off count value must be greater than 6. At this time, the decimal BCD counter or the binary counter with more than 3 digits can meet the requirements. In the current L on-off count values read, the controller unit no longer judges and processes whether the relay switch whose detection flag is in the stop-check state is invalid.

The following method can also be used to judge whether the relay switch whose detection flag is in the state of inspection is invalid: when the current on-off count value of the relay switch to be judged is not in the relationship between the previous on-off count value and the previous on-off count value, the relay switch is invalid. , otherwise it does not fail; the method is alternatively, when it is to be judged that the current on-off count value of the relay switch V consecutive times and the previous on-off count value are not in the relationship of increasing by 1, then the relay switch fails, otherwise it does not fail; the V is Integer greater than or equal to 2. The on-off count value adopts the cyclic counting method. After the on-off count value reaches the maximum value of the tri-state output counting circuit, adding 1 will overflow to 0; Take the off-count value as an example, the maximum value is 1111, and the next on-off count value that satisfies the relationship of increment by 1 is 0.

The following method can also be used to judge whether the relay switch whose detection flag is in the state of inspection is invalid: when it is judged that the current on-off count value of the accumulated W times of the relay switch and the previous on-off count value are not in the relationship of increasing by 1, then the The relay switch fails, otherwise it does not fail; the W is an integer greater than or equal to 2.

The controller unit and the man-machine interface unit can adjust and display the NO and NC duty ratio of the relay switch (that is, set the ratio of the pull-in time and the release time) according to the needs, select the failure judgment method and set and display the failure judgment parameters. On-off cycle setting and display, etc. The device can also add a temperature monitoring unit to monitor the temperature of the relay during the test.

In order to reduce the volume and improve the reliability, it is preferable to use PAL, GAL, CPLD, FPGA, or other programmable logic devices for all or part of the L on-off counting units, oscillator units, and gating control units. , the logic unit to achieve.

Except for the technical features described in the specification, they are all conventional technologies mastered by those skilled in the art. For example, select the controller of the controller unit, design the relevant peripheral control circuit and compile the program according to the detection control process and method of the device to realize its function; select or design the gating control unit circuit to meet the requirements of decoding gating; select Or design the multivibrator of the oscillator unit to output the sampling clock pulse CLK that meets the requirements; select the composition and circuit structure of the man-machine interface unit, connect it with the controller unit, and realize the corresponding functions; Conventional techniques mastered by technicians.

Claims (10)

1. a relay life detection method, is characterized in that, comprises: Step 1, initialization, including setting the detection flags of the L relay switches to the detection state, clearing the life counter to 0, and sending a clearing signal to clear all the L on-off count values to 0; Step 2: Control the on-off times of the L relay switches once, and simultaneously count the on-off times of the L relay switches to obtain L on-off count values; the life counter adds 1 to count; Step 3, read the current L on-off count values; Step 4: Judging whether the relay switch whose detection flag is in the state of inspection is invalid one by one; the detection flag of the relay switch which is judged to be invalid this time is set to the state of being stopped, and the count value of the current life counter is used as the judgment this time. is the life value of the fail relay switch; Step 5, if there is still a state under inspection in the detection flags of the L relay switches, return to step 2, otherwise stop the detection; The method is to judge whether the relay switch whose detection flag is in the state of inspection is invalid. The method is to judge whether the current on-off count value of the accumulated W times of the relay switch and the previous on-off count value are not in the relationship of increasing by 1, then the relay switch is invalid. , otherwise it does not fail; the W is an integer greater than or equal to 2. 2. The relay life detection method according to claim 1 is characterized in that: the on-off times of L relay switches are counted respectively, which is realized by L on-off count units with the same structure and composition; the on-off count units include: Pulse generating circuit, anti-pulse interference circuit and tri-state output counting circuit; The pulse generation circuit outputs the initial pulse generated by the relay switch on and off to the anti-pulse interference circuit; the anti-pulse interference circuit performs pulse filtering on the initial pulse and outputs the counting pulse; the tri-state output counting circuit counts the counting pulse and outputs the on-off count value. 3. The relay life detection method according to claim 2, wherein the anti-pulse interference circuit comprises a reversible limiter counter, a comparison threshold value setter, an upper limit value comparator, a lower limit value comparator, and an RS trigger. device; The input of the reversible limiter counter is the initial pulse and the sampling clock pulse, and the output is the limiter accumulated count value that counts the sampling clock pulse; the output of the comparison threshold setter is the upper limit comparison threshold and the lower limit comparison threshold; the upper limit comparator The input of the limiter is the cumulative count value and the upper limit comparison threshold, and the output is the first set signal; the input of the lower limit comparator is the limiter cumulative count value and the lower limit comparison threshold, and the output is the second set signal; RS flip-flop The input is the first set signal and the second set signal, and the output is a count pulse; the lower limit amplitude of the limit accumulated count value is 0, and the upper limit amplitude value is N; the N is an integer greater than or equal to 2; The upper limit comparison threshold is an integer greater than N/2 and less than or equal to N, and the lower limit comparison threshold is an integer greater than or equal to 0 and less than N/2. 4. The relay life detection method according to claim 3 is characterized in that: the function of the reversible limiter counter is to control whether the reversible limiter counter is in an up-counting state or a down-counting state by the level state of the initial pulse; When the limiter counter is in the count-up state and the limiter cumulative count value is greater than or equal to the upper limit value N, the sampling clock pulse is not counted up; when the reversible limiter counter is in the downcount state and the limiter cumulative count value is equal to the lower limit value of 0, Sampling clock pulses are not counted down. 5 . The relay life detection method according to claim 4 , wherein the function of the upper limit comparator is to make the first set signal valid when the input limiter cumulative count value is greater than or equal to the upper limit comparison threshold, 5 . Otherwise, the first set signal is invalid; the function of the lower limit comparator is to make the second set signal valid when the input limiter cumulative count value is less than or equal to the lower limit comparison threshold, otherwise the second set signal is invalid. 6. The relay life detection method according to claim 5, characterized in that: the first set signal is a set signal of an RS flip-flop, and the second set signal is a reset signal of an RS flip-flop; the counting Pulses are output from the non-inverting output of the RS flip-flop, or from the inverting output of the RS flip-flop. 7. The relay life detection method according to claim 3, characterized in that: the reversible limiter counter is composed of a reversible counter with a single clock input and a limiter and an addition and subtraction control circuit; the reversible counter has an addition and subtraction control input end and enable input. 8. The relay life detection method according to any one of claims 1 to 7, characterized in that: it consists of a controller unit, L on-off counting units, a man-machine interface unit, a relay drive unit, and an oscillator unit. device implementation; The man-machine interface unit is electrically connected to the controller unit for issuing detection commands and displaying the lifespan of the L relay switches; the controller unit is electrically connected to the relay driving unit, and sends a relay driving signal to the relay driving unit to control the L relays The on-off of the switch; the oscillator unit outputs the sampling clock pulse to the L on-off count units; the L on-off count units respectively count the on-off of the L relay switches to obtain L on-off count values; It is connected to the controller unit, and is used for the controller unit to read in the on-off count values of the L on-off count units and control the clearing of the on-off count values of the L on-off count units. 9 . The relay life detection method according to claim 8 , wherein the on-off counting unit is electrically connected to the controller unit for the controller unit to read in the on-off count values of the L on-off counting units respectively. 10 . The method is that the on-off count values of the L on-off counting units are output in tri-state buffer mode; the tri-state buffer output ports of all on-off counting units are all connected in parallel to the count data input ports of the controller unit; The on-off control signal enables the three-state buffer output ports of each on-off count unit one by one, and reads the corresponding on-off count value from the count data input port. 10. The relay life detection method according to claim 9, characterized in that: the device further comprises a gating control unit; the controller unit sends an on-off counting unit address coding signal to the gating control unit, and the gating control unit sends Decoding the address coding signal of the on-off counting unit to obtain the gating control signal.

Images