CN110658447A

CN110658447A - Relay service life detection method

Info

Publication number: CN110658447A
Application number: CN201910978796.0A
Authority: CN
Inventors: 凌云; 文定都; 王兵; 罗学明
Original assignee: Hunan University of Technology
Current assignee: Hunan University of Technology
Priority date: 2017-11-16
Filing date: 2017-11-16
Publication date: 2020-01-07
Anticipated expiration: 2037-11-16
Also published as: CN107976626A; CN107976626B; CN110658447B

Abstract

A method for detecting the service life of a relay is realized by a device comprising a controller unit, L on-off counting units, a human-computer interface unit, a relay driving unit and an oscillator unit, the on-off times of a plurality of relay switches can be counted simultaneously to obtain on-off counting values, and whether the relay and the switches thereof are invalid or not is judged according to the on-off counting values; the anti-pulse interference circuit in the on-off counting unit can filter out edge jitter interference and narrow pulse interference in counting pulses, so that the accuracy of the detection of the service life of the relay is ensured; the mode that a plurality of counters are arranged outside the controller unit and count the on-off times of the relay switch respectively is adopted, and the number of the relay switches for detecting the service life of the relay is not limited by the number of the counters inside the controller unit.

Description

Relay service life detection method

The invention relates to a relay service life detection device, which is a divisional application with an original application number of 201711133937.6 and an application date of 2017, 11 and 16.

Technical Field

The invention relates to the field of test methods and devices, in particular to a relay service life detection method.

Background

The service life of the relay is generally between tens of thousands to hundreds of thousands. The service condition of the relay is simulated, the relay is controlled to be switched on and off to generate electric pulses, and then the electric pulses are counted, so that the service life of the relay can be tested. The electrical pulses generated by the relay action contain edge jitter, and the unprocessed pulses are directly counted, so that a great error is generated. The software delay mode of the MCU can lead the MCU to be unconscious when the MCU needs to test the service life of a plurality of relay switches at the same time.

Disclosure of Invention

In order to solve the above problem, the present invention provides a method for detecting a life of a relay, including:

step 1, initializing, namely setting detection marks of L relay switches to be in a detection state, clearing 0 a service life counter, and sending a clear 0 signal to enable all L on-off count values to be clear 0;

step 2, controlling the on-off of the L relay switches once, and simultaneously counting the on-off times of the L relay switches respectively to obtain L on-off count values; the service life counter counts by adding 1;

step 3, reading current L on-off count values;

step 4, judging whether the relay switches with the detection marks in the detection states are invalid one by one; setting the detection mark which is judged as the failure relay switch at this time to be in a stop detection state, and taking the count value of the current life counter as the life value of the relay switch which is judged as the failure at this time;

and 5, returning to the step 2 if the detection marks of the L relay switches are still in the detection state, otherwise, stopping detection.

Judging whether the relay switch with the detection mark in the detection state is invalid or not, wherein the method is that when the current on-off count value accumulated for W times of the relay switch to be judged is not in the relationship of increasing 1 with the previous on-off count value, the relay switch is invalid, otherwise, the relay switch is not invalid; and W is an integer greater than or equal to 2.

The on-off times of the L relay switches are respectively counted, and the counting is realized by L on-off counting units with the same structure and composition; the on-off counting unit comprises a pulse generating circuit, an anti-pulse interference circuit and a tri-state output counting circuit. The pulse generating circuit outputs an initial pulse generated by the on-off of the relay switch to the anti-pulse interference circuit; the anti-pulse interference circuit performs pulse filtering on the initial pulse and outputs a counting pulse; the tri-state output counting circuit counts the counting pulse and outputs an on-off counting value.

The anti-pulse interference circuit comprises a reversible amplitude limiting counter, a comparison threshold value setter, an upper limit value comparator, a lower limit value comparator and an RS trigger. The input of the reversible amplitude limiting counter is an initial pulse and a sampling clock pulse, and the output is an amplitude limiting accumulated count value for counting the sampling clock pulse; the output of the comparison threshold value setter is an upper comparison threshold value and a lower comparison threshold value; the input of the upper limit value comparator is an amplitude limiting accumulated count value and an upper limit comparison threshold value, and the output is a first setting signal; the input of the lower limit value comparator is an amplitude limiting accumulated count value and a lower limit comparison threshold value, and the output is a second set signal; the input of the RS trigger is a first set signal and a second set signal, and the output is a counting pulse; the lower limit amplitude of the amplitude limiting accumulated count value is 0, and the upper limit amplitude is N; n is an integer greater than or equal to 2; the upper limit comparison threshold value is an integer which is greater than N/2 and less than or equal to N, and the lower limit comparison threshold value is an integer which is greater than or equal to 0 and less than N/2.

The function of the reversible amplitude limiting counter is that the level state of the initial pulse controls the reversible amplitude limiting counter to be in an up-counting state or a down-counting state; when the reversible amplitude limiting counter is in an up-counting state and the amplitude limiting accumulated count value is greater than or equal to the upper limit amplitude value N, the sampling clock pulse is not up-counted; when the reversible amplitude limiting counter is in a count-down state and the amplitude limiting accumulated count value is equal to the lower limit amplitude value 0, the sampling clock pulse is not counted down.

The upper limit value comparator has the function that when the input amplitude limiting accumulated count value is larger than or equal to the upper limit comparison threshold value, the first setting signal is enabled, otherwise, the first setting signal is disabled; the lower limit value comparator is used for enabling the second set signal when the input amplitude limiting accumulated count value is smaller than or equal to the lower limit comparison threshold value, and enabling the second set signal to be invalid otherwise.

The first setting signal is a setting signal of an RS trigger, and the second setting signal is a reset signal of the RS trigger; the counting pulse is output from the non-inverting output terminal of the RS flip-flop or is output from the inverting output terminal of the RS flip-flop.

The reversible amplitude limiting counter consists of a reversible counter with single clock input and an amplitude limiting and adding and subtracting control circuit; the up-down counter has an up-down control input and an enable input.

The relay service life detection method is realized by a relay service life detection device comprising a controller unit, L on-off counting units, a human-computer interface unit, a relay driving unit and an oscillator unit. The human-computer interface unit is electrically connected to the controller unit and used for sending out a detection command and displaying the service life of the L relay switches; the controller unit is electrically connected to the relay driving unit and sends a relay driving signal to the relay driving unit to control the on-off of the L relay switches; the oscillator unit outputs sampling clock pulses to the L on-off counting units; the L on-off counting units respectively count the on-off of the L relay switches to obtain L on-off counting values; the on-off counting unit is electrically connected to the controller unit and used for respectively reading on-off counting values of the L on-off counting units and controlling the clear 0 of the on-off counting values of the L on-off counting units by the controller unit.

The on-off counting unit is electrically connected to the controller unit, and the method for the controller unit to respectively read in the on-off counting values of the L on-off counting units is that the on-off counting values of the L on-off counting units are all output in a three-state buffer mode; the tri-state buffer output ports of all the on-off counting units are all connected in parallel to the counting data input port of the controller unit; the controller unit sends out gating control signals to enable the three-state buffer output ports of the on-off counting units one by one, and corresponding on-off counting values are read in from the counting data input port.

The relay service life detection device also comprises a gating control unit; the controller unit sends an address coding signal of the on-off counting unit to the gating control unit, and the gating control unit decodes the address coding signal of the on-off counting unit to obtain a gating control signal.

The invention has the beneficial effects that: the method can detect the service lives of a plurality of relay switches simultaneously; the method comprises the following steps that an anti-pulse interference circuit is adopted to automatically filter edge jitter interference and narrow pulse interference in electric pulses generated by the on-off of a relay switch, and the effect of filtering the pulse interference can be adjusted by changing the size of an upper limit amplitude of an amplitude limiting accumulated count value or changing the size of an upper limit comparison threshold and a lower limit comparison threshold; the accuracy of the service life detection of the relay and the switch is ensured; the mode that a plurality of counters are arranged outside the controller unit and count the on-off times of the relay switch respectively is adopted, and the number of the relay switches for detecting the service life of the relay is not limited by the number of the counters inside the controller unit.

Drawings

Fig. 1 is a block diagram of an embodiment of a relay life detection device when L is 4 in fig. 1;

FIG. 2 is an embodiment of an on-off counting unit;

fig. 3 is an embodiment of an invertible slicing counter when N is 6;

fig. 4 shows an embodiment of the comparison threshold setter when N is 6;

fig. 5 shows an embodiment of the upper limit comparator when N is 6;

fig. 6 is an embodiment of the lower limit value comparator when N is 6;

FIG. 7 is an RS flip-flop embodiment;

FIG. 8 shows an embodiment of a 1# pulse generating circuit;

fig. 9 is a schematic diagram of an anti-interference effect of the anti-glitch circuit when N is 6;

FIG. 10 is a tri-state output counting circuit embodiment;

fig. 11 is a relay drive unit embodiment.

Detailed Description

The invention is further described below with reference to the accompanying drawings.

Fig. 1 is a block diagram of an embodiment of a relay life detection device when L is 4, and includes a controller unit 10, a 1# on-off counting unit 11, a 2# on-off counting unit 12, a 3# on-off counting unit 13, a 4# on-off counting unit 14, a human-machine interface unit 15, a gating control unit 16, a relay driving unit 17, and an oscillator unit 18.

The human-machine interface unit 15 communicates with the controller unit 10 through an interface I/O1 of the controller unit 10, and is used for detecting issuance of commands, parameter modification, display of the service life of each relay switch, and the like; the controller unit 10 sends a relay driving signal to the relay driving unit 17 through an output port OUT2 to control the on-off of the 1# to 4# relay switches; the oscillator unit 18 outputs sampling clock pulses CP1 to the # 1 on-off counting unit 11, the # 2 on-off counting unit 12, the # 3 on-off counting unit 13, and the # 4 on-off counting unit 14; the 1# on-off counting unit 11, the 2# on-off counting unit 12, the 3# on-off counting unit 13 and the 4# on-off counting unit 14 respectively perform pulse generation, pulse filtering and on-off frequency counting on the on-off of 4 relay switches; the controller unit 10 sends an address coding signal of an on-off counting unit to be gated to the gating control unit 16 through an output port OUT1, the gating control unit 16 decodes the address coding signal of the on-off counting unit to obtain gating control signals CS1, CS2, CS3 and CS4, and on-off count values CV1, CV2, CV3 and CV4 of the 1# on-off counting unit 11, the 2# on-off counting unit 12, the 3# on-off counting unit 13 and the 4# on-off counting unit are respectively controlled to be sent to the controller unit 10 through an input port IN1, and the IN1 is a counting data input port of the controller unit; the controller unit 10 sends a clear 0 signal CLR to the 1# on-off counting unit 11, the 2# on-off counting unit 12, the 3# on-off counting unit 13 and the 4# on-off counting unit 14 through an output port OUT 3; when the clear 0 signal CLR is effective, the on-off counting values of the 4 on-off counting units are all cleared by 0.

Fig. 2 is a block diagram of an embodiment of a 1# on-off counting unit. In fig. 2, the 1# pulse generating circuit 100 outputs an initial pulse P1 generated by turning on and off the 1# relay switch; an interference pulse filtering circuit is formed by a reversible amplitude limiting counter 101, a comparison threshold value setter 102, an upper limit value comparator 103, a lower limit value comparator 104 and an RS trigger 105, pulse filtering is carried out on the initial pulse P1, and a counting pulse P2 is output; the tri-state output counting circuit 106 counts the counting pulse P2, is controlled by a gating control signal CS1 and outputs an on-off counting value CV1 of the 1# relay switch; the tri-state output counting circuit 106 is simultaneously controlled by the clear 0 signal CLR, and when the clear 0 signal CLR is effective, the on-off counting value in the tri-state output counting circuit 106 is cleared by 0.

In the anti-glitch circuit of fig. 2, the input of the up-down limiter counter 101 is the initial pulse P1 and the sampling clock CP1, and the output is the limiter accumulated count value X1, the upper limit amplitude of the limiter accumulated count value X1 is N, and the lower limit amplitude is 0; the output of the comparison threshold setter 102 is an upper comparison threshold Y1 and a lower comparison threshold Y2; the input of the upper limit value comparator 103 is a clipping accumulated count value X1 and an upper limit comparison threshold value Y1, and the output is a first set signal SE 1; the input of the lower limit value comparator 104 is the clipping accumulated count value X1 and the lower limit comparison threshold value Y2, and the output is the second set signal RE 1; the RS flip-flop 105 has inputs of a first set signal SE1 and a second set signal RE1, and an output of a count pulse P2.

In the following embodiments of the anti-glitch circuit, N is 6.

Fig. 3 shows an embodiment of the up-down clipping counter when N is 6. In fig. 3, FC1 is a 4-bit binary up-down counter 74HC191, the set control input LD input 1 of FC1, FC1 operates in a controllable up-down counting state, and is an up-down counter with a single clock input; the M input of FC1 is the add-subtract control input and the CE input is the enable control input. The NAND gates FA1, FA2, FA3 and FA4 form an amplitude limiting and adding and subtracting control circuit. The level states of the initial pulse include a high level and a low level, in the embodiment of fig. 3, the P1 is connected to the add/subtract control input terminal M through the nand gate FA4, and the high level state and the low level state of the initial pulse P1 control the reversible slice counter to be in the up-counting state and the down-counting state respectively. Alternatively, P1 can be directly connected to the up/down control input terminal M, so that the high level and the low level of the initial pulse P1 can control the up/down counter to be in the down-counting state and the up-counting state, respectively.

When P1 is 1 and x13 and x12 are 1 at the same time, the nand gate FA1 outputs low level, the nand gate FA3 outputs high level, the enable control end CE of FC1 inputs high level, and 74HC191 works in a hold state, that is, the inverse slice counter maintains the output state unchanged at the rising edge of the sampling clock pulse CP1, the inverse slice counter is in an upper limit value slice state, and no count-up is performed; the condition that x13 and x12 are 1 simultaneously comprises 2 conditions, and when x13, x12 and x11 are 1, 1 and 0, the output of the reversible limiting counter is equal to the upper limit amplitude value of 6; when x13, x12 and x11 are 1, 1 and 1, the output of the reversible amplitude limiting counter is equal to 7, the reversible amplitude limiting counter is in an overrun state, the output of the reversible amplitude limiting counter is in the overrun state, the output of the reversible amplitude limiting counter cannot be in the overrun state after the reversible amplitude limiting counter enters a normal amplitude limiting counting interval after counting down. When P1 is 0 and x13, x12 and x11 are 0 at the same time, the nand gate FA2 outputs low level, the nand gate FA3 outputs high level, the enable control end CE of FC1 inputs high level, and 74HC191 operates in a hold state, that is, the inverse slice counter maintains the output state at the rising edge of the sampling clock CP1, the inverse slice counter is in a lower limit slice state, and the count down is not performed. The initial pulse P1 has 2 states of high level and low level, i.e., the initial pulse P1 has 2 states of 1 and 0, and the two states of the initial pulse P1 control the up-down counter to count or down-count the sampling clock pulse CP1, respectively. When P1 is 1 and x13 and x12 are not 1 at the same time, both the nand gates FA1 and FA2 output high level, the nand gate FA3 outputs low level, the enable control end CE of FC1 inputs low level, the P1 inputs low level to the add-subtract control end M through the nand gate FA4, 74HC191 operates in an up-counting state, and the up-down limiter counter performs up-counting on the rising edge of the sampling clock pulse CP 1. When P1 is 0 and x13, x12 and x11 are not 0 at the same time, the nand gates FA1 and FA2 both output high level, the nand gate FA3 outputs low level, the enable control end CE of the FC1 inputs low level, the add-subtract control end M inputs high level, the 74HC191 operates in the count-down state, and the reversible limiter counter performs count-down on the rising edge of the sampling clock pulse CP 1. 74HC191 is a synchronous binary counter, which controls whether to count and whether to count up or down only in the state of the rising edge time P1 of the sampling clock pulse CP1 inputted from its clock input end CP; at the non-rising edge time of the CP1, the P1 causes the change of the enable control terminal CE and the add-subtract control terminal M to not affect the x13, x12, and x11 output by the 74HC 191. During the period when the clock input end CP is low, the P1 causes the change of the enable control end CE and the add/subtract control end M to affect the carry/borrow signal of the 74HC191, and in the embodiment of fig. 3, the carry/borrow signal of the 74HC191 is not used, so that the effect is not affected. The output of the inverse limiting counter is controlled and changed by the value of P1 at the rising edge moment of the sampling clock pulse, namely, the output of the inverse limiting counter is related to the sampling value at the rising edge moment of the sampling clock pulse P1 and is controlled by the sampling value at the rising edge moment of the sampling clock pulse P1. The output of the up-down clipping counter may also be controlled to change by the value of P1 at the time of the falling edge of the sampling clock pulse.

When N is other number, the number of nand gates for performing count and slice control in fig. 3 can be increased or decreased, and the number of input signals of each nand gate can be increased or decreased. The function of the reversible clipping counter can also be implemented by other devices or circuits, for example, 74HC191 is replaced by 74HC190, CD4516, etc., or a synchronous reversible counter is formed by flip-flops and gates.

Fig. 4 shows an embodiment of the comparison threshold setter when N is 6. In fig. 4, + VCC is a power supply, GND is a common ground, and resistors R91, R92, R93 and switches K91, K92, K93 constitute an upper limit comparison threshold Y1 setting circuit; when the K91, the K92 and the K93 are respectively in an open state, a closed state and a open state, the upper limit comparison threshold Y1 output by the comparison threshold setter is 5, and the 3-bit binary outputs Y13, Y12 and Y11 of the comparison threshold setter are 1, 0 and 1. A lower limit comparison threshold Y2 setting circuit is formed by the resistors R94, R95 and R96 and the switches K94, K95 and K96; when the K94, the K95 and the K96 are respectively in the closed state, the closed state and the open state, the lower comparison threshold Y2 output by the comparison threshold setter is 1, and the 3-bit binary outputs Y23, Y22 and Y21 are 0, 0 and 1. The comparison threshold setter can also be composed of a binary dial switch, or a BCD dial switch, or a plurality of pull-up resistors and circuit short-circuit points for controlling 0 and 1 outputs, and other circuits capable of outputting multi-bit binary set values.

The upper limit value comparator is used for enabling the first set signal when the input amplitude limiting accumulated count value is larger than or equal to the upper limit comparison threshold value, and enabling the first set signal to be invalid otherwise. Fig. 5 shows an embodiment of the upper limit comparator when N is 6, the upper limit comparator is composed of a four-digit binary value comparator FC2 and an or gate FO1, and FC2 is 74HC 85. The 3-bit binary outputs X13, X12 and X11 of the clipped accumulated count value X1 are respectively connected to the input terminals a2, a1 and a0 of the FC2, the 3-bit binary outputs Y13, Y12 and Y11 of the upper limit comparison threshold Y1 are respectively connected to the input terminals B2, B1 and B0 of the FC2, and the input terminals A3 and B3 are respectively input with 0. The inputs a > B IN and a < B IN of FC2 are both 0 inputs and the input a is B IN input 1. The output terminals a > B OUT, a ═ B OUT of the FC2 are connected to the input terminals of the or gate FO1, respectively, and the output terminal of the or gate FO1 is the first set signal SE 1. The upper limit value comparator in fig. 5 realizes a function that the output SE1 is high when the clip accumulated count value X1 is equal to or higher than the upper limit comparison threshold Y1, and otherwise SE1 is low. SE1 is active high in FIG. 5; changing or gate FO1 to nor gate, SE1 is active low.

The lower limit value comparator is used for enabling the second set signal when the input amplitude limiting accumulated count value is smaller than or equal to the lower limit comparison threshold value, and enabling the second set signal to be invalid otherwise. Fig. 6 shows an embodiment of the lower limit comparator when N is 6, the lower limit comparator is composed of a four-bit binary comparator FC3 and an or gate FO2, and FC3 is 74HC 85. The 3-bit binary outputs X13, X12 and X11 of the clipped accumulated count value X1 are respectively connected to the input ends A2, A1 and A0 of FC3, the 3-bit binary outputs Y23, Y22 and Y21 of the lower limit comparison threshold Y2 are respectively connected to the input ends B2, B1 and B0 of FC2, and the input ends A3 and B3 are both connected to 0. The input terminals a > B IN and a < B IN of FC3 are both connected to 0, and the input terminal a ═ B IN is connected to 1. The output terminals a < B OUT and a ═ B OUT of the FC3 are connected to the input terminal of the or gate FO2, respectively, and the output terminal of the or gate FO2 is the second set signal RE 1. The lower limit value comparator in fig. 6 realizes a function that the output RE1 is high when the clip accumulated count value X1 is equal to or less than the lower limit comparison threshold Y2, and otherwise SE1 is low. RE1 is active high in FIG. 6; the or gate FO2 is changed to a nor gate, then RE1 is active low.

When the value of N is large, 2 or more pieces of 74HC85 can be selected to form a multi-bit binary value comparator to realize the function of an upper limit value comparator or a lower limit value comparator; the function of the upper limit value comparator or the lower limit value comparator can also be realized by 1 or more four-bit binary value comparators CD4063, or by other combinational logic circuits.

Fig. 7 is an RS flip-flop embodiment. In fig. 7, the nor gates FO3 and FO4 constitute an RS flip-flop, the first set signal SE1 is a set signal of the RS flip-flop, and the second set signal RE1 is a reset signal of the RS flip-flop, both of which are active at high level; the count pulse P2 is output from the non-inverting output of the RS flip-flop, i.e., the output of FO 4. The count pulse P2 may also be output from the inverting output of the RS flip-flop, i.e., the output of the or gate FO 3. The RS flip-flop may also take other forms.

In the embodiment where N is 6, the upper comparison threshold Y1 is 5, and the lower comparison threshold Y2 is 1. When the clip accumulated count value X1 is equal to or greater than 5, the output SE1 is at a high level, and the count pulse P2 is set to 1; when the clip accumulated count value X1 is equal to or less than 1, the output RE1 is at a high level, and the count pulse P2 is set to 0.

FIG. 8 shows an embodiment of a 1# pulse generating circuit. The 1# relay switch KA1 is connected in series with the load resistor RA1 and then connected to the power supplies V1 and V2; the voltage reduction resistor R11 is connected in series with the bidirectional voltage regulator VD1 and then connected to two ends of the load resistor RA1 in parallel; u11 is a bidirectional input optocoupler, a current limiting resistor R12 is connected with a bidirectional light emitting diode at the input end of U11 in series and then connected to two ends of a bidirectional voltage regulator tube VD1 in parallel; the pull-up resistor R13 is a collector load resistor of the U11 output triode; the initial pulse P1 is output from the collector of the U11 output transistor. The AC/DC switch K11 is connected in series with the voltage-reducing capacitor C11 and then connected in parallel to two ends of the voltage-reducing resistor R11. In the embodiment of fig. 8, the relay switch KA1 is a normally open switch; the relay switch may also be a normally closed switch, for example, KA1 in the embodiment of fig. 8 may be replaced by a normally closed switch, and the rest of the circuit is maintained.

In fig. 8, when the test power supplies V1 and V2 are dc power supplies, V1 is positive and V2 is negative, or V1 is negative and V2 is positive, and the ac/dc switch K11 is turned off. When KA1 is off, there is no voltage across the load resistor RA1, the output transistor of U11 is turned off, and the initial pulse P1 is high. When the KA1 is switched on, the voltage on the load resistor RA1 is reduced by the R11 and stabilized by the VD1, the input diode of the U11 is controlled to emit light by the R12, the output triode of the U11 is in saturated conduction, and the initial pulse P1 is at a low level. KA1 is switched on and off once, and an initial pulse P1 outputs a pulse with a jittering narrow pulse interference at the edge.

In fig. 8, when the test power supplies V1 and V2 are ac power supplies, the positive and negative of V1 and V2 change alternately, and the ac/dc switch K11 is turned on. When KA1 is off, there is no voltage across the load resistor RA1, the output transistor of U11 is turned off, and the initial pulse P1 is high. When KA1 is switched on, alternating current voltage of a load resistor RA1, which is not zero-crossing point, is subjected to voltage reduction through R11 and voltage stabilization through VD1, an input diode of U11 is controlled to emit light through R12, an output triode of U11 is in saturated conduction, and an initial pulse P1 is at a low level; when the alternating voltage on the load resistor RA1 passes through zero, the voltage is low and is not enough to drive an input diode of U11 to emit light, an output triode of U11 is cut off, and the initial pulse P1 is at a high level; therefore, when KA1 is turned on, the initial pulse P1 is a pulse with more low level and less high level, or the initial pulse P1 is said to be low level at this time, but there is a positive narrow pulse interference; KA1 is switched on and off once, and an initial pulse P1 outputs a pulse with shaking narrow pulse interference and positive narrow pulse interference at the edge of a band.

The size of the load resistor RA1 can be changed, and the resistive load current of the relay switch KA1 to be detected can be adjusted. When the test power supplies V1 and V2 in fig. 8 are ac power supplies, the load resistor RA1 may be an inductive load or a capacitive load. The VD1 in FIG. 8 can also select a bidirectional TVS tube. When the test power supplies V1 and V2 are constantly direct current, the alternating current/direct current switch K11 and the voltage reduction capacitor C11 in FIG. 8 can be removed, the VD1 selects a unidirectional voltage regulator tube or a unidirectional TVS tube, and the U11 selects a unidirectional input optocoupler. When the power supply sources V1 and V2 are tested to be constantly alternating current, the alternating current/direct current switch K11 in fig. 8 can be removed, and the voltage reduction capacitor C11 is directly connected in parallel to two ends of the voltage reduction resistor R11. The pulse generating circuit may also adopt other forms of circuits than the circuit shown in fig. 8.

Fig. 9 is a schematic diagram of the anti-interference effect of the anti-glitch circuit when N is 6. In fig. 9, the sampled value P1 of the initial pulse P1, the sliced accumulated count value X1 of each sampled point, and the resultant count pulse P2 are shown for 15 sampling clock pulses CP 1. The sampling value P1 is the value of the initial pulse P1 when the sampling clock pulse CP1 counts edges; the up-counting or down-counting of the sampling clock pulse CP1 is performed by the up-down limiter counter controlled by the 2 states of the initial pulse P1, and the up-counting or down-counting of the sampling clock pulse CP1 is performed by the up-down limiter counter controlled by the value of the initial pulse P1 when the sampling clock pulse CP1 counts the edge. The clip accumulated count value X1 set before the sampling point 1 of CP1 in fig. 9 is 0, and the count pulse P2 is 0. In fig. 9, the initial pulse P1 shows positive pulse interference at sampling point 2 of CP1, resulting in that X1 samples at sampling point 2 to obtain interference value 1 of P1 ×; the initial pulse P1 shows positive narrow pulse interference between sample point 4 and sample point 5 of CP1, but the positive narrow pulse width is smaller than the sampling period and between 2 sample points, and the sampling result P1 is not affected, i.e. the sampling process automatically filters out the positive narrow pulse interference. The initial pulse P1 changes from 0 to 1 after the sampling point 6 of CP1, and 2 times of edge jitter (or positive narrow pulse interference and edge jitter) occurs in the process of changing from 0 to 1, where the 2 nd positive narrow pulse jitter interference is automatically filtered by the sampling process, and the values of the sampling point 7 and the sampling point 8 are 1 and 0, respectively. In fig. 9, the sample value P1, the count pulse P2, and the clip accumulated count value X1 obtained from sample point 1 to sample point 15 of the clock CP1 are shown in table 1.

Table 1 sample points 1-15, sample value P1, clip count cumulative value X1, and count pulse P2

Observing the condition of the sampling points in table 1, at sampling points 1-9, X1 is less than or equal to Y2, RE1 is valid, SE1 is invalid, and P2 is set to 0; at sampling points 10-12, X1 is greater than Y2 and less than Y1, both SE1 and RE1 are inactive, and P2 remains 0; at sample points 13-15, X1 is equal to or greater than Y1, SE1 is active, RE1 is inactive, and P2 is set to 1. When N is 6, the counting interval of the reversible amplitude limiting counter is 0-N; at sample 3 in table 1, X1 has reached the lower limit amplitude of 0, at samples 4-6, P1 ═ 0 (i.e., at this time, P1 ═ 0), X1 is also not counted down, and X1 is maintained at the lower limit amplitude of 0; at sample 14, X1 has reached the upper limit amplitude of 6, at sample 15, P1 ═ 1 (i.e., at this time, P1 ═ 1), X1 is also not counted up, and X1 remains at the upper limit amplitude of 6. At sampling points 1-8, the initial pulse P1 is in a low level state output by the pulse generating circuit, and is a pulse with more low level ratio and less high level ratio, that is, the middle part contains some positive narrow pulse interferences, but because the low level holding time of the initial pulse P1 in the interval is far longer than the time occupied by the positive narrow pulse interferences, the positive narrow pulse interferences do not influence the change interval of the amplitude-limiting accumulated count value X1 as a whole, and X1 is maintained to change between 0 and 1; even if the influence of the positive and narrow-pulse interference is still larger, as long as the time occupied by the positive and narrow-pulse interference is smaller than the low-level holding time, the clip accumulated count value X1 does not exceed N/2, and it is more difficult to reach Y1 or more, and the state of the count pulse P2 is not changed. Fig. 9 shows the anti-positive pulse interference effect of the interference pulse filtering circuit when the initial pulse P1 is 0, and the condition and process of the initial pulse P1 changing from 0 to 1. The interference pulse filtering circuit has the same anti-negative pulse interference effect when the initial pulse P1 is 1, the same conditions and processes of changing the initial pulse P1 from 1 to 0, the same anti-positive pulse interference effect when the initial pulse P1 is 0, and the same conditions and processes of changing the initial pulse P1 from 0 to 1. Similarly, when some negative glitches are included in the middle of the high state of the initial pulse P1, and the high hold time of the initial pulse P1 is longer than the time occupied by the negative glitches during this period, the slice accumulated count value X1 is not less than N/2, is more difficult to be equal to or less than Y2, and does not change the state of the count pulse P2.

The clip accumulated count value X1 set before the sampling point 31 of the clock CP1 is 6, and the count pulse P2 is 1. The sample value P1, the clipped cumulative count value X1 and the count pulse P2 from sample point 31 to sample point 45 are shown in table 2.

Sample values P1, clipped cumulative count X1 and count pulses P2 of samples 31-45 of table 2

Observing the conditions of the sampling points in the table 2, wherein X1 is greater than or equal to Y1, SE1 is effective, RE1 is ineffective, and P2 is set to be 1 at the sampling points 31-32; at sample point 33, X1 is greater than Y2 and less than Y1, both SE1 and RE1 are inactive, and P2 remains 1; at a sampling point 34, X1 is greater than or equal to Y1, SE1 is effective, RE1 is ineffective, and P2 is set to be 1; at sample points 35-39, X1 is greater than Y2 and less than Y1, neither SE1 nor RE1 is effective, and P2 remains 1; because the sampling value P1 is in the state of more than 0 and less than 1 between the sampling points 31-40, the accumulated counting result of the reversible amplitude limiting counter is that the accumulated counting value X1 of the amplitude limiting tends to decrease until the sampling point 40, X1 is less than or equal to Y2, RE1 is effective, SE1 is ineffective, and P2 is set to 0; at sample point 41, X1 is greater than Y2 and less than Y1, both SE1 and RE1 are inactive, P2 remains 0; at sampling points 42-45, X1 is less than or equal to Y2, RE1 is active, SE1 is inactive, and P2 is set to 0. At sample 43 in table 2, X1 has reached the lower limit amplitude of 0, and at samples 44-45, P1 ═ 0 (i.e., at this time, P1 ═ 0), X1 is also not counted down, and X1 is maintained at the lower limit amplitude of 0.

In the present embodiment, where N is 6, the counting pulse P2 is in phase with the initial pulse P1. If the function of the up-down clipping counter is changed to: when P1 is equal to 1, the reversible amplitude limiting counter counts down; when P1 is equal to 0, the up-down limiter counter counts up, and the counter pulse P2 and the initial pulse P1 are in an inverse correlation. Alternatively, in fig. 7, the counting pulse P2 is output from the nor gate FO3 instead, and the counting pulse P2 and the initial pulse P1 are inversely related. If the above modification is performed simultaneously, the counting pulse P2 and the initial pulse P1 are in phase.

Taking the in-phase relationship between the counting pulse P2 and the initial pulse P1 as an example, it can be concluded from tables 1 and 2 and the working principle of the circuit that since the reversible clipping counter has an accumulation effect, when the number of 1's in the sampling value of the initial pulse P1 is greater than 0 within a period of time, the clipped accumulated count value X1 tends to increase, so that X1 is greater than or equal to Y1 and the counting pulse P2 is set to 1; when the number of 0's is more than 1 in the sampling values of the initial pulse P1 within a period of time, the clipped cumulative count value X1 tends to decrease, X1 is less than or equal to Y2 and the count pulse P2 is set to 0; the characteristic enables the amplitude limiting counting unit of the circuit of the invention to have self-starting capability, amplitude limiting function and the amplitude limiting counting unit to enter a normal amplitude limiting counting interval to carry out amplitude limiting addition and subtraction counting when 0 in a sampling value P1 of an initial pulse P1. When the initial clipped cumulative count value X1 is greater than N and is in an overrun state, X1 is greater than or equal to the upper comparison threshold value Y1, SE1 output by the upper limit comparator is enabled, RE1 output by the lower limit comparator is disabled, and P2 is set to 1.

Since the upper comparison threshold Y1 is an integer greater than N/2 and equal to or less than N and the lower comparison threshold Y2 is an integer greater than 0 and equal to or less than N/2, the first set signal SE1 and the second set signal RE1 cannot be simultaneously asserted, and thus the output of the RS flip-flop is not indeterminate in logic state.

The counting pulse P2 and the initial pulse P1 are in phase, for example. When the initial pulse P1 makes the clip accumulated count value X1 less than or equal to the lower limit comparison threshold Y2 and the count pulse P2 is set to 0, the count pulse P2 does not become 1 as long as the clip accumulated count value X1 is always less than the upper limit comparison threshold Y1; when the initial pulse P1 makes the clip accumulated count value X1 equal to or greater than the upper limit comparison threshold Y1 and the count pulse P2 becomes 1, the count pulse P2 does not become 0 as long as the clip accumulated count value X1 is always greater than the lower limit comparison threshold Y2. When both P1 and P2 are low, as long as a positive pulse appearing in P1 causes values of 1 to continuously appear in Y1 or more in the P1 sample value, or a value of 1 to continuously appear in Y1+1 in the continuous Y1+ 2P 1 sample values, or the like, a positive pulse corresponding to the positive pulse in P1 can be output from P2; when both P1 and P2 are at a high level, a negative pulse corresponding to the negative pulse in P1 can be output from P2, as long as the negative pulse in P1 causes N-Y2 consecutive sampled values to have 0 values in the P1, or N-Y2+1 consecutive sampled values in the N-Y2+ 2P 1, and so on. When the initial pulse P1 changes from 0 to 1, the counting pulse P2 needs the clip accumulated count value X1 to be delayed by the counting of several sampling pulse periods, so that the clip accumulated count value X1 is greater than or equal to the upper limit comparison threshold Y1, and P2 is set to 1; when the initial pulse P1 changes from 1 to 0, the count pulse P2 needs the clip accumulated count value X1 to be delayed by counting down for several sampling pulse periods, so that the clip accumulated count value X1 is less than or equal to the lower limit comparison threshold Y2, and P2 is set to 0. When the value of the upper limit comparison threshold value Y1 is larger, the condition that the counting pulse P2 is changed from 0 to 1 is more rigorous, and the low-level positive pulse interference resisting effect of the circuit is better; when the value of the lower limit comparison threshold value Y2 is smaller, the condition that the counting pulse P2 is changed from 1 to 0 is more rigorous, and the high-level negative pulse interference resisting effect of the circuit is better. When the value of N is larger, the interference pulse filtering circuit strictly changes the conditions of changing the counting pulse P2 from 0 to 1 and changing the counting pulse P2 from 1 to 0, the interference resistance effect is better, but the delay time of the counting pulse P2 relative to the initial pulse P1 is larger; when the value of N becomes small, the interference pulse filter circuit widens the conditions that the count pulse P2 changes from 0 to 1 and from 1 to 0, and the interference suppression effect becomes small, but the delay time of the count pulse P2 with respect to the initial pulse P1 becomes small.

Fig. 10 is a tri-state output counting circuit embodiment. Fig. 10(a) shows tristate output counting circuit embodiment 1, which is composed of counter FC4 and not gate FN1, and FC4 is 8-bit binary counter 74HC590 with tristate output. The count permission end CCKEN of the FC4 inputs 0, and the clear 0 control end CCLR is a clear 0 signal CLR input end of the tri-state output counting circuit; when the clear 0 signal CLR is active at a low level, that is, the clear 0 signal CLR output by the controller unit is at a low level, the on-off count value in the counter FC4 is cleared by 0; when the clear 0 signal CLR output by the controller unit is at a high level, the FC4 operates in an up-counting state, the counting pulse P2 is directly connected to the counting pulse input end CCK of the FC4, and the FC4 counts by 1 at the rising edge of the counting pulse P2 to obtain an on-off count value. The count pulse P2 is connected to the FC4 data latch RCK through the not gate FN1, and the content of the counter inside the FC4 is latched to the output latch at the falling edge of the count pulse P2. When the gate control signal CS1 is connected to the output enable control terminal G of the FC4 and CS1 is low, the FC4 outputs the on-off count value CV1 in the output latch from Q7 to Q0; when CS1 is at high level, Q7-Q0 of FC4 are in high-impedance state. The on-off count value output by the tri-state output counting circuit embodiment 1 is an 8-bit binary count value.

Fig. 10(b) shows tristate output counting circuit embodiment 2, which is composed of counter FC5 and tristate buffer FB1, FC5 is 4-bit binary counter 74HC161, FB1 is tristate buffer 74HC 244. Count control ends CTP and CTR of FC5 and a count control end LD are connected to 1, and a clear 0 control end CR is a clear 0 signal CLR input end of the tri-state output counting circuit; when the clear 0 signal CLR is active at a low level, that is, the clear 0 signal CLR output by the controller unit is at a low level, the on-off count value in the counter FC5 is cleared by 0; when the clear 0 signal CLR output by the controller unit is at a high level, the FC5 operates in an up-counting state, the counting pulse P2 is directly connected to the counting pulse input end CP of the FC5, and the FC5 counts by 1 at the rising edge of the counting pulse P2 to obtain an on-off count value. The 4-bit data input ends A3-A0 of the tristate buffer FB1 are respectively connected to the 4-bit count value output ends Q3-Q0 of the counter FC5, the gating control signal CS1 is connected to the output enabling control end 1G of the FB1, and when the CS1 is at a low level, the FB1 outputs the on-off count value CV1 output by the counter FC5 from Y3-Y0; when CS1 is at high level, Y3-Y0 of FB1 are in high-impedance state. The on-off count value output by the tri-state output counting circuit embodiment 2 is a 4-bit binary count value.

In the embodiment of the relay service life detection device when L is 4, the 2# on-off counting unit, the 3# on-off counting unit and the 4# on-off counting unit adopt the same circuit composition and structure as the 1# on-off counting unit, namely all the on-off counting units comprise a pulse generating circuit, an anti-pulse interference circuit and a tri-state output counting circuit; the pulse generating circuit, the anti-pulse interference circuit and the tri-state output counting circuit have the same composition and structure.

Fig. 11 is a relay drive unit embodiment. Fig. 11(a) shows an embodiment of a relay coil powered by a dc power supply, which comprises a transistor VT, a freewheeling diode VD, and a base resistor R61; the coil of the relay to be detected is connected in parallel with the nodes A1 and A2, and the direct current power supply of the coil of the relay is + V. Assuming that 4 relay switches in the embodiment of fig. 1 are included in 2 relays, only 2 relay coils J1, J2 are connected in parallel in fig. 11 (a). When a relay driving signal C1 sent by the controller unit is in a high level, all relay coils connected in parallel on the nodes A1 and A2 are electrified; when the relay driving signal C1 sent by the controller unit is in a low level, all the relay coils connected in parallel on the nodes A1 and A2 lose power; when the relay driving signal C1 sent by the controller unit changes one pulse period, the relay switches of all the relays connected with the coils in parallel at the nodes A1 and A2 are switched on and off once. When the number of the relay coils is large and the transistor VT in fig. 11(a) is not fully driven, the same or similar driving circuit may be added to expand the driving capability.

Fig. 11(b) is an embodiment of a relay coil powered by an ac power supply, and is composed of a current-driven solid-state relay SSR1, a voltage dependent resistor RU1, and a current limiting resistor R62; the coil of the relay to be detected is connected in parallel with the nodes B1 and B2, and the alternating current power supply of the coil of the relay is AC 0; + VCC is the current driven power supply of the SSR 1. Assuming that 4 relay switches in the embodiment of fig. 1 are included in 2 relays, only 2 relay coils J3, J4 are connected in parallel in fig. 11 (b). When a relay driving signal C2 sent by the controller unit is in a low level, all relay coils connected in parallel on the nodes B1 and B2 are electrified; when a relay driving signal C2 sent by the controller unit is in a high level, all relay coils connected in parallel on the nodes B1 and B2 lose power; when the relay driving signal C2 sent by the controller unit changes one pulse period, the relay switches of all the relays with the coils connected in parallel at the nodes B1 and B2 are switched on and off once. When the number of the relay coils is large and the solid-state relay SSR1 in fig. 11(b) is not enough to be driven completely, the same or similar driving circuit can be added to expand the driving capability.

When the relay coil using the dc power supply and the relay coil using the ac power supply exist in the relay where the L relay switches are located, the circuits in fig. 11(a) and fig. 11(b) can be used for classified driving. The relay drive unit may also employ other circuits as desired.

The oscillator unit is used to output a sampling clock pulse CP1, and any one of various multivibrators may be selected to constitute the oscillator unit. During testing, the frequency of the on-off of the relay switch is usually between 10 times/min and 30 times/min, the initial pulse comes from the on-off control output of the relay switch, the high level and the low level of the formed pulse are close to or more than 1000ms in width, therefore, the period of the sampling clock pulse CP1 can be selected between 8ms and 48ms, and because the period of the interference of the positive narrow pulse in the P1 is 10ms, the sampling clock pulse CP1 should be avoided to be an integral multiple of 10ms, and N is a value in the range of 5 to 10.

The human-computer interface unit preferably uses a touch screen and adopts RS485 or RS232 to communicate with the controller unit. The man-machine interface unit can also be optionally composed of a key circuit and a liquid crystal display.

The on-off count values of all the on-off counting units are output in a tri-state buffering mode; all the tri-state buffer output ports of all the on-off counting units are connected in parallel to the counting data input port of the controller unit, the controller unit sends out gating control signals to enable the tri-state buffer output ports of all the on-off counting units respectively, and on-off counting values output by the enabled tri-state buffer output ports are read in from the counting data input port. The on-off count value in the embodiment 1 of the tri-state output counting circuit is 8-bit binary data, and a tri-state buffer output port of the on-off counting unit and a counting data input port of the controller unit are 8-bit parallel ports; the on-off count value in the tri-state output counting circuit embodiment 2 is 4-bit binary data, and the tri-state buffer output port of the on-off counting unit and the counting data input port of the controller unit are both 4-bit parallel ports. When the L value is small and the number of digits of the on-off counting value is small, the on-off counting value of the on-off counting unit can be output without adopting a three-state buffer mode, and the output ports of the on-off counting value of each on-off counting unit are respectively and directly connected to different parallel ports of the controller unit; for example, when L is 4 and the on-off count value is a 4-bit binary value, the on-off count value output ports of the 4 on-off count units are directly connected to different parallel ports of the controller unit, and only 16-bit I/O port lines, that is, 2 8-bit input ports, in total need to be consumed by the controller unit.

The controller unit sends out gating control signals through the gating control unit. The gating control unit is a decoder circuit and decodes the on-off counting unit address coding signal sent by the controller unit to obtain a gating control signal. In the embodiment of fig. 1, the on-off counting unit address encoding signals corresponding to the 1# on-off counting unit 11, the 2# on-off counting unit 12, the 3# on-off counting unit 13 and the 4# on-off counting unit are binary 00, 01, 10 and 11 respectively, and are decoded and output as CS1, CS2, CS3 and CS 4; the controller unit enables CS1, CS2, CS3, CS4 one by one, enables the tri-state buffer output port of each on-off counting unit, and then reads IN the corresponding on-off count value from the count data input port IN 1. The decoder circuit of the gate control unit in the embodiment can select 74HC139, or 74HC138, or adopt gate circuit composition. When the value of L is large, the decoder circuit can adopt a plurality of pieces of 74HC139, or a multistage cascade circuit formed by 74HC138 and the like, or a plurality of gates. When the value of L is small, the gating control unit may be omitted, and the controller unit directly sends out the gating control signal to each on-off counting unit through the output port, for example, in the embodiment of fig. 1, the gating control signals CS1, CS2, CS3, and CS4 may be directly sent out by the controller unit 10 without using the gating control unit.

The controller unit is used for controlling the whole relay service life detection device, and preferably uses a single chip microcomputer as a core to form the relay service life detection device. The core of the controller unit can also be ARM, or DSP, or programmable controller. The detection control process of the relay service life detection device comprises the following steps:

step 3, reading current L on-off count values;

Controlling the L relay switches to be turned on and off once means that the controller unit sends a relay driving signal to turn on and off the relay switches once, for example, the relay driving signal C1 sent by the controller unit in fig. 11(a) changes by one pulse cycle, or the relay driving signal C2 sent by the controller unit in fig. 11(b) changes by one pulse cycle. The service life counter is a software counter in the controller unit, the controller unit sends a relay driving signal for turning on and off the relay switch once, and the count value of the service life counter is increased by 1. And meanwhile, the on-off times of the L relay switches are respectively counted to obtain L on-off counting values, and the L on-off counting values are respectively counted by L on-off counting units outside the controller unit.

And judging whether the relay switch with the detection mark in the detection state is invalid or not, wherein the method is that if the error between the controlled on-off times of the relay switch to be judged and the on-off counting value of the relay switch is less than E, the relay switch is not invalid, otherwise, the relay switch is invalid. The counting value of the current service life counter is the number of times of on/off control of the relay switch to be judged. The specific judgment method is that the maximum count value of the on-off count value is set as G, and the count value of the current life counter is modulo G to obtain a remainder Q; and if the read on-off count value of the relay switch to be judged is K, if one of | K-Q | < E, or | K- (Q-G) | < E, or | K- (Q + G) | < E is satisfied, the relay switch is not failed, otherwise, the relay switch is failed. The on-off count value adopts a cyclic counting mode, and after the on-off count value reaches the maximum count value G of the tri-state output counting circuit, 1 is added, and the overflow is changed into 0; taking the 4-bit binary on-off count value output by the tri-state output counting circuit embodiment 2 as an example, the maximum value is 1111, and the next on-off count value is 0; in the judgment expression, comparing K with Q-G is to offset the influence of smaller K value plus counting overflow and larger Q value; comparing K with Q + G cancels out the larger value of K and the smaller influence of Q on G after modulus extraction. Because E is an integer which is more than or equal to 1 and less than or equal to G/2(G is divided by 2), after the error E is determined, the maximum count value G of the on-off count value must be more than 2 times of E; for example, if E is determined to be 3, the maximum count value G of the on-off count value must be greater than 6, and at this time, both the decimal BCD counter and the binary counter with more than 3 bits satisfy the requirement. And in the read current L on-off count values, the controller unit does not judge and process whether the relay switch with the detection mark in the detection stop state is invalid.

Whether the relay switch with the detection mark in the detection state is invalid or not can be judged, and the following method can also be adopted: when the current on-off count value of the relay switch is not increased by 1 with the previous on-off count value, the relay switch is invalid, otherwise, the relay switch is not invalid; the method comprises the steps that if the current on-off count value of the relay switch to be judged for V times continuously is not in the plus 1 relation with the previous on-off count value, the relay switch is invalid, otherwise, the relay switch is not invalid; and V is an integer greater than or equal to 2. The on-off count value adopts a cyclic counting mode, and after the on-off count value reaches the maximum value of the tri-state output counting circuit, 1 is added, and the overflow is changed into 0; taking the 4-bit binary on-off count value output by the tri-state output counting circuit embodiment 2 as an example, the maximum value is 1111, and the next on-off count value satisfying the 1-increasing relationship is 0.

Whether the relay switch with the detection mark in the detection state is invalid or not can be judged, and the following method can be adopted: when the current on-off count value accumulated by the relay switch for W times is not increased by 1 with the previous on-off count value, the relay switch is invalid, otherwise, the relay switch is not invalid; and W is an integer greater than or equal to 2.

The controller unit and the human-computer interface unit can adjust and display NO and NC duty ratios (namely, setting the proportion of pull-in time and release time) of the relay switch according to needs, select a failure judgment mode, set and display failure judgment parameters, set and display on-off periods of the relay switch and the like. The device can also be added with a temperature monitoring unit to monitor the temperature of the relay in the test process.

In order to reduce the volume and improve the reliability, all or part of the L on-off counting units, the oscillator units and the gating control units are preferably implemented by PAL, GAL, CPLD, FPGA or other programmable logic devices and logic units.

Except for the technical features described in the specification, the method is the conventional technology which is mastered by a person skilled in the art. For example, the controller of the selected controller unit, the related peripheral control circuit designed and programmed according to the detection control process and method of the device to realize its functions; selecting or designing a gating control unit circuit to meet the requirement of decoding gating; selecting or designing a multivibrator of an oscillator unit, and outputting a sampling clock pulse CLK meeting requirements; selecting the composition and circuit structure of the human-computer interface unit, and connecting the human-computer interface unit with the controller unit to realize corresponding functions; and the like, are conventional techniques known to those skilled in the art.

Claims

1. A method for detecting the service life of a relay is characterized by comprising the following steps:

step 3, reading current L on-off count values;

step 5, if the detection marks of the L relay switches are still in the detection state, returning to the step 2, otherwise, stopping the detection;

2. The relay life detection method according to claim 1, characterized in that: the on-off times of the L relay switches are respectively counted, and the counting is realized by L on-off counting units with the same structure and composition; the on-off counting unit comprises a pulse generating circuit, an anti-pulse interference circuit and a three-state output counting circuit;

the pulse generating circuit outputs an initial pulse generated by the on-off of the relay switch to the anti-pulse interference circuit; the anti-pulse interference circuit performs pulse filtering on the initial pulse and outputs a counting pulse; the tri-state output counting circuit counts the counting pulse and outputs an on-off counting value.

3. The relay life detection method according to claim 2, characterized in that: the anti-pulse interference circuit comprises a reversible amplitude limiting counter, a comparison threshold value setter, an upper limit value comparator, a lower limit value comparator and an RS trigger;

the input of the reversible amplitude limiting counter is an initial pulse and a sampling clock pulse, and the output is an amplitude limiting accumulated count value for counting the sampling clock pulse; the output of the comparison threshold value setter is an upper comparison threshold value and a lower comparison threshold value; the input of the upper limit value comparator is an amplitude limiting accumulated count value and an upper limit comparison threshold value, and the output is a first setting signal; the input of the lower limit value comparator is an amplitude limiting accumulated count value and a lower limit comparison threshold value, and the output is a second set signal; the input of the RS trigger is a first set signal and a second set signal, and the output is a counting pulse; the lower limit amplitude of the amplitude limiting accumulated count value is 0, and the upper limit amplitude is N; n is an integer greater than or equal to 2; the upper limit comparison threshold value is an integer which is greater than N/2 and less than or equal to N, and the lower limit comparison threshold value is an integer which is greater than or equal to 0 and less than N/2.

4. The relay life detection method according to claim 3, characterized in that: the function of the reversible amplitude limiting counter is that the level state of the initial pulse controls the reversible amplitude limiting counter to be in an up-counting state or a down-counting state; when the reversible amplitude limiting counter is in an up-counting state and the amplitude limiting accumulated count value is greater than or equal to the upper limit amplitude value N, the sampling clock pulse is not up-counted; when the reversible amplitude limiting counter is in a count-down state and the amplitude limiting accumulated count value is equal to the lower limit amplitude value 0, the sampling clock pulse is not counted down.

5. The relay life detection method according to claim 4, characterized in that: the upper limit value comparator has the function that when the input amplitude limiting accumulated count value is larger than or equal to the upper limit comparison threshold value, the first setting signal is enabled, otherwise, the first setting signal is disabled; the lower limit value comparator is used for enabling the second set signal when the input amplitude limiting accumulated count value is smaller than or equal to the lower limit comparison threshold value, and enabling the second set signal to be invalid otherwise.

6. The relay life detection method according to claim 5, characterized in that: the first setting signal is a setting signal of an RS trigger, and the second setting signal is a reset signal of the RS trigger; the counting pulse is output from the non-inverting output terminal of the RS flip-flop or is output from the inverting output terminal of the RS flip-flop.

7. The relay life detection method according to claim 3, characterized in that: the reversible amplitude limiting counter consists of a reversible counter with single clock input and an amplitude limiting and adding and subtracting control circuit; the up-down counter has an up-down control input and an enable input.

8. The relay life detection method according to any one of claims 1 to 7, characterized in that: the device is realized by a device comprising a controller unit, L on-off counting units, a human-computer interface unit, a relay driving unit and an oscillator unit;

the human-computer interface unit is electrically connected to the controller unit and used for sending out a detection command and displaying the service life of the L relay switches; the controller unit is electrically connected to the relay driving unit and sends a relay driving signal to the relay driving unit to control the on-off of the L relay switches; the oscillator unit outputs sampling clock pulses to the L on-off counting units; the L on-off counting units respectively count the on-off of the L relay switches to obtain L on-off counting values; the on-off counting unit is electrically connected to the controller unit and used for respectively reading on-off counting values of the L on-off counting units and controlling the clear 0 of the on-off counting values of the L on-off counting units by the controller unit.

9. The relay life detection method according to claim 8, characterized in that: the on-off counting unit is electrically connected to the controller unit, and the method for the controller unit to respectively read in the on-off counting values of the L on-off counting units is that the on-off counting values of the L on-off counting units are all output in a three-state buffer mode; the tri-state buffer output ports of all the on-off counting units are all connected in parallel to the counting data input port of the controller unit; the controller unit sends out gating control signals to enable the three-state buffer output ports of the on-off counting units one by one, and corresponding on-off counting values are read in from the counting data input port.

10. The relay life detection method according to claim 9, characterized in that: the apparatus further includes a gating control unit; the controller unit sends an address coding signal of the on-off counting unit to the gating control unit, and the gating control unit decodes the address coding signal of the on-off counting unit to obtain a gating control signal.