CN107831433B - Reed pipe service life detection method - Google Patents
Reed pipe service life detection method Download PDFInfo
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- CN107831433B CN107831433B CN201711133946.5A CN201711133946A CN107831433B CN 107831433 B CN107831433 B CN 107831433B CN 201711133946 A CN201711133946 A CN 201711133946A CN 107831433 B CN107831433 B CN 107831433B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/327—Testing of circuit interrupters, switches or circuit-breakers
- G01R31/3277—Testing of circuit interrupters, switches or circuit-breakers of low voltage devices, e.g. domestic or industrial devices, such as motor protections, relays, rotation switches
- G01R31/3278—Testing of circuit interrupters, switches or circuit-breakers of low voltage devices, e.g. domestic or industrial devices, such as motor protections, relays, rotation switches of relays, solenoids or reed switches
Abstract
a reed switch service life detection method can count the on-off times of a plurality of reed switches to obtain on-off count values at the same time, and judge whether the on-off count values of the reed switches are qualified or not according to the number of asynchronous times between the count of the on-off count values and the on-off times of the reed switches to determine whether the reed switches are invalid or not; an anti-pulse interference circuit in the on-off counting unit can filter out edge jitter interference in counting pulses, so that the accuracy of the reed switch service life detection is ensured; the mode that a plurality of counters are arranged outside the controller unit and count the on-off times of the reed pipes respectively is adopted, and the number of the reed pipes for detecting the service life of the reed pipes is not limited by the number of the counters inside the controller unit.
Description
Technical Field
The invention relates to the field of testing methods and devices, in particular to a reed switch service life detection method.
background
The life of the reed pipe is generally from tens of thousands to hundreds of thousands. The service condition of the reed switch is simulated, electric pulses are generated by controlling the on-off of the reed switch, and the service life of the reed switch can be tested by counting the electric pulses. The electric pulse generated by the on-off of the reed switch contains edge jitter, and the unprocessed pulse is directly counted, so that a great error is generated. The influence of shaking pulses is removed by using the MCU software delay mode, and when the MCU needs to test the service lives of a plurality of reed switches at the same time, the MCU software delay mode can make the MCU careless.
Disclosure of Invention
In order to solve the problems in the aspect of service life detection of the conventional reed switch, the invention provides a method for detecting the service life of the reed switch, which comprises the following steps of:
Step 1, initializing, namely setting detection marks of L reed pipes to be in a detection state, clearing a service life counter to be 0, and reading L on-off count values for the first time;
Step 2, controlling the on-off of the L reed pipes once, and simultaneously counting the on-off times of the L reed pipes respectively to obtain L on-off count values; the service life counter counts by adding 1;
Step 3, reading the current L on-off count values;
Step 4, judging whether the reed switches with the detection marks in the detection state are invalid one by one; setting the detection mark of the reed switch judged to be failed at this time to be in a detection stop state, and taking the count value of the current life counter as the life value of the reed switch judged to be failed at this time;
And 5, if the detection marks of the L reed pipes are still in the detection state, returning to the step 2, otherwise, stopping detection.
Judging whether the reed switch with the detection mark in the detection state is invalid or not by the method that when the current on-off count value of the reed switch to be judged is not increased by 1 with the previous on-off count value, the reed switch is invalid, otherwise, the reed switch is not invalid; the method is that if the current on-off count value of the reed switch to be judged for K times continuously does not increase 1 with the previous on-off count value, the reed switch is invalid, otherwise, the reed switch is not invalid; and K is an integer greater than or equal to 2.
The on-off times of the L reed pipes are respectively counted to obtain L on-off counting values, and the L on-off counting values are realized by L on-off counting units with the same structure and composition; the on-off counting unit comprises a pulse generating circuit, an anti-pulse interference circuit and a three-state output counting circuit; the pulse generating circuit outputs an initial pulse to the anti-pulse interference circuit; the anti-pulse interference circuit performs pulse filtering on the initial pulse and outputs a counting pulse; the tri-state output counting circuit counts the counting pulse and outputs an on-off counting value.
The anti-pulse interference circuit comprises a shift register, an anti-interference threshold value setter, a ROM (read only memory) and an RS trigger; the input of the shift register is an initial pulse and a sampling clock pulse, and the output is N-bit sequence data; the anti-interference threshold value setter outputs an anti-interference threshold value; the input of the ROM is N-bit sequence data and an anti-interference threshold, and the output is a first setting signal and a second setting signal; the RS trigger inputs a first set signal and a second set signal and outputs a counting pulse.
The shift register samples the initial pulse at the edge of the sampling clock pulse to obtain N-bit sequence data, wherein N is an integer greater than or equal to 2, and the N-bit sequence data is the latest N times sampling value of the initial pulse; the address input of the ROM memory consists of N-bit sequence data and an anti-interference threshold M, and the two-bit data output is a first setting signal and a second setting signal respectively; m is an integer greater than or equal to 0 and less than N/2(N divided by 2); the N-bit sequence data and the anti-interference threshold value M are both N-bit binary data.
The function of the ROM memory is that when the number of '1' in the input N-bit sequence data is more than or equal to N-M (N minus M), the output first set signal is effective; when the number of '1' in the input N-bit sequence data is less than or equal to M, the output second set signal is valid. Setting both the first set signal and the second set signal active high and output from the data outputs D1 and D0, respectively, of the ROM memory in which the cell contents D1 and D0 are specifically determined,
Determining M according to the numerical value of an anti-interference threshold value M part in the address of the storage unit;
determining the number of '1' in the N-bit sequence data according to the numerical value of the N-bit sequence data part in the address of the storage unit;
③ when the number of '1' in the N-bit sequence data is greater than or equal to N-M, D1 is equal to 1, otherwise, D1 is equal to 0; when the number of "1" in the N-bit sequence data is equal to or less than M, D0 is equal to 1, otherwise, D0 is equal to 0.
when both the first set signal and the second set signal are active low, the contents of D1 and D0 in the memory may be inverted.
the RS trigger has the functions that the first setting signal is a setting signal of the RS trigger, and the second setting signal is a reset signal of the RS trigger; the counting pulse is output from the non-inverting output terminal or the inverting output terminal of the RS flip-flop.
The method for detecting the service life of the reed switch is realized by a device comprising a controller unit, a magnetic control driving unit and an oscillator unit; the L reed switches are controlled to be switched on and off once, and the controller unit sends a magnetic control driving signal to the magnetic control driving unit to realize the switching; the oscillator unit outputs a sampling clock pulse.
the on-off count values of the L on-off counting units are all output in a three-state buffering mode; the tri-state buffer output ports of all the on-off counting units are all connected in parallel to the counting data input port of the controller unit; the controller unit sends out gating control signals to enable the three-state buffer output ports of the on-off counting units one by one, and corresponding on-off counting values are read in from the counting data input port.
The invention has the beneficial effects that: the service lives of a plurality of reed pipes can be detected simultaneously; the pulse interference resisting circuit is adopted to automatically filter the edge jitter interference in the electric pulse generated by the on-off of the reed switch, the effect of filtering the pulse interference can be adjusted by changing the number of bits of the parallel output end of the shift register or changing the size of an anti-interference threshold value, and the accuracy of the detection of the service life of the reed switch is ensured; the mode that a plurality of counters are arranged outside the controller unit and count the on-off times of the reed pipes respectively is adopted, and the number of the reed pipes for detecting the service life of the reed pipes is not limited by the number of the counters inside the controller unit.
Drawings
fig. 1 is a block diagram of an embodiment of a reed switch life detection device when L is 4;
FIG. 2 is a block diagram of an embodiment of a 1# on-off counting unit;
FIG. 3 shows an embodiment of a 1# pulse generating circuit;
Fig. 4 shows an embodiment of an N-5 shift register;
Fig. 5 shows an embodiment of an interference rejection threshold setter and ROM memory when N is 5;
FIG. 6 is an RS flip-flop embodiment;
fig. 7 is a schematic diagram of an anti-interference effect of the anti-glitch circuit when N is 5;
Fig. 8 is a tri-state output counting circuit embodiment.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The reed switch service life detection method is realized by a reed switch service life detection device comprising a controller unit, L on-off counting units, a human-computer interface unit, a magnetic control driving unit and an oscillator unit. The human-computer interface unit is electrically connected to the controller unit and used for sending out a detection command and displaying the service life of the L reed pipes; the controller unit is electrically connected to the magnetic control driving unit and sends a magnetic control driving signal to the magnetic control driving unit to control the on-off of the L reed switches; the oscillator unit outputs sampling clock pulses to the L on-off counting units; the L on-off counting units respectively count the on-off of the L reed pipes to obtain L on-off counting values; the on-off counting unit is electrically connected to the controller unit, and the controller unit respectively reads in on-off counting values of the L on-off counting units. When the L value is larger, the on-off count values of the L on-off counting units are all output in a tri-state buffering mode; the tri-state buffer output ports of all the on-off counting units are all connected in parallel to the counting data input port of the controller unit; the controller unit sends out gating control signals to enable the three-state buffer output ports of the on-off counting units one by one, and corresponding on-off counting values are read in from the counting data input port. The apparatus may further include a gating control unit electrically connected to the controller unit; the controller unit sends an on-off counting unit address coding signal to the gating control unit, the gating control unit decodes the on-off counting unit address coding signal to obtain a gating control signal, and a tri-state buffer output port of the on-off counting unit corresponding to the on-off counting unit address coding signal is enabled.
Fig. 1 is a block diagram of an embodiment of a reed switch life detection device when L is 4, and includes a controller unit 10, a 1# on-off counting unit 11, a 2# on-off counting unit 12, a 3# on-off counting unit 13, a 4# on-off counting unit 14, a human-machine interface unit 15, a gating control unit 16, a magnetron driving unit 17, and an oscillator unit 18.
The human-machine interface unit 15 communicates with the controller unit 10 through an interface I/O1 of the controller unit 10, and is used for detecting issuance of commands, parameter modification, display of the life of each reed switch, and the like; the controller unit 10 sends a magnetic control driving signal to the magnetic control driving unit 17 through an output port OUT2 to control the on-off of the reed switches from No. 1 to No. 4; the oscillator unit 18 outputs sampling clock pulses CLK to the 1# on-off counting unit 11, the 2# on-off counting unit 12, the 3# on-off counting unit 13 and the 4# on-off counting unit 14; the number 1 of on-off counting units 11, the number 2 of on-off counting units 12, the number 3 of on-off counting units 13 and the number 4 of on-off counting units 14 respectively perform pulse generation, pulse filtering and on-off frequency counting on the on-off of 4 reed pipes; the controller unit 10 sends an address coding signal of an on-off counting unit to be gated to the gating control unit 16 through an output port OUT1, the gating control unit 16 decodes the address coding signal of the on-off counting unit to obtain gating control signals CS1, CS2, CS3 and CS4, and on-off count values CV1, CV2, CV3 and CV4 of the 1# on-off counting unit 11, the 2# on-off counting unit 12, the 3# on-off counting unit 13 and the 4# on-off counting unit are respectively controlled to be sent to the controller unit 10 through an input port IN1, and the IN1 is a counting data input port of the controller unit.
Fig. 2 is a block diagram of an embodiment of a 1# on-off counting unit. In fig. 2, a 1# pulse generating circuit 100 outputs an initial pulse P11 generated by switching on and off a 1# reed switch; the shift register 101, the ROM 102, the anti-interference threshold value setter 103 and the RS trigger 104 form an anti-pulse interference circuit, pulse filtering is carried out on the initial pulse P11, and a counting pulse P12 is output; the tri-state output counting circuit 105 counts the counting pulse P12, and outputs the on-off count value CV1 of the 1# reed switch under the control of the gate control signal CS 1.
In the anti-glitch circuit of fig. 2, the shift register 101 includes a serial input terminal, an N-bit parallel output terminal, and a sampling clock input terminal, the initial pulse P11 is input from the serial input terminal of the shift register 101, the sampling clock CLK is input from the sampling clock input terminal of the shift register 101, and the N-bit parallel output terminal of the shift register 101 outputs N-bit sequence data X1; the anti-interference threshold value setter 103 outputs an anti-interference threshold value M; the input of the ROM memory 102 is N-bit sequence data X1 and an interference rejection threshold M, and the output is a first set signal SE1 and a second set signal RE 1; the RS flip-flop 104 has inputs of a first set signal SE1 and a second set signal RE1, and an output of a count pulse P12. The anti-glitch circuit embodiment chooses N-5.
FIG. 3 shows an embodiment of a 1# pulse generating circuit. The 1# reed switch KA1 is connected in series with a load resistor RA1 and then connected in parallel to a power supply + VCC1 and a common ground GND, and the current limiting resistor R11 is connected in series with a voltage stabilizing tube VD1 and then connected in parallel to two ends of a load resistor RA 1; an initial pulse P11 generated by switching on and off a No. 1 reed switch is output from a voltage regulator tube VD 1. The reed switch is mainly used for counting, limiting and other occasions, and the load of the reed switch is mainly direct current resistive load; the size of the load resistor RA1 can be adjusted, so that the size of the resistive direct-current load current of the reed switch KA1 to be detected can be adjusted. KA1 in FIG. 3 is a normally open switch; the circuit of fig. 3 can still output an initial pulse P1 generated by the on-off of a reed switch by changing the KA1 into a normally closed switch. The pulse generating circuit can also adopt other circuits which can generate initial pulse by on-off control of the reed switch.
Fig. 4 shows an embodiment of an N-5 shift register. In fig. 4, 5D flip-flops FF1, FF2, FF3, FF4 and FF5 form a 5-bit serial shift register, and an input end D of FF1 is a serial input end of the shift register and is connected to an initial pulse P11; clock input ends CP of FF1, FF2, FF3, FF4 and FF5 are connected in parallel to form a shift pulse input end of the shift register, namely a sampling clock pulse input end of the shift register, and are connected to a sampling clock pulse CLK; the output end Q of FF1, FF2, FF3, FF4 and FF5 is X11, X12, X13, X14 and X15 respectively, and in fig. 4, the N-bit sequence data X1 is composed of X11, X12, X13, X14 and X15. The N-bit sequence data X1 is the last N sample values of the shift register at the rising edge of the sampling clock pulse CLK edge to the initial pulse P11.
When N is other value, the number of D flip-flops in fig. 4 can be increased or decreased to realize the function of the shift register. The D flip-flop in fig. 4 may be replaced with other flip-flops, for example, N JK flip-flops are used to implement the function of the shift register of N bits. The shift register can also be implemented by using a single or multiple dedicated multi-bit shift registers, for example, 1 chip 74HC164 or 1 chip 74HC595 can be used to implement the function of the shift register with no more than 8 bits, and multiple chips 74HC164 or 74HC595 can be used to implement the function of the shift register with more than 8 bits.
Fig. 5 shows an embodiment of the interference rejection threshold setter and ROM memory when N is 5. The anti-interference threshold value setter consists of resistors R91 and R90 and threshold value selection switches K91 and K90; + VCC is the power supply, GND is common ground. In fig. 5, the interference rejection threshold M output by the interference rejection threshold setter is composed of y11 and y 10; because the anti-interference threshold M is a non-negative integer smaller than N/2, when N is 5, M takes a value among 0, 1, and 2, that is, y11 and y10 only take values of 0, or 0, 1, or 1, 0, and are selectively set through the threshold selector switches K91 and K90. The anti-interference threshold setter can be composed of a multi-bit binary dial switch, a BCD dial switch, a plurality of common switches and pull resistors, or a plurality of pull-up resistors for controlling 0 and 1 outputs, a circuit short-circuit point and other similar circuits.
In fig. 5, the ROM device FR1 constitutes a ROM memory. The function of the ROM memory is to input the interference rejection threshold M and the N-bit sequence data X1 as address signals, and output the first set signal SE1 and the second set signal RE1 as data; the ROM memory determines whether the output first set signal SE1 and second set signal RE1 are valid respectively, based on the currently input interference rejection threshold M and the number of "1" s in the N-bit sequence data X1.
when N is 5, FR1 is required to have 7-bit address input, i.e., address input terminals a6-a0 of FR1 in fig. 5; FR1 is required to have 2-bit data outputs, namely D1 and D0 of FR1 in fig. 5. Assuming that the address input terminals a4, A3, a2, a1, a0 of FR1 respectively input X15, X14, X13, X12, X11 of the N-bit sequence data X1, the address input terminals a6, A5 respectively input y11, y10 of the interference rejection threshold M, and the data output terminals D1, D0 of FR1 respectively are the first set signal 573se 5 and the second set signal RE1, the contents of each address unit in FR1 are shown in table 1. In table 1, when N is 5, the first set signal SE1 and the second set signal RE1 output from D1 and D0 are both active high.
table 1 ROM memory cell contents when N is 5
Taking memory cell 0110000 in ROM as an example, M part is the upper 2 bits of address, and the value is 1; the number of the address lower 5-bit N-bit sequence data parts "1" is 1, and the condition that N-M is not more than N-M is not satisfied, so that D1 is 0; since the condition of M or less is satisfied, D0 is 1. Taking the storage unit 0001001 in the ROM memory as an example, the value of M in the storage unit address is 0; the N-bit sequence data part in the memory cell address is the lower 5 bits of the address, wherein the number of '1' is 2; since the number of "1" s in the N-bit sequence data does not satisfy the condition of being equal to or greater than N-M, D1 is 0; since the number of "1" s in the N-bit sequence data does not satisfy the condition of M or less, D0 is 0.
when the interference rejection threshold M is 0, y11 and y10 input by the addresses a6 and a5 are 0 and 0, at this time, when the number of "1" in the N-bit sequence data X1 is equal to 5, the output SE1 is high, otherwise SE1 is low, and in table 1, this condition is satisfied only when the addresses a6-a0 are 0011111; when the number of "1" in the N-bit sequence data X1 is equal to 0, the output RE1 is high, otherwise RE1 is low, which is satisfied only when the addresses a6-a0 are 0000000 in table 1.
When the interference resistance threshold M is 1, y11 and y10 input by the addresses a6 and a5 are 0 and 1, at this time, when the number of "1" in the N-bit sequence data X1 is greater than or equal to 4, the output SE1 is high, otherwise SE1 is low, and in table 1, this condition is satisfied when the addresses a6-a0 are 0101111, 0110111, 0111011, 0111101, 0111110 and 0111111; when the number of "1" in the N-bit sequence data X1 is equal to or less than 1, the output RE1 is at high level, otherwise RE1 is at low level, and in table 1, this condition is satisfied when the addresses a6-a0 are 0100000, 0100001, 0100010, 0100100, 0101000, 0110000.
When the interference rejection threshold M is 2, y11 and y10 of the inputs of the addresses a6 and a5 are 1 and 0, at this time, when the number of "1" in the N-bit sequence data X1 is greater than or equal to 3, the output SE1 is high, otherwise SE1 is low, in table 1, 16 address inputs of 1000111, 1001011 and the like in the addresses a6-a0 meet the condition; when the number of "1" in the N-bit sequence data X1 is less than or equal to 2, the output RE1 is high, otherwise RE1 is low, and table 1 shows that 16 inputs at addresses a6-a0, i.e., 1000000, 1000001, and the like, satisfy this condition.
When the contents of D1 and D0 stored in each memory cell in table 1 are inverted, i.e., 0 changes to 1 and 1 changes to 0, the output first set signal SE1 and second set signal RE1 are both active low. When N is 5, M can only take values among 0, 1, and 2, that is, y11 and y10 cannot take values of 1 and 1. M in table 1 takes values only among 0, 1, and 2, and 96 memory cells in the ROM memory are used in total. To avoid unpredictable situations in the system when M is set erroneously to 3, i.e. when all the threshold selector switches K91, K90 in the disturb threshold selector cell are turned off, the situation where M is set erroneously to 3 may be determined as one of M being 0, or 1, or 2 when determining the contents of the memory cells in the ROM memory. For example, when M is erroneously set to 3, it is handled as a case where M is 2; taking the storage location 1110010 in the ROM memory as an example, the interference rejection threshold M part in the storage location address is the upper 2 bits of the address, so the value of M is set to 3 by mistake, and M is taken to be 2; the N-bit sequence data part in the memory cell address is the lower 5 bits of the address, wherein the number of '1' is 2; since the number of "1" s in the N-bit sequence data does not satisfy the condition of being equal to or greater than N-M, D1 is 0; since the condition that the number of "1" in the N-bit sequence data is equal to or less than M is satisfied, D0 is 1. When considering the M false setting condition, the high-order 2 bits of the ROM memory include 00, 01, 10 and 11 cases, 128 memory cells in the ROM memory are used in common, that is, all cells corresponding to the 7-bit binary address input are included.
The corresponding relation between each binary digit of the anti-interference threshold value M and each binary digit of the N-bit sequence data and each bit of the binary address of the ROM can adopt any one-to-one corresponding relation. Taking an embodiment with N being 5 as an example, y11 and y10 of M may correspond to address input terminals a1 and a0, respectively, and X15, X14, X13, X12 and X11 of X1 may correspond to address input terminals A6, a5, a4, A3 and a2, respectively, one to one; or y11 and y10 of M correspond to the address input ends A1 and A0 respectively, and X11, X12, X13, X14 and X15 of X1 correspond to the address input ends A6, A5, A4, A3 and A2 respectively in a one-to-one manner; or y11, x14, x15, x11, x12, y10 and x13 are respectively in one-to-one correspondence with the address input terminals A6, a5, a4, A3, a2, a1 and a0, and the like.
Fig. 6 shows an RS flip-flop embodiment, which is composed of nor gates FO1 and FO2, and the first set signal SE1 and the second set signal RE1 are both active high. When SE1 is active and RE1 is inactive, a count pulse P12 output from the in-phase output terminal FO2 is set to 1; when the SE1 is invalid and the RE1 is valid, setting the counting pulse P12 to be 0; when both SE1 and RE1 are inactive, the state of the count pulse P12 is unchanged. The RS flip-flop may also take other forms.
in fig. 6, the counting pulse P12 is in phase with the initial pulse P11. If the count pulse P12 is output from the inverting output terminal, i.e., the or gate FO1, the function is to set the count pulse P12 to 0 when SE1 is active and RE1 is inactive; when the SE1 is invalid and the RE1 is valid, setting the counting pulse P12 to be 1; when both SE1 and RE1 are inactive, the state of the count pulse P12 is unchanged; the counting pulse P12 and the initial pulse P11 are in an inverse relationship.
as can be seen from table 1, since the immunity threshold M is a non-negative integer smaller than N/2, the first set signal SE1 and the second set signal RE1 cannot be simultaneously asserted, and thus, the output of the RS flip-flop is not indeterminate in logic state.
Fig. 7 is a schematic diagram illustrating the anti-interference effect of the anti-glitch circuit when N is 5. Setting an anti-interference threshold M to select 1, when the number of '1' in the N-bit sequence data X1 is more than or equal to 4, SE1 is effective, and a counting pulse P12 is set to be 1; when the number of '1' in the N-bit sequence data X1 is less than or equal to 1, RE1 is valid, and the count pulse P12 is set to 0; when the number of "1" in the N-bit sequence data X1 is more than 1 and less than 4, both SE1 and RE1 are inactive and the count pulse P12 maintains the state. The result of sampling the initial pulse P11 by 12 sampling clock pulses CLK, and the resultant count pulse P12 are shown in fig. 7. Assuming that 5 pieces of sequence data X1 sampled before sample point 1 of CLK in fig. 7 are all 0, the count pulse P12 is 0. In fig. 7, the initial pulse P11 starts to change from 0 to 1 after sampling point 4 of CLK, and 2 times of edge jitter occurs in the process of changing from 0 to 1, wherein the 1 st positive narrow pulse is sampled, and the value of sampling point 5 is 1; the 2 nd positive narrow pulse width is less than the sample period and is between the 5 th and 6 th sample points, and does not affect the sampling result of the sequence data X1, i.e., the sampling process automatically filters out the positive narrow pulse interference, and the value of sample point 6 is 0. In fig. 7, the number X2 of "1" in the N-bit sequence data X1, N-bit sequence data X1, and the count pulse P12 sampled at sample point 1 to sample point 12 of the clock pulse CLK are shown in table 2.
TABLE 2 number X2 of "1" in N-bit sequence data X1, X1 and counting pulse P12 of samples 1-12
Observing the condition of the sampling points in table 2, at sampling points 1-6, X2 is less than or equal to 1, RE1 is valid, SE1 is invalid, and P12 is set to 0; at sample points 7-9, X2 is greater than 1 and less than 4, SE1, RE1 are both inactive, P12 remains 0; at sample points 9-12, X2 is 4 or greater, SE1 is active, RE1 is inactive, and P12 is set to 1. Obviously, in the case where the number of "1" s in the N-bit sequence data X1 is not satisfied by the condition of 4 or more until the sampling point 9 of fig. 7 among the consecutive 5 sequence data X1 values, the first set signal SE1 is asserted, and the count pulse P12 is changed from 0 to 1.
Fig. 7 shows the anti-glitch effect of the anti-glitch circuit when the initial pulse P11 is 0, and the condition and process of the initial pulse P11 changing from 0 to 1. The anti-glitch circuit has the anti-negative-glitch effect when the initial pulse P11 is 1, and the condition and process of the initial pulse P11 changing from 1 to 0 are the same as the anti-positive-glitch effect when the initial pulse P11 is 0, and the condition and process of the initial pulse P11 changing from 0 to 1. The 5 sample values of CLK to the initial pulse P11 before the sample point 31 of the clock pulse CLK are all 1, the count pulse P12 is 1, and the number X2 of "1" in the N-bit sequence data X1 and the N-bit sequence data X1 and the count pulse P12 obtained by sampling from the sample point 31 to the sample point 42 are shown in table 3.
TABLE 3 number X2 of "1" in N-bit sequence data X1, X1 and counting pulse P12 of sample points 31-42
observing the condition of the sampling points in the table 3, at the sampling points 31-32, X2 is greater than or equal to 4, SE1 is effective, RE1 is ineffective, and P12 is set to 1; at sample points 33-38, X1 is greater than 1 and less than 4, SE1, RE1 are both inactive, P12 remains 1; at sample points 39-42, X2 is less than or equal to 1, RE1 is active, SE1 is inactive, and P12 is set to 0.
The counting pulse P12 and the initial pulse P11 are in phase, for example. When the initial pulse P11 and the count pulse P12 are both 0, in N consecutive samples, as long as the sampling result formed by single or multiple positive pulse interferences does not cause the number of "1" in the N-bit sequence data X1 to be greater than or equal to N-M, the count pulse P12 does not become 1; when both the initial pulse P11 and the count pulse P12 are 1, the count pulse P12 does not become 0 in consecutive N samples as long as the sampling result formed by the single or multiple negative pulse glitches does not cause the number of "1" s in the N-bit sequence data X1 to be equal to or less than M. When both P11 and P12 are at low level, a positive pulse corresponding to the positive pulse in P11 can be output from P12 as long as the positive pulse appearing in P11 makes N-M or more of consecutive N P11 sample values 1; when both P11 and P12 are at a high level, a negative pulse corresponding to the negative pulse in P11 can be output from P12 as long as M or less of N consecutive P11 sample values are 1 due to the negative pulse occurring in P11. After the initial pulse P11 has changed from 0 to 1, or from 1 to 0, the count pulse P12 needs to change the number of "1" s in the N-bit sequence data X1 to N-M or less after the condition is satisfied, and then change the count pulse P12 from 0 to 1, or change the count pulse P12 from 1 to 0, with a delay of several sampling pulse periods. When the value of the anti-interference threshold value M is larger, the conditions that the counting pulse P12 is changed from 0 to 1 and from 1 to 0 are stricter, the effect of resisting positive pulse interference and negative pulse interference is better, but the delay time of the counting pulse P12 relative to the initial pulse P11 is larger; conversely, when the value of M is smaller, the effect of the anti-positive pulse and the anti-negative pulse interference becomes smaller, but the delay time of the count pulse P12 with respect to the initial pulse P11 becomes smaller. When the value of N is larger, the anti-pulse interference circuit changes the counting pulse P12 from 0 to 1 and changes the conditions from 1 to 0 strictly, the anti-interference effect is better, but the delay time of the counting pulse P12 relative to the initial pulse P11 is larger; when the value of N becomes smaller, the conditions that the counter pulse P12 changes from 0 to 1 and from 1 to 0 become wider by the anti-glitch circuit, the anti-glitch effect becomes smaller, but the delay time of the counter pulse P12 with respect to the initial pulse P11 becomes smaller.
fig. 8 is a tri-state output counting circuit embodiment. Fig. 8(a) shows tristate output counting circuit embodiment 1, which is composed of counter FC1 and not gate FN1, and FC1 is 8-bit binary counter 74HC590 with tristate output. The count enable terminal CCKEN input 0, the clear 0 control terminal CCLR input 1 and the FC1 of the FC1 work in an up-count state. The count pulse P12 is directly connected to the count pulse input CCK of the FC1, and the FC1 counts by 1 at the rising edge of the count pulse P12 to obtain an on-off count value. The count pulse P12 is connected to the FC1 data latch RCK through the not gate FN1, and the contents of the internal counter are latched to the output latch at the falling edge of the count pulse P12. When the gate control signal CS1 is connected to the output enable control terminal G of the FC1 and CS1 is low, the FC1 outputs the on-off count value CV1 in the output latch from Q7 to Q0; when CS1 is at high level, Q7-Q0 of FC1 are in high-impedance state. The on-off count value output by the tri-state output counting circuit embodiment 1 is an 8-bit binary count value.
Fig. 8(b) shows tristate output counting circuit embodiment 2, which is composed of counter FC2 and tristate buffer FB1, FC2 is 4-bit binary counter 74HC161, FB1 is tristate buffer 74HC 244. Count control terminals CTP and CTR, and clear 0 control terminal CR and count control terminal LD of FC2 are all connected to 1, and FC2 operates in an up-count state. The count pulse P12 is directly connected to the count pulse input CP of the FC2, and the FC2 counts up by 1 at the rising edge of the count pulse P12 to obtain an on-off count value. The 4-bit data input ends A3-A0 of the tristate buffer FB1 are respectively connected to the 4-bit count value output ends Q3-Q0 of the counter FC2, the gating control signal CS1 is connected to the output enabling control end 1G of the FB1, and when the CS1 is at a low level, the FB1 outputs the on-off count value CV1 output by the counter FC2 from Y3-Y0; when CS1 is at high level, Y3-Y0 of FB1 are in high-impedance state. The on-off count value output by the tri-state output counting circuit embodiment 2 is a 4-bit binary count value.
in the embodiment of the device for detecting the service life of the reed switch when L is 4, the 2# on-off counting unit, the 3# on-off counting unit and the 4# on-off counting unit adopt the same circuit composition and structure as the 1# on-off counting unit, namely all the on-off counting units comprise a pulse generating circuit, an anti-pulse interference circuit and a tri-state output counting circuit; the pulse generating circuit, the anti-pulse interference circuit and the tri-state output counting circuit have the same composition and structure.
The oscillator unit is used for outputting a sampling clock pulse CLK, and any one of various multivibrators may be selected to constitute the oscillator unit. The initial pulse comes from the on-off control output of the reed switch, the frequency of controlling the on-off of the reed switch by the controller unit is lower than 10Hz, the width of the high level and the low level of the formed pulse is close to or larger than 50ms, and the jitter interference during the on-off of the reed switch does not exceed 5ms, so that the period of the sampling clock pulse CLK can be selected to be about 5ms, and N is selected to be a value within the range of 3-8.
The human-computer interface unit preferably uses a touch screen and adopts RS485 or RS232 to communicate with the controller unit. The man-machine interface unit can also be optionally composed of a key circuit and a liquid crystal display.
the magnetic control driving unit consists of an electromagnet and a driving circuit thereof. The on-off control of 1 reed switch by 1 electromagnet and a driving circuit thereof can be adopted, or the on-off control of a plurality of reed switches can be simultaneously carried out by 1 electromagnet and a driving circuit thereof, so that the on-off control of L reed switches is integrally realized. The magnetic field generated by the electromagnet should ensure that the reed switch controlled correspondingly can reliably act, and the whole magnetic control driving unit should ensure that the L reed switches can reliably act.
The on-off count values of all the on-off counting units are output in a tri-state buffering mode; all the tri-state buffer output ports of all the on-off counting units are connected in parallel to the counting data input port of the controller unit, the controller unit sends out gating control signals to enable the tri-state buffer output ports of all the on-off counting units respectively, and on-off counting values output by the enabled tri-state buffer output ports are read in from the counting data input port. The on-off count value in the embodiment 1 of the tri-state output counting circuit is 8-bit binary data, and a tri-state buffer output port of the on-off counting unit and a counting data input port of the controller unit are 8-bit parallel ports; the on-off count value in the tri-state output counting circuit embodiment 2 is 4-bit binary data, and the tri-state buffer output port of the on-off counting unit and the counting data input port of the controller unit are both 4-bit parallel ports. When the L value is small and the number of digits of the on-off counting value is small, the on-off counting value of the on-off counting unit can be output without adopting a three-state buffer mode, and the output ports of the on-off counting value of each on-off counting unit are respectively and directly connected to different parallel ports of the controller unit; for example, when L is 4 and the on-off count value is a 4-bit binary value, the on-off count value output ports of the 4 on-off count units are directly connected to different parallel ports of the controller unit, and only 16-bit I/O port lines, that is, 2 8-bit input ports, in total need to be consumed by the controller unit.
The controller unit sends out gating control signals through the gating control unit. The gating control unit is a decoder circuit and decodes the on-off counting unit address coding signal sent by the controller unit to obtain a gating control signal. In the embodiment of fig. 1, the on-off counting unit address encoding signals corresponding to the 1# on-off counting unit 11, the 2# on-off counting unit 12, the 3# on-off counting unit 13 and the 4# on-off counting unit are binary 00, 01, 10 and 11 respectively, and are decoded and output as CS1, CS2, CS3 and CS 4; the controller unit enables CS1, CS2, CS3, CS4 one by one, enables the tri-state buffer output port of each on-off counting unit, and then reads IN the corresponding on-off count value from the count data input port IN 1. The decoder circuit of the gate control unit in the embodiment can select 74HC139, or 74HC138, or adopt gate circuit composition. When the value of L is large, the decoder circuit can adopt a plurality of pieces of 74HC139, or a multistage cascade circuit formed by 74HC138 and the like, or a plurality of gates. When the value of L is small, the gating control unit may be omitted, and the controller unit directly sends out the gating control signal to each on-off counting unit through the output port, for example, in the embodiment of fig. 1, the gating control signals CS1, CS2, CS3, and CS4 may be directly sent out by the controller unit 10 without using the gating control unit.
the controller unit is used for controlling the whole reed switch service life detection device and realizing the reed switch service life detection method. The controller unit is preferably formed by using a single chip microcomputer as a core, and the core of the controller unit can also be ARM, or DSP, or a programmable controller. The reed switch service life detection method comprises the following steps:
Step 1, initializing, namely setting detection marks of L reed pipes to be in a detection state, clearing a service life counter to be 0, and reading L on-off count values for the first time;
Step 2, controlling the on-off of the L reed pipes once, and simultaneously counting the on-off times of the L reed pipes respectively to obtain L on-off count values; the service life counter counts by adding 1;
step 3, reading the current L on-off count values;
Step 4, judging whether the reed switches with the detection marks in the detection state are invalid one by one; setting the detection mark of the reed switch judged to be failed at this time to be in a detection stop state, and taking the count value of the current life counter as the life value of the reed switch judged to be failed at this time;
and 5, if the detection marks of the L reed pipes are still in the detection state, returning to the step 2, otherwise, stopping detection.
The control of the on-off of the L reed pipes is performed once, which means that the controller unit sends a magnetic control signal for enabling the reed pipes to be on and off once through the magnetic control driving unit. The service life counter is a software counter in the controller unit, the controller unit sends a magnetic control signal for switching on and off the reed pipe once, and the count value of the service life counter is increased by 1. And meanwhile, the on-off times of the L reed pipes are respectively counted to obtain L on-off counting values, and the L on-off counting units except the controller unit respectively count the on-off times of the L reed pipes.
Judging whether the reed switch with the detection mark in the detection state is invalid or not, wherein the method is that when the current on-off count value of the reed switch to be judged is not in the increasing 1 relation with the previous on-off count value, the reed switch is invalid, otherwise, the reed switch is not invalid; the method is that if the current on-off count value of the reed switch to be judged for K times continuously does not increase 1 with the previous on-off count value, the reed switch is invalid, otherwise, the reed switch is not invalid; and K is an integer greater than or equal to 2. The on-off count value adopts a cyclic counting mode, and after the on-off count value reaches the maximum value of the tri-state output counting circuit, 1 is added, and the overflow is changed into 0; taking the 4-bit binary on-off count value output by the tri-state output counting circuit embodiment 2 as an example, the maximum value is 1111, and the next on-off count value satisfying the 1-increasing relationship is 0. And in the read current L on-off count values, the controller unit does not judge and process whether the reed switch with the detection mark in the detection stop state is invalid or not.
Whether the reed switch with the detection mark in the detection state is invalid or not can be judged, and the following method can be adopted: when the current on-off count value accumulated by the reed switch for W times is not increased by 1 with the previous on-off count value, the reed switch fails, otherwise, the reed switch does not fail; and W is an integer greater than or equal to 2.
Whether the reed switch with the detection mark in the detection state is invalid or not can be judged, and the following method can be adopted: if the error between the controlled on-off times of the reed switch and the on-off counting value is smaller than E, the reed switch is not invalid, otherwise, the reed switch is invalid; e is an integer of 1 to G/2(G divided by 2). The counting value of the current life counter is the number of times of on-off control of the reed pipe to be judged. The specific judgment method is that the maximum count value of the on-off count value is set as G, and the count value of the current life counter is modulo G to obtain a remainder Q; and if the read on-off count value of the reed pipe to be judged is V, if one of | V-Q | < E, or | V- (Q-G) | < E, or | V- (Q + G) | < E is satisfied, the reed pipe is not failed, otherwise, the reed pipe is failed. The on-off count value adopts a cyclic counting mode, and after the on-off count value reaches the maximum counting value G of the three-state output counting circuit, 1 is added, and the overflow is changed into 0; taking the 4-bit binary on-off count value output by the tri-state output counting circuit embodiment 2 as an example, the maximum value is 1111, and the next on-off count value is 0; in the judgment expression, comparing V with Q-G is to counteract the influence of smaller V value plus counting overflow and larger Q value; comparing V with Q + G cancels out the larger value of V and the smaller influence of Q on G modulo. After the error E is determined, the maximum count value G of the on-off count value must be more than 2 times of the error E; for example, if E is determined to be 3, the maximum count value G of the on-off count value must be greater than 6, and at this time, both the decimal BCD counter and the binary counter with more than 3 bits satisfy the requirement.
The controller unit and the human-computer interface unit can adjust and display NO and NC duty ratios (namely, setting suction time and release time proportion) of the reed switch, select failure judgment modes, set and display failure judgment parameters, set and display on-off periods of the reed switch and the like according to needs.
In order to reduce the volume and improve the reliability, all or part of the L on-off counting units, the oscillator units and the gating control units are preferably implemented by PAL, GAL, CPLD, FPGA or other programmable logic devices and logic units.
Except for the technical features described in the specification, the method is the conventional technology which is mastered by a person skilled in the art. For example, the controller of the controller unit is selected, and the related peripheral control circuits are designed and programmed to realize the functions thereof; selecting or designing a gating control unit circuit to meet the requirement of decoding gating; selecting or designing a multivibrator of an oscillator unit, and outputting a sampling clock pulse CLK meeting requirements; the electromagnet and the driving circuit of the magnetic control driving unit are selected or designed to meet the requirement of on-off control on the L reed switches; selecting the composition and circuit structure of the human-computer interface unit, and connecting the human-computer interface unit with the controller unit to realize corresponding functions; and the like, are conventional techniques known to those skilled in the art.
Claims (8)
1. A reed switch service life detection method is characterized by comprising the following steps:
Step 1, initializing, namely setting detection marks of L reed pipes to be in a detection state, clearing a service life counter to be 0, and reading L on-off count values for the first time;
Step 2, controlling the on-off of the L reed pipes once, and simultaneously counting the on-off times of the L reed pipes respectively to obtain L on-off count values; the service life counter counts by adding 1;
Step 3, reading the current L on-off count values;
step 4, judging whether the reed switches with the detection marks in the detection state are invalid one by one; setting the detection mark of the reed switch judged to be failed at this time to be in a detection stop state, and taking the count value of the current life counter as the life value of the reed switch judged to be failed at this time;
step 5, if the detection marks of the L reed pipes are still in the detection state, returning to the step 2, otherwise, stopping the detection;
Judging whether the reed switch with the detection mark in the detection state is invalid or not, wherein the method is that when the current on-off count value of the reed switch to be judged is not in the increasing 1 relation with the previous on-off count value, the reed switch is invalid, otherwise, the reed switch is not invalid; the method is that if the current on-off count value of the reed switch to be judged for K times continuously does not increase 1 with the previous on-off count value, the reed switch is invalid, otherwise, the reed switch is not invalid; k is an integer greater than or equal to 2;
The on-off times of the L reed pipes are respectively counted to obtain L on-off counting values, and the L on-off counting values are realized by L on-off counting units with the same structure and composition; the on-off counting unit comprises a pulse generating circuit, an anti-pulse interference circuit and a three-state output counting circuit;
the pulse generating circuit outputs an initial pulse generated by the on-off of the reed switch to the anti-pulse interference circuit; the anti-pulse interference circuit performs pulse filtering on the initial pulse and outputs a counting pulse; the tri-state output counting circuit counts the counting pulse and outputs an on-off counting value;
The anti-pulse interference circuit comprises a shift register, an anti-interference threshold value setter, a ROM (read only memory) and an RS trigger;
The input of the shift register is an initial pulse and a sampling clock pulse, and the output is N-bit sequence data; the anti-interference threshold value setter outputs an anti-interference threshold value; the input of the ROM is N-bit sequence data and an anti-interference threshold, and the output is a first setting signal and a second setting signal; the input of the RS trigger is a first set signal and a second set signal, and the output is a counting pulse; and N is an integer greater than or equal to 2.
2. the reed pipe life detection method according to claim 1, characterized in that:
The shift register samples the initial pulse at the edge of the sampling clock pulse to obtain N-bit sequence data, wherein the N-bit sequence data is the latest N times of sampling values of the initial pulse; the address input of the ROM memory consists of N-bit sequence data and an anti-interference threshold, and the two-bit data output is a first setting signal and a second setting signal respectively;
The anti-interference threshold value is equal to M, and M is an integer which is greater than or equal to 0 and smaller than N/2; the N-bit sequence data and the anti-interference threshold are both N-bit binary data.
3. the reed pipe life detection method according to claim 2, characterized in that: the ROM memory has the function that when the number of '1' in the input N-bit sequence data is more than or equal to N-M, the output first set signal is effective; when the number of '1' in the input N-bit sequence data is less than or equal to M, the output second set signal is valid.
4. the reed pipe life detection method according to claim 3, characterized in that: the RS trigger has the functions that the first setting signal is a setting signal of the RS trigger, and the second setting signal is a reset signal of the RS trigger; the counting pulse is output from the non-inverting output terminal or the inverting output terminal of the RS flip-flop.
5. The reed pipe life detection method according to any one of claims 1 to 4, characterized in that: the device is realized by a device comprising a controller unit, a magnetic control driving unit and an oscillator unit; the oscillator unit outputs a sampling clock pulse.
6. The reed pipe life detection method according to claim 5, characterized in that: the L reed switches are controlled to be switched on and off once, and the controller unit sends a magnetic control driving signal to the magnetic control driving unit to realize the switching control.
7. the reed pipe life detection method according to claim 5, characterized in that: the on-off count values of the L on-off counting units are all output in a three-state buffering mode; the tri-state buffer output ports of all the on-off counting units are all connected in parallel to the counting data input port of the controller unit; the controller unit sends out gating control signals to enable the three-state buffer output ports of the on-off counting units one by one, and corresponding on-off counting values are read in from the counting data input port.
8. The reed pipe life detection method according to claim 7, characterized in that: the apparatus further includes a gating control unit; the controller unit sends an address coding signal of the on-off counting unit to the gating control unit, and the gating control unit decodes the address coding signal of the on-off counting unit to obtain a gating control signal.
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