CN208112622U - A kind of radio frequency front-end devices are from control interface arrangement - Google Patents

Abstract

The utility model discloses a kind of radio frequency front-end devices from control interface arrangement, based on MIPI RFFE v2.0 agreement, and it can be integrated in full sheet, the utility model all uses digital logic unit and basic circuit elements to build, to be easily achieved the Embedded from control device circuit, it can be integrated into locating in radio-frequency front-end sheet of elements from control device, only pass through three signal wire VIO of MIPI RFFE interface, SCLK, SDAT can realize the flexible control of radio-frequency front-end element.Processor output pin used in the utility model is less, therefore the control occupied printed circuit plate suqare of signal is also less, without using additional plate grade component, therefore cost is relatively low needed for implementation the utility model, and the occupied device space is also smaller, miniaturization, cost effective design conducive to mobile device are highly suitable for the control of the various radio frequency front-end devices in mobile industry.

Description

A kind of radio frequency front-end devices are from control interface arrangement

Technical field

The utility model belongs to mobile communication technology field, and in particular to a kind of radio frequency front-end devices are from control interface arrangement Design.

Background technique

With the high speed development of mobile communication technology, the equipment such as modern mobile product such as mobile phone, removable computer are Develop towards lighter and thinner direction.In these present mobile communication equipment other than using RF transceiver, also widely Power amplifier, low-noise amplifier, filter, switch, power management module and antenna tuner etc. has been used to penetrate Frequency front-end devices.The overwhelming majority in these radio frequency front-end devices is controlled and is worked by number bus by main controller The configuration of mode.

For unified industry standard, many standardization bodies have formulated the communication standard suitable for mobile device.Wherein most draw People gazes at and application range is most commonly used, to belong to by Mobile Industry Processor Interface (Mobile Industry Processor Interface, MIPI) alliance formulate radio-frequency front-end (Radio Frequency Front End, RFFE) control Interface processed.MIPI PFFE interface is a kind of easy interface for radio frequency system, can be carried out with the logical device of lesser amt The integrated investment to reduce cost.MIPI RFFE control interface uses three signal wires, and wherein SCLK is bus clock signal Line, SDAT are data signal bus line, and VIO is bus voltage reference/power supply line.The data that high-speed may be implemented in the interface pass It is defeated and easy to use, it is widely used today on the radio frequency front-end devices of mobile industry.

In order to realize the control by MIPI RFFE interface for radio frequency front-end devices, can using directly controlling or The methods of controlled by programmable logic device such as FPGA.As shown in Figure 1, the control of radio frequency front-end devices can be by mobile device Processor directly realizes that processor, which passes through, exports a series of control signal CTRL1, CTRL2, CTRL3 ..., CTRLN-1, CTRLN puts power management module, RF switch, filter, low-noise amplifier and the power inside mobile device to realize The radio frequency front-end devices such as big device directly control.The method directly controlled is easy to use, but it is defeated to consume a large amount of processor Pin out, while the printed circuit board that can also consume large area is used as signal lead, this gradually tends to minimize in mobile device Today it is clearly infeasible, and since printed circuit plate suqare is larger, cost is also higher.

As shown in Fig. 2, the control of radio frequency front-end devices can also realize indirect control by MIPI RFFE interface by FPGA System.The processor of mobile device controls FPGA by three signal wires VIO, SCLK, SDAT of MIPI RFFE interface System, FPGA export a series of control signal CTRL1, CTRL2, CTRL3 ..., and CTRLN-1, CTRLN are controlled inside mobile device The radio frequency front-end devices such as power management module, RF switch, filter, low-noise amplifier and power amplifier.This For kind method compared with the method that processor directly controls, the processor output pin of consumption is less, therefore the processor money consumed Source is less, and the occupied printed circuit plate suqare of signal lead is also less.But this method needs to occupy additional printing Board area puts the programmable logic device such as FPGA and provides control signal lead from FPGA to radio frequency front-end devices, Consumed board area is also more.And cost will increase using additional FPGA device, be equally also unfavorable for movement and set Standby miniaturization.

In addition, traditional configurable register schemes as shown in figure 3, in order to realize 32 eight bit register data (from REGDATA0[7:0] REGDATA31 [7 is arrived:0] output) is needed using 32 output registers, such as D1 to D32 institute in Fig. 3 Show.The number for selecting internal register data whether to export and export by controlling the enable pin ENA of each output register Amount.If desired the data of internal 32 registers are all exported, is needed using 32 output registers, while also having 32 groups 8 output pins are (from OUT0 [7:0] OUT31 [7 is arrived:0]).So in traditional scheme, if to export 32 eight bit registers Data, need to use 32 groups 8 output pins, that is, 256 output pins.Therefore the configurable register of this tradition Scheme can consume more output pin resource when needing to export more register data, therefore can occupy more chip face Product, is unfavorable for the requirement of device miniaturization.

Utility model content

Purpose of the utility model is to solve the above problems in the prior art, propose a kind of radio frequency front-end devices From control interface arrangement, it is based on MIPI RFFE v2.0 agreement, and can be integrated in full sheet, without using additional plate grade component, It is smaller to occupy the device space, miniaturization, cost effective design conducive to mobile device.

The technical solution of the utility model is：A kind of radio frequency front-end devices are from control interface arrangement, including sequentially connected connect Mouth logic module, data decoder module and configurable register module.The input terminal of interface logic biock is from control interface arrangement Input terminal, respectively with bus clock signal line SCLK, data signal bus line SDAT and bus voltage reference/power supply line VIO connection.Data decoder module is used to be decoded the bus data received, input terminal connecting interface logic module Output end, output end connect the input terminal of configurable register module.Configurable register module is used to fill to from control interface The output end set is configured, and output end is connect as the output end from control interface arrangement with radio frequency front-end devices.

The utility model has the beneficial effects that：The utility model proposes what can be implemented to be assisted based on MIPI RFFE v2.0 The radio frequency front-end devices of view are from the concrete scheme for controlling interface arrangement, before being particularly suitable for the radio frequency of the use of the industry interface protocol End-apparatus part.The utility model all uses Digital Logic basic unit to build, to be easily achieved out of, control device circuit piece It is integrated, and occupied space is also small, is highly suitable for the control of the various radio frequency front-end devices in mobile industry.

Further, interface logic biock include double mode reset submodule, bus clock SCLK input driven submodule and Bus data SDAT bi-directional drive submodule.Input terminal and bus voltage reference/power supply line VIO of double mode reset submodule connect It connects, for detecting bus input and output voltage benchmark/state of power supply signal and the state of controller power supply, exports simultaneously RSEN signal come carry out from control interface arrangement reset, and will from control interface arrangement be respectively placed in off state, starting state or Current state.The input terminal of bus clock SCLK input driven submodule is connect with bus clock signal line SCLK, for driving From the internal clock cable SCLK of control interface arrangement.The input terminal and data signal bus of bus data SDAT bi-directional drive submodule Line SDAT connection, for selecting input or the output state of data signal bus line SDAT, so that bus data is respectively placed in High resistant input or output state.

Further, double mode reset submodule includes power on detection circuit, VIO signal condition change detection circuit, first Inverter circuit, the second inverter circuit, biconditional gate circuit and the first AND gate circuit.Power on detection circuit includes field-effect Pipe M1, resistance R1 and capacitor C1, the source electrode of field-effect tube M1 connect to power supply, grid with drain electrode be connected, and respectively with resistance The second input terminal connection of one end of R1, one end of capacitor C1, the input terminal of the first inverter circuit and biconditional gate circuit, The other end of resistance R1 connects to power supply, and the other end of capacitor C1 is connected to ground.The output end of first inverter circuit and second The input terminal of inverter circuit connects, and the output end of the second inverter circuit is connect with the first input end of biconditional gate circuit, The output end of biconditional gate circuit is connect with the first input end of the first AND gate circuit.VIO signal condition change detection circuit packet Include resistance R2, resistance R3, resistance R4, capacitor C2, transistor Q1 and hysteresis comparator, one end of resistance R2 and one end of resistance R3 Be connected to the input terminal of double mode reset submodule, the other end of resistance R2 respectively with the collector of transistor Q1, transistor Q1 Base stage and hysteresis comparator first input end connection, the emitter of transistor Q1 is connected to ground, the other end of resistance R3 It is connect respectively with the second input terminal of one end of resistance R4, one end of capacitor C2 and hysteresis comparator, the other end of resistance R4 It being connected to ground with the other end of capacitor C2, the output end of hysteresis comparator is connect with the second input terminal of the first AND gate circuit, Output end of the output end of first AND gate circuit as double mode reset submodule.

Above-mentioned further scheme has the beneficial effect that：The utility model uses double mode reset submodule, fills from control interface Set power on Rapid reset when the variation of VIO signal condition and enabled described from control interface arrangement, realize described from control interface arrangement To the stability contorting of radio-frequency front-end element, the generation of control disorder when preventing system electrification and VIO signal condition from switching.Compared to Traditional POR electrification reset module, double mode reset submodule used by the utility model incorporate power-on reset function and VIO The Interface status turn function that signal is controlled, can be better achieved it is described from control interface arrangement in state switching and system The response of electricity.

Further, data decoder module includes state machine submodule, SSC detection sub-module and data output submodule Block.State machine submodule is used to control the state of data decoder module, and the state of control data decoder module includes that RST interface is silent Recognize state, ADD1 command frame data accumulation storage state, ACK1 command frame responsive state, ADD2 data frame add up storage state, ACK2 data frame responsive state, the response of ACK3 data frame jumps state, ACK4 read operation responsive state, ACK5 read operation terminate to ring Answer state and NUL redundant operation state.The input terminal of SSC detection sub-module inputs driven submodule with bus clock SCLK respectively Output end and bus data SDAT bi-directional drive submodule output end connection, for detecting RFFE data signal bus Homing sequence.The input terminal of data output sub-module is defeated with the output end of double mode reset submodule and bus clock SCLK respectively The output end connection for entering driven submodule, is used for RFFE bus in the case where data decoder module is in ACK4 read operation responsive state The data to be read are output to one by one on data signal bus line SDAT from a high position to low level.

Above-mentioned further scheme has the beneficial effect that：The utility model adoption status loom module connects to control described from control Mouthful device simultaneously carries out switching corresponding to the state of bus different conditions, enhance it is described from control interface arrangement for MIPI RFFE The response of interface bus state enhances the reliability from control interface arrangement.

Further, SSC detection sub-module includes d type flip flop D1, d type flip flop D2 and the second AND gate circuit, d type flip flop The Clk pin of D1 and the Clk pin of d type flip flop D2 are connect with the output end of bus data SDAT bi-directional drive submodule, D touching The ENA pin of the ENA pin and d type flip flop D2 of sending out device D1 is connect with MARK signal, the D pin and d type flip flop of d type flip flop D1 The D pin of D2 with bus clock SCLK input driven submodule output end connect, the Q pin of d type flip flop D1 and second and Second input terminal of gate circuit connects, and the Q pin of d type flip flop D2 is connect with the first input end of the second AND gate circuit, second and Output end of the output end of gate circuit as SSC detection sub-module exports SSCDETECT signal.

Further, data output sub-module includes multiple selector S1~S6, d type flip flop D3~D5, the first multi input OR circuit, decoder and the second multi input OR circuit；The first input end of multiple selector S1~S4 connects with power supply It connects, and is connect respectively with the first input end of the input terminal of decoder, the Q pin of d type flip flop D3 and multiple selector S6, it is more The second input terminal of road selector S1~S4 is connected to ground, and the Q pin with the input terminal of decoder, d type flip flop D3 respectively And multiple selector S6 first input end connection, the output end of multiple selector S1~S4 with the D pin of d type flip flop D3 Connection, the output end of decoder are defeated with the first of each input terminal of the first multi input OR circuit and multiple selector S5 respectively Enter end connection, the output end of multiple selector S5 is connect with the D pin of d type flip flop D4, and the output end and D of multiple selector S6 touches Send out the D pin connection of device D5, output of the Clk pin of d type flip flop D3~D5 with bus clock SCLK input driven submodule End connection, the Reset pin of d type flip flop D3~D5 are connect with the output end of double mode reset submodule, and the Q of d type flip flop D4 draws Foot is connect with the second input terminal of multiple selector S5, and exports READFIN signal, the Q pin of d type flip flop D5 respectively with SCLK The second input terminal and the second multi input OR circuit of the eight bit data signal of rising edge clock input, multiple selector S6 Each input terminal is connected with output end, and exports SDATOUT signal.

Above-mentioned further scheme has the beneficial effect that：The utility model realizes MIPI using data output sub-module Data double-way transmission on RFFE bus data line SDAT, make data can be written into and reads it is described from control interface arrangement, increase The flexibility and reliability controlled from control interface arrangement for late-class circuit.

Further, configurable register module includes multiple selector S7~S10 and d type flip flop D7~D42, D touching The Clk pin for sending out device D7~D42 is connect with from the internal clock cable SCLK of control interface arrangement, d type flip flop D7~D42's Reset pin is connect with RSEN signal, the D pin of d type flip flop D7~D38 with from 32 registers inside control interface arrangement Output end connects one to one, the D pin of d type flip flop D7~D38 respectively with the second input terminal of multiple selector S7~S10 Connection, the first input end of multiple selector S7~S10 are connect with from the output end of mask register inside control interface arrangement, The output end of multiple selector S7~S10 and the D pin of d type flip flop D39~D42 connect one to one, d type flip flop D39~D42 Q pin as from control interface arrangement output end, connect with radio frequency front-end devices.

Above-mentioned further scheme has the beneficial effect that：The utility model realizes internal control using configurable register module Whole outputs of register control signal processed, using 4 groups 8 output pins, by configuring internal configurable register mould Block, to export totally 256 control signals inside control device in 32 control registers.It can configure compared to traditional Register module, the scheme that the utility model is proposed can realize more control signal output with less output pin, The control signal that output pin is exported can be switched by MIPI RFFE interface flexible, make it possible to and be applied to have not In the various radio frequency front-end devices required with control.

Detailed description of the invention

Fig. 1 show mobile device processor in the prior art and directly controls radio frequency front-end devices schematic diagram.

Fig. 2 show mobile device processor in the prior art and by FPGA indirectly controls radio frequency front-end devices schematic diagram.

Fig. 3 is shown can configure register architecture schematic diagram in the prior art.

Fig. 4 show a kind of radio frequency front-end devices provided by the embodiment of the utility model from control interface arrangement structural block diagram.

Fig. 5 show double mode reset submodular circuits structural schematic diagram provided by the embodiment of the utility model.

Fig. 6 show state machine submodule status diagram provided by the embodiment of the utility model.

Fig. 7 show SSC detection sub-module and data output sub-module circuit structure provided by the embodiment of the utility model Schematic diagram.

Fig. 8 show configurable register module electrical block diagram provided by the embodiment of the utility model.

Fig. 9 show radio frequency front-end devices provided by the embodiment of the utility model and uses signal from control interface arrangement connection Figure.

Description of symbols：

100- interface logic biock, 200- data decoder module, 300- can configure register module；

110- double mode reset submodule, 120- bus clock SCLK input driven submodule, 130- bus data SDAT are bis- To driven submodule；

The first inverter circuit of 111-, the second inverter circuit of 112-, 113- biconditional gate circuit, 114- first and door electricity Road, 115- hysteresis comparator；

210- state machine submodule, 220-SSC detection sub-module, 230- data output sub-module；

The second AND gate circuit of 221-, the first multi input of 231- OR circuit, 232- decoder, the second multi input of 233- or door Circuit.

Specific embodiment

It is described in detail the illustrative embodiments of the utility model with reference to the drawings.It should be appreciated that showing in attached drawing It is only exemplary out with the embodiment of description, it is intended that illustrate the principles of the present invention and spirit, and not limit this The range of utility model.

The utility model embodiment provides a kind of radio frequency front-end devices from control interface arrangement structural block diagram, as shown in figure 4, Including sequentially connected interface logic biock 100, data decoder module 200 and configurable register module 300；Interface logic mould The input terminal of block 100 be from control interface arrangement input terminal, respectively with bus clock signal line SCLK, data signal bus line SDAT and bus voltage reference/power supply line VIO connection；Data decoder module 200 is used to carry out the bus data received Decoding, the output end of input terminal connecting interface logic module 100, output end connect the defeated of configurable register module 300 Enter end；Configurable register module 300 is used to configure to from the output end of control interface arrangement, and output end is used as and connects from control The output end of mouth device, connect with radio frequency front-end devices.

Interface logic biock 100 includes double mode reset submodule 110, bus clock SCLK input 120 and of driven submodule Bus data SDAT bi-directional drive submodule 130.The input terminal and bus voltage reference/power supply line of double mode reset submodule 110 VIO connection, for detecting bus input and output voltage benchmark/state of power supply signal and the state of controller power supply, together When export RSEN signal come carry out from control interface arrangement reset, and will from control interface arrangement be respectively placed in off state, starting State or current state.The input terminal of bus clock SCLK input driven submodule 120 is connect with bus clock signal line SCLK, For driving the internal clock cable SCLK from control interface arrangement；The input terminal of bus data SDAT bi-directional drive submodule 130 with Data signal bus line SDAT connection, for selecting input or the output state of data signal bus line SDAT, thus by bus Data are respectively placed in high resistant input or output state.

As shown in figure 5, double mode reset submodule 110 include power on detection circuit, VIO signal condition change detection circuit, First inverter circuit 111, the second inverter circuit 112, biconditional gate circuit 113 and the first AND gate circuit 114.First is anti- Phase device circuit 111, the second inverter circuit 112 and biconditional gate circuit 113 constitute electrification reset pulse-generating circuit, in system A pulse signal is generated when powering on.Power on detection circuit includes field-effect tube M1, resistance R1 and capacitor C1, field-effect tube M1's Source electrode (i.e. 1 end in figure) connects to power supply, grid (i.e. 2 ends in figure) with drain electrode (i.e. 3 ends in figure) be connected, and respectively with resistance One end (i.e. 2 ends in figure) of R1, one end (i.e. 1 end in figure) of capacitor C1, the first inverter circuit 111 input terminal (i.e. 1 in figure End) and biconditional gate circuit 113 the second input terminal (i.e. 2 ends in figure) connection, the other end (i.e. 1 end in figure) of resistance R1 with Power supply connection, the other end (i.e. 2 ends in figure) of capacitor C1 are connected to ground.The output end of first inverter circuit 111 is (i.e. 2 in figure End) it is connect with the input terminal (i.e. 1 end in figure) of the second inverter circuit 112, the output end of the second inverter circuit 112 (is schemed In 2 ends) connect with the first input end (i.e. 1 end in figure) of biconditional gate circuit 113, the output end of biconditional gate circuit 113 is (i.e. 3 end in figure) it is connect with the first input end (i.e. 1 end in figure) of the first AND gate circuit 114.VIO signal condition change detection circuit Including resistance R2, resistance R3, resistance R4, capacitor C2, transistor Q1 and hysteresis comparator 115, one end of resistance R2 is (i.e. 1 in figure End) with one end (i.e. 1 end in figure) of resistance R3 it is connected to the input terminal of double mode reset submodule 110, the other end of resistance R2 (i.e. 2 ends in figure) respectively with the collector of transistor Q1 (i.e. 1 end in figure), transistor Q1 base stage (i.e. 2 ends in figure) and late The first input end (i.e. 1 end in figure) of stagnant comparator 115 connects, and the emitter (i.e. 3 ends in figure) of transistor Q1 is connected to ground, electricity Hinder the other end (i.e. 2 ends in figure) one end (i.e. 1 end in figure) with one end of resistance R4 (i.e. 1 end in figure), capacitor C2 respectively of R3 And the second input terminal (i.e. 2 ends in figure) connection of hysteresis comparator 115, the other end (i.e. 2 ends in figure) and capacitor of resistance R4 The other end (i.e. 2 ends in figure) of C2 is connected to ground, the output end (i.e. 3 ends in figure) of hysteresis comparator 115 and first and door electricity Second input terminal (i.e. 2 ends in figure) on road 114 connects, and the output end (i.e. 3 ends in figure) of the first AND gate circuit 114 is multiple as bimodulus The output end of bit submodule 110.

First AND gate circuit 114 by the output signal of biconditional gate circuit 113 and hysteresis comparator 115 carry out and operation, It exports a system and enables reset signal RSEN.Signal RSEN is used as the reset from control interface arrangement, enables and is turning off Jumping between state, starting state and current state.When signal RSEN is in high level, it is in existing from control interface arrangement State, it is in an off state from control interface arrangement when signal RSEN is in low level, when one negative sense of appearance on signal RSEN When pulse signal, starting state is in from control interface arrangement.

In the utility model embodiment, bus clock SCLK inputs driven submodule 120 and the two-way drive of bus data SDAT Data buffer structure generally in the art can be used to realize for mover module 130, details are not described herein.

Data decoder module 200 includes state machine submodule 210, SSC detection sub-module 220 and data output sub-module 230.State machine submodule 210 is used to control the state of data decoder module 200, controls the state packet of data decoder module 200 It is tired to include RST interface default conditions, ADD1 command frame data accumulation storage state, ACK1 command frame responsive state, ADD2 data frame Storage state, ACK2 data frame responsive state, the response of ACK3 data frame is added to jump state, ACK4 read operation responsive state, ACK5 Read operation terminates responsive state and NUL redundant operation state.

In the utility model embodiment, Moore type finite state machine generally in the art is can be used in state machine submodule 210 Circuit or Mealy type finite state machine circuit realize that details are not described herein.

As shown in fig. 6, state machine submodule 210 is selected according to the state of MIPI bus VIO, SCLK and SDAT into following Each state, each circle in Fig. 6 corresponds to individual state, and is specified by capitalization, corresponds under capitalization 4 binary codings shown by side.Here is the description of these states：

(1)RST：Interface default conditions.When the output signal RSEN of double mode reset submodule 110 changes to low electricity from high level Usually, state machine submodule 210 carries out reset operation from control interface arrangement to this into this state.In this case, originally from control Interface arrangement is packed into corresponding initial value to internal register automatically, and this is set from each output pin of control interface arrangement It is set to default value.After the completion of the above operation, state is directed toward ADD1 automatically by state machine submodule 210, in SCLK bus clock Next clock falling edge arrive when enter state ADD1.

(2)ADD1：Command frame data accumulation storage state.To this from control interface arrangement carry out immediate restoration of service it Afterwards, state machine submodule 210 is automatically into state ADD1.In this case, the control of state machine submodule 210 is originally from control interface dress It sets and samples SDAT bus data in each clock falling edge arrival of SCLK bus clock, and successively from a high position to low level The data that sampling obtains are stored in this in the order frame register inside control interface arrangement.Sampling, the 12nd SDAT is total For line number after, state machine submodule 210 resets this from the counting accumulator inside control interface arrangement, and is automatically directed toward state ACK1 enters state ACK1 when next clock falling edge of SCLK bus clock arrives.

(3)ACK1：Command frame responsive state.12 originally have been sampled from control interface arrangement in the control of state machine submodule 210 After command frame on data signal bus line SDAT, state machine submodule 210 is automatically into state ACK1.In this case, shape The control of state loom module 210 originally samples SDAT bus data when SCLK clock bus failing edge arrives from control interface arrangement, and The odd result of the 12 SDAT data/address bus command frames sampled in itself and state ADD1 is compared simultaneously.If life Enable the odd result of frame and the SDAT bus data sampled not identical, state is directed toward NUL by state machine submodule 210.Such as The odd result of fruit command frame is identical with the SDAT bus data sampled, and state machine submodule 210 automatically controls this from control Interface arrangement continues to judge 4 chip address data segment Slave Address (SA) in 12 SDAT data/address bus command frames. If 4 chip address data segments and this built-in 4 core from control interface arrangement in 12 SDAT data/address bus command frames Piece address date is not identical, and state is directed toward NUL by state machine submodule 210.If 4 in 12 SDAT data/address bus command frames Position chip address data segment is identical with this built-in 4 chip address data from control interface arrangement, and state machine submodule 210 is certainly Dynamic control originally continues to judge 3 read write command sections in 12 SDAT data/address bus command frames from control interface arrangement.If 12 3 read write command sections in SDAT data/address bus command frame are write order (Write), and state machine submodule 210 is automatically by state It is directed toward ADD2.If 3 read write command sections in 12 SDAT data/address bus command frames are read command (Read), state machine submodule State is directed toward ACK4 automatically by block 210.If 3 read write command sections in 12 SDAT data/address bus command frames are neither write life It enables nor state is directed toward NUL by read command, state machine submodule 210.

(4)ADD2：Data frame adds up storage state.12 SDAT data/address bus orders are judged in state machine submodule 210 3 read write command sections in frame is after write order, state machine submodule 210 are automatically into state ADD2.In this case, state Originally from control interface arrangement, when each clock falling edge of SCLK bus clock arrives, sampling SDAT is total for the control of loom module 210 Line number evidence, and the data that sampling obtains successively are stored in this from the data frame register inside controller from a high position to low level In.After sampling the 8th SDAT bus data, state machine submodule 210 adds up this from the counting inside control interface arrangement Device is reset, and state is directed toward ACK2 automatically, enters state when next clock falling edge of SCLK bus clock arrives ACK2。

(5)ACK2：Data frame responsive state.8 originally have been sampled from control interface arrangement in the control of state machine submodule 210 After data frame on SDAT data/address bus, state machine submodule 210 is automatically into state ACK2.In this case, state loom The control of module 210 originally samples SDAT bus data when SCLK clock bus failing edge arrives from control interface arrangement, and simultaneously will The odd result of itself and the 8 SDAT data/address bus data frames sampled in state ADD2 compares.If data frame Odd result and the SDAT bus data sampled be not identical, and state is directly directed toward ACK3 by state machine submodule 210.If The odd result of data frame is identical with the SDAT bus data sampled, then state machine submodule 210 judges 12 SDAT numbers According to the value of 5 bit register address date section Address (A) in bus line command frame, judge the register of write-in to be from deposit Device 0, register 1 to register 30, which register in register 31.If being register 28 by the register of write-in, It is assigned to data output flag position by the 0th of data frame register, and the value of data frame register is assigned to register 28.If By other registers that the register of write-in is in above-mentioned register, then directly the value of data frame register is assigned to post accordingly Storage.5th, 6,7 composition mask register SEL [2 of register 28:0], in the case where state machine submodule 210 is in the state, Register module 300 be can configure according to mask register SEL [2:0] described from the data controlled on device output port to configure.? State machine submodule 210 control this from control interface arrangement complete above-mentioned register write operation after, state machine submodule 210 will State is directed toward ACK3.

(6)ACK3：Data frame response jumps state.In this case, state is directed toward ADD1 by state machine submodule 210, And enter leave state ACK3 when next SCLK bus clock failing edge arrives, into state ADD1.

(7)ACK4：Read operation responsive state.Judge in 12 SDAT data/address bus command frames in state machine submodule 210 3 read write command sections be read command after, state machine submodule 210 is automatically into state ACK4.In this case, state loom The first set read command flag bit of module 210 and data bus status flag bit, state machine submodule 210 judges 12 SDAT later The value of 5 bit register address date section Address (A) in data/address bus command frame, judge be by the register for reading data Which register from register 0, register 1 to register 30, register 31.State machine submodule 210 has judged to read The data in corresponding register are fitted into data frame register after the register of data out, state machine submodule 210 will later State is directed toward ACK5.

(8)ACK5：Read operation terminates detecting state.In the corresponding registers data that state machine submodule 210 will be read After being fitted into data frame register, state machine submodule 210 is automatically into state ACK5.In this case, state machine submodule 210 detect the value of read command end mark position when each clock falling edge of SCLK bus clock arrives.If detected The value of read command end mark position is 1, then is zero by read command flag bit and data bus status mark position, and by state machine 210 state of submodule is directed toward ADD1.If detecting that the value of read command end mark position is 0, state machine submodule 210 is by state It continues to point to ACK5 and continues to test the value of read command end mark position when next SCLK bus clock failing edge arrives, directly Until the value position 1 for detecting read command end mark position.

(9)NUL：Redundant operation state.In this case, state machine submodule 210 detects each of SCLK bus clock A clock falling edge simultaneously counts.After state machine submodule 210 count down to the 9th clock falling edge, state machine submodule 210 will This resets from the counting accumulator inside control interface arrangement, and state is directed toward ACK3 automatically.

The input terminal of SSC detection sub-module 220 respectively with bus clock SCLK input driven submodule 120 output end with And the output end connection of bus data SDAT bi-directional drive submodule 130, for detecting the starting sequence of RFFE data signal bus Column, after detecting the homing sequence of RFFE data signal bus, it is tired that state machine submodule 210 jumps to ADD1 order frame data Storage state is added to start to receive the data in RFFE bus.The input terminal of data output sub-module 230 is sub with double mode reset respectively The output end connection of output end and bus clock SCLK the input driven submodule 120 of module 110, for decoding mould in data Block 200 is under ACK4 read operation responsive state the data that RFFE bus to be read being output to bus one by one from a high position to low level On data signal line SDAT.

As shown in fig. 7, SSC detection sub-module 220 includes d type flip flop D1, d type flip flop D2 and the second AND gate circuit 221, The output of the Clk pin of d type flip flop D1 and the Clk pin of d type flip flop D2 with bus data SDAT bi-directional drive submodule 130 End connection, the ENA pin of d type flip flop D1 and the ENA pin of d type flip flop D2 are connect with MARK signal, and the D of d type flip flop D1 draws The D pin of foot and d type flip flop D2 are connect with the output end of bus clock SCLK input driven submodule 120, d type flip flop D1's Q pin is connect with the second input terminal (i.e. 2 ends in figure) of the second AND gate circuit 221, the Q pin of d type flip flop D2 and second and door The first input end (i.e. 1 end in figure) of circuit 221 connects, and the output end (i.e. 3 ends in figure) of the second AND gate circuit 221 is used as SSC The output end of detection sub-module 220 exports SSCDETECT signal.

In SSC detection sub-module 220, d type flip flop D1 and d type flip flop D2 are detecting data signal bus line respectively Level value and the output on bus clock signal line SCLK at that time, d type flip flop D1 and D are stored when the rising edge and failing edge of SDAT The output signal of trigger D2 obtains output signal SSCDETECT after the second AND gate circuit 221 does logical AND operation.When After SSC detection sub-module 220 detects SSC sequence initial conditions, output signal SSCDETECT is set to 1, otherwise output signal SSCDETECT always remains as 0.Output signal SSCDETECT is for state machine submodule 210 in ADD1 command frame data accumulation Whether detection receives SSC homing sequence from control interface arrangement under storage state, if output signal SSCDETECT is 1, from control Interface arrangement starts to receive order frame data at state ADD1, if output signal SSCDETECT is 0, from control interface arrangement The state ADD1 of being maintained at is failure to actuate.

As shown in fig. 7, data output sub-module 230 includes multiple selector S1~S6, d type flip flop D3~D5, more than first Input OR circuit 231, decoder 232 and the second multi input OR circuit 233.The first input of multiple selector S1~S4 End (i.e. 1 end in figure) connect to power supply, and respectively with the input terminal of decoder 232, the Q pin of d type flip flop D3 and multichannel The first input end (i.e. 1 end in figure) of selector S6 connects, and the second input terminal (i.e. 2 ends in figure) of multiple selector S1~S4 is equal It is connected to ground, and the first input with the input terminal of decoder 232, the Q pin of d type flip flop D3 and multiple selector S6 respectively (i.e. 1 end in figure) connection is held, the output end (i.e. 3 ends in figure) of multiple selector S1~S4 connects with the D pin of d type flip flop D3 Connect, the output end of decoder 232 respectively with each input terminal of the first multi input OR circuit 231 and multiple selector S5 One input terminal (i.e. 1 end in figure) connection, the output end (i.e. 3 ends in figure) of multiple selector S5 and the D pin of d type flip flop D4 connect It connects, the output end (i.e. 3 ends in figure) of multiple selector S6 is connect with the D pin of d type flip flop D5, and the Clk of d type flip flop D3~D5 draws Foot with bus clock SCLK input driven submodule 120 output end connect, the Reset pin of d type flip flop D3~D5 with The output end of double mode reset submodule 110 connects, and the Q pin of d type flip flop D4 (is schemed with the second input terminal of multiple selector S5 In 2 ends) connection, and export READFIN signal, the Q pin of the d type flip flop D5 eight-digit number with the input of SCLK rising edge clock respectively It is believed that number DATAOUT [7:0], the second input terminal (i.e. 2 ends in figure) and the second multi input OR circuit of multiple selector S6 233 each input terminal is connected with output end, and exports SDATOUT signal.

In data output sub-module 230, multiple selector S1~S4 and d type flip flop D3 composition counter are total to clock Rising edge clock on line clock cable SCLK is counted, and prepares the previous of output data in data signal bus line SDAT The eight bit data for preparing output is taken out the input terminal for being sent to multiple selector S6 by a SCLK rising edge clock.Multiple selector S6 With d type flip flop D5 in subsequent SCLK rising edge clock by the eight bit data DATAOUT [7 of input:0] successively from highest order to most Low level is output to SDATOUT output end.Multiple selector S5 and d type flip flop D4 constitute counter on clock bus SCLK when Clock rising edge is counted, when data output sub-module 230 outputs eight bit data DATAOUT [7:0] it after lowest order, will count It is set to 1 according to the output signal READFIN of output sub-module 230, expression has finished on read operation data output state, state machine Submodule 210, which will automatic jump to ACK5 read operation, terminates detecting state.

As shown in figure 8, configurable register module 300 includes multiple selector S7~S10 and d type flip flop D7~D42, The Clk pin of d type flip flop D7~D42 is connect with from the internal clock cable SCLK of control interface arrangement, d type flip flop D7~D42's Reset pin is connect with RSEN signal, the D pin of d type flip flop D7~D38 with from 32 registers inside control interface arrangement Output end connects one to one, the D pin of d type flip flop D7~D38 respectively with the second input terminal of multiple selector S7~S10 (i.e. 2 ends in figure) connection, the first input end (i.e. 1 end in figure) of multiple selector S7~S10 is and inside control interface arrangement The output end of mask register connects, the output end (i.e. 3 ends in figure) and d type flip flop D39~D42 of multiple selector S7~S10 D pin connect one to one, the Q pin of d type flip flop D39~D42 is as the output end from control interface arrangement, with radio-frequency front-end Device connection.

In configurable register module 300, d type flip flop D7~D38 is used to store and buffer from REGDATA0 [7:0] it arrives REGDATA31[7:0] internal register data.REGDATA0[7:0], [7 REGDATA1:0] ..., [7 REGDATA30:0], REGDATA31[7:It 0] is from control interface arrangement internal register 0, register 1 ..., register 30, the output end of register 31. Multiple selector S7~S10 is according to mask register SEL [2:0] Configuration Values are selected from REGDATA0 [7:0] REGDATA31 is arrived [7:This 4 groups of 8 data are output to output pin OUT0 [7 by output register D39~D42 by 4 groups of data in 0]:0], OUT1[7:0], [7 OUT2:0], [7 OUT3:0] on.By this method, it may be implemented internal with 4 groups of 8 output pins outputs The data of 32 groups of eight bit registers, namely the control signal of 256 internal registers is only exported by 32 output pins.4 groups defeated The output data on a foot is by mask register SEL [2 out:0] value determines, is being in data frame response shape from control interface arrangement Under state ACK2, multiple selector S7~S10 is according to SEL [2:0] value is by corresponding REGDATA0 [7:0]~REGDATA31 [7: 0] 4 groups of register datas in are sent to output end OUT0 [7 by output register D39~D42:0], [7 OUT1:0], OUT2 [7:0], [7 OUT3:0] on.

Radio frequency front-end devices provided by the embodiment of the utility model can be integrated from control interface arrangement in full sheet, and be based on MIPI RFFE v2.0 agreement, as shown in figure 9, all use digital logic unit and basic circuit elements to build from control interface arrangement, from And it is easily achieved the Embedded from control device circuit, it can be integrated into locating in radio-frequency front-end sheet of elements from control device.Only The flexible control of radio-frequency front-end element can be realized by three signal wires VIO, SCLK, SDAT of MIPI RFFE interface.Cause This due to the utility model can Embedded, used processor output pin is also less, thus control signal it is occupied Printed circuit plate suqare is also less, and the utility model is without using additional plate grade component.Therefore it is practical new to implement this Cost is relatively low needed for type, and the occupied device space is also smaller, conducive to mobile device miniaturization, cost effective set Meter is highly suitable for the control of the various radio frequency front-end devices in mobile industry.

Those of ordinary skill in the art will understand that the embodiments described herein, which is to help reader, understands this reality With novel principle, it should be understood that the scope of the present invention is not limited to such specific embodiments and embodiments. Those skilled in the art can be made according to the technical disclosures disclosed by the utility model it is various do not depart from it is practical Novel substantive various other specific variations and combinations, these variations and combinations are still within the protection scope of the present invention.

Claims (7)

1. a kind of radio frequency front-end devices from control interface arrangement, which is characterized in that including sequentially connected interface logic biock (100), data decoder module (200) and configurable register module (300)；

The input terminal of the interface logic biock (100) is the input terminal from control interface arrangement, is believed respectively with bus clock Number line SCLK, data signal bus line SDAT and bus voltage reference/power supply line VIO connection；

The data decoder module (200) is for being decoded the bus data received, input terminal connecting interface logic The output end of module (100), output end connect the input terminal of configurable register module (300)；

The configurable register module (300) is used to configure to described from the output end of control interface arrangement, output end As the output end from control interface arrangement, it is connect with radio frequency front-end devices.

2. radio frequency front-end devices according to claim 1 from control interface arrangement, which is characterized in that the interface logic biock It (100) include double mode reset submodule (110), bus clock SCLK input driven submodule (120) and bus data SDAT bis- To driven submodule (130)；

The input terminal of the double mode reset submodule (110) is connect with bus voltage reference/power supply line VIO, for detecting bus The state of input and output voltage benchmark/power supply signal state and controller power supply, while RSEN signal is exported to carry out The reset from control interface arrangement, and off state, starting state or existing shape are respectively placed in from control interface arrangement by described State；

The input terminal of bus clock SCLK input driven submodule (120) is connect with bus clock signal line SCLK, is used for The driving internal clock cable SCLK from control interface arrangement；

The input terminal of the bus data SDAT bi-directional drive submodule (130) is connect with data signal bus line SDAT, is used for Input or the output state of data signal bus line SDAT are selected, so that bus data is respectively placed in high resistant input or output shape State.

3. radio frequency front-end devices according to claim 2 from control interface arrangement, which is characterized in that the double mode reset submodule Block (110) includes power on detection circuit, VIO signal condition change detection circuit, the first inverter circuit (111), the second reverse phase Device circuit (112), biconditional gate circuit (113) and the first AND gate circuit (114)；

The power on detection circuit includes field-effect tube M1, resistance R1 and capacitor C1, the source electrode and power supply of the field-effect tube M1 Connection, grid and draining are connected, and respectively with one end of resistance R1, one end of capacitor C1, the first inverter circuit (111) The connection of second input terminal of input terminal and biconditional gate circuit (113), the other end of the resistance R1 connects to power supply, described The other end of capacitor C1 is connected to ground；

The output end of first inverter circuit (111) is connect with the input terminal of the second inverter circuit (112), and described second The output end of inverter circuit (112) is connect with the first input end of biconditional gate circuit (113), the biconditional gate circuit (113) output end is connect with the first input end of the first AND gate circuit (114)；

The VIO signal condition change detection circuit includes resistance R2, resistance R3, resistance R4, capacitor C2, transistor Q1 and sluggishness Comparator (115), one end of the resistance R2 and one end of resistance R3 are connected to the defeated of the double mode reset submodule (110) Enter end, the other end of the resistance R2 respectively with the collector of transistor Q1, the base stage of transistor Q1 and hysteresis comparator (115) first input end connection, the emitter of the transistor Q1 is connected to ground, the other end of the resistance R3 respectively with electricity Hinder the second input terminal connection of one end of R4, one end of capacitor C2 and hysteresis comparator (115), the other end of the resistance R4 It is connected to ground with the other end of capacitor C2, the of the output end of the hysteresis comparator (115) and the first AND gate circuit (114) The connection of two input terminals, output of the output end of first AND gate circuit (114) as the double mode reset submodule (110) End.

4. radio frequency front-end devices according to claim 2 from control interface arrangement, which is characterized in that the data decoder module It (200) include state machine submodule (210), SSC detection sub-module (220) and data output sub-module (230)；

The state machine submodule (210) is used to control the state of data decoder module (200), the control data decoder module (200) state include RST interface default conditions, ADD1 command frame data accumulation storage state, ACK1 command frame responsive state, ADD2 data frame adds up, and storage state, ACK2 data frame responsive state, ACK3 data frame respond the state that jumps, ACK4 read operation is rung State, ACK5 read operation is answered to terminate responsive state and NUL redundant operation state；

The output with bus clock SCLK input driven submodule (120) respectively of the input terminal of the SSC detection sub-module (220) The output end of end and bus data SDAT bi-directional drive submodule (130) connection, for detecting RFFE data signal bus Homing sequence；

The input terminal of the data output sub-module (230) output end and bus with double mode reset submodule (110) respectively Clock sclk inputs the output end connection of driven submodule (120), for being in ACK4 read operation in data decoder module (200) The data that RFFE bus to be read are output to one by one on data signal bus line SDAT from a high position to low level under responsive state.

5. radio frequency front-end devices according to claim 4 are from control interface arrangement, which is characterized in that the SSC detects submodule Block (220) includes d type flip flop D1, d type flip flop D2 and the second AND gate circuit (221), the Clk pin and D of the d type flip flop D1 The Clk pin of trigger D2 is connect with the output end of bus data SDAT bi-directional drive submodule (130), the d type flip flop The ENA pin of D1 and the ENA pin of d type flip flop D2 are connect with MARK signal, the D pin and d type flip flop of the d type flip flop D1 The D pin of D2 is connect with the output end of bus clock SCLK input driven submodule (120), the Q pin of the d type flip flop D1 It is connect with the second input terminal of the second AND gate circuit (221), the Q pin of the d type flip flop D2 and the second AND gate circuit (221) First input end connection, output end of the output end of second AND gate circuit (221) as SSC detection sub-module (220) are defeated SSCDETECT signal out.

6. radio frequency front-end devices according to claim 4 are from control interface arrangement, which is characterized in that the data export submodule Block (230) includes multiple selector S1~S6, d type flip flop D3~D5, the first multi input OR circuit (231), decoder (232) And the second multi input OR circuit (233)；The first input end of the multiple selector S1~S4 connects to power supply, and point It is not connect with the first input end of the input terminal of decoder (232), the Q pin of d type flip flop D3 and multiple selector S6, it is described The second input terminal of multiple selector S1~S4 is connected to ground, and respectively with the input terminal of decoder (232), d type flip flop D3 Q pin and multiple selector S6 first input end connection, the output end of the multiple selector S1~S4 with D trigger The D pin of device D3 connects, each input with the first multi input OR circuit (231) respectively of the output end of the decoder (232) The connection of the first input end of end and multiple selector S5, the output end of the multiple selector S5 and the D pin of d type flip flop D4 Connection, the output end of the multiple selector S6 are connect with the D pin of d type flip flop D5, and the Clk of the d type flip flop D3~D5 draws Foot is connect with the output end of bus clock SCLK input driven submodule (120), and the Reset of the d type flip flop D3~D5 draws Foot is connect with the output end of double mode reset submodule (110), and the of the Q pin of the d type flip flop D4 and multiple selector S5 The connection of two input terminals, and READFIN signal is exported, what the Q pin of the d type flip flop D5 was inputted with SCLK rising edge clock respectively Each input terminal of eight bit data signal, the second input terminal of multiple selector S6 and the second multi input OR circuit (233) and Output end connection, and export SDATOUT signal.

7. radio frequency front-end devices according to claim 2 from control interface arrangement, which is characterized in that the configurable register Module (300) includes multiple selector S7~S10 and d type flip flop D7~D42, the Clk pin of the d type flip flop D7~D42 It is connect with from the internal clock cable SCLK of control interface arrangement, the Reset pin of the d type flip flop D7~D42 is believed with RSEN Number connection, the D pin of the d type flip flop D7~D38 are corresponded with from the output end of 32 registers inside control interface arrangement Connection, the D pin of the d type flip flop D7~D38 is connect with the second input terminal of multiple selector S7~S10 respectively, described The first input end of multiple selector S7~S10 is connect with from the output end of mask register inside control interface arrangement, described The output end of multiple selector S7~S10 and the D pin of d type flip flop D39~D42 connect one to one, the d type flip flop D39 The Q pin of~D42 is connect as the output end from control interface arrangement with radio frequency front-end devices.