CN103308846A - Method and device for detecting functional performance of integrated chip based on model identification - Google Patents
Method and device for detecting functional performance of integrated chip based on model identification Download PDFInfo
- Publication number
- CN103308846A CN103308846A CN2013101644425A CN201310164442A CN103308846A CN 103308846 A CN103308846 A CN 103308846A CN 2013101644425 A CN2013101644425 A CN 2013101644425A CN 201310164442 A CN201310164442 A CN 201310164442A CN 103308846 A CN103308846 A CN 103308846A
- Authority
- CN
- China
- Prior art keywords
- chip
- model
- unit
- pin
- file
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
The invention relates to a method for detecting the functional performance of an integrated chip based on model identification. The method comprises the following steps of 1, reading an IBIS (Input/Output Buffer Information Specification) model file through a main control platform, analyzing the model of the chip and the I/O characteristic curve of a first input pin through a model resolving unit, translating the characteristic curve into a parameter value which can be tested, transmitting to a parameter receiving/transmitting unit through a command, sending the command to a signal simulating and detecting device, making a microprocessor of the signal simulating and detecting device generate a simulation voltage or a logical level according to a control signal source, and transmitting to the input pin of a chip to be detected via a pin driving and protecting circuit of the chip to be detected; and 2, starting a high-speed ADC (Analog-Digital Converter), reading and recording the parameter value of the output pin end of the chip to be detected in real time, starting the parameter receiving/transmitting unit for receiving current group output information, and saving. According to the method and the device, an IBIS model is taken as the testing basis of the integrated chip, so that a special SCPI (Standard Command for Programming Instrument) file is not required to be acquired. The functional and performance testing of any chip can be realized.
Description
Technical field
The present invention relates to a kind of detection technique, relate to a kind of method of carrying out the actual physical detection according to simulation and the IBIS model of digital integrated chip.
Background technology
In scientific research and production run, need discriminating that whether various devices are damaged and the screening of performance quality.Be starved of chip detecting system for this reason and finish this work.Existing chip detection system and method have two kinds, a kind of is that integrated chip at the specific function of producing carries out Function detection, be 200610139145.5 described chip test system and chip detecting methods as the patent No., the patent No. is the described chip test system of 200710002298.X and method of testing, and the patent No. is described chip detecting method, Apparatus and system based on script control of 201010153051.X; Another kind is to be that core is equipped with the related expanding parts in conjunction with the man-machine interaction realization chip detection of host computer with the single-chip microcomputer.The former does detection at the integrated chip product of producing, only to certain functional chip test, chip kind that relate to is considerably less though test is comprehensive, even the chip detecting method based on script control, its script is programmable instrument standard commands SCPI, obtaining and non-open type of this script is unsuitable for the real-time detection of many devices; The latter is that core can detect more integrated chip with the single-chip microcomputer, but along with the increasing of detection chip quantity, excitation algorithm and the size of code of the chip testing that needs sharply increase, and cause the Single Chip Microcomputer (SCM) system resource to be difficult to hold at last.
IBIS(Input/Output Buffer Information Specification) model is a kind of method to I/O BUFFER modeling quick and precisely based on the I/V curve, be reflection chip drives and a kind of international standard that receives electrical specification, provide a kind of standard file format to record as parameters such as drive source output impedance, rising/fall time and input loads.Each analog device or digital integrated chip have IBIS model separately.
Goal of the invention
For solving the defective of said method, the present invention proposes a kind of integrated chip functional performance detection method based on Model Identification and survey method and system, make chip detecting system have more universality and extensibility, realize the functional test of integrated chip, good and bad differentiation and performance screening.
Technical scheme
The invention provides a kind of integrated chip functional performance detection method survey method based on Model Identification, comprise the steps: step 1: read the IBIS model file by the master control platform, and by the model resolution unit, analyze the model of chip, and analyze the I/O characteristic curve of first input pin, and characteristic curve translated into testable magnitude of voltage and current value, this magnitude of voltage and current value send to parameter reception/transmitting element by instruction, again this instruction is handed down to signal imitation and pick-up unit, the microprocessor of signal imitation and pick-up unit produces aanalogvoltage according to fill order control signal source or logic level drives with holding circuit to chip input pin to be measured through chip pin to be measured; Step 2: open high-speed ADC, read magnitude of voltage or the current value of chip under test output pin end in real time and be recorded in storage unit, the data of this storage unit are as the real output value of chip, and start-up parameter reception/transmitting element receives current group of output information of detection chip and preserves; Step 3: after finishing, get back to step 1, start the input and output pin instruction of next group signal, repeat to finishing whole instructions.
Beneficial effect
Use the IBIS model as the foundation of integrated chip test, no longer need studying carefully concrete integrated chip handbook.
Do not need oneself to write specific exciting test file, can directly resolve the IBIS model according to device, conversion generates executable control statement and is handed down to signal imitation and pick-up unit, no longer needs to obtain special-purpose SCPI file.Can realize function and performance test to arbitrary chip, the detection chip kind can add the IBIS model according to user's request and expand arbitrarily.
Description of drawings
Fig. 1 chip detecting system overall construction drawing;
Fig. 2 chip detecting system master control platform structure figure;
Fig. 3 chip detecting system master control platform process figure;
Fig. 4 signal imitation and pick-up unit structural drawing;
Fig. 5 signal imitation and pick-up unit flowchart.
Embodiment
The invention provides a kind of system and method that the integrated chip functional performance detects that carries out, is a kind of chip detecting system and detection method with universality and extensibility.
A kind of system that carries out the detection of integrated chip functional performance comprises master control platform, signal imitation and pick-up unit, chip to be measured, as Fig. 1, the master control platform is connected by the USB line with pick-up unit with signal imitation, usb interface module is in signal imitation and pick-up unit, and chip to be measured is installed in the system by the socket on signal imitation and the pick-up unit.
Chip detecting system master control platform structure such as Fig. 2 comprise that IBIS model reading unit, model resolution unit, instruction generation unit, parameter reception/transmitting element, parameter comparing unit, visualization result unit and user expand gateway unit.
Various chips to be measured have the IBIS model file of oneself, can obtain from the website of each chip manufacturer.Pin model in the IBIS model file and ramp rate, rising and falling waveform in the data model are the main foundations of carrying out chip detection.The IBIS model of the document reader spare of IBIS model reading unit by expanding entrance input from the user.
The model resolution unit is extracted pin function statement and ramp rate, rising and the falling waveform statement in the IBIS model, and wherein chip output pin feature, ramp rate, rising and falling waveform data are preserved as normative document.
The input pin sequence number that the instruction generation unit provides according to the model resolution unit and signal value generate executable instruction and preserve as execute file.
Parameter reception/transmitting element is the unit that uses when concrete chip is done actual detected, frequency of utilization is the highest, parameter reception/transmitting element takes out the execute file corresponding with chip to be measured, give signal imitation and pick-up unit with the perform statement of one group of input pin by USB port, parameter reception/transmitting element receives data result and the preservation that the output pin corresponding with this group input pin obtains.Transmit next group pin instruction after finishing, until all finishing.
The parameter comparing unit obtains data result file and the normative document of chip output and carries out the contrast of function and waveform character, when only chip functions being done detection, and the terminal numerical value of the destination file that can read-onlyly fetch data.
The visualization result unit shows the comparative result of parameter comparing unit at the interface of man-machine interaction.
The master control platform is reserved the user and is expanded entrance, and for the chip type that is not included in the detection system, after the user provided the IBIS model file, the master control platform was resolved and generated control statement and detects.
Do not comprise the execute file that detects at any chip when this chip test system is initial.IBIS model reading unit, model resolution unit, instruction generation unit are to carry out the preceding module that generates the detection system execute file of chip detection, must expand the execute file that gateway unit guiding operation generates chip to be measured by the user when detecting certain chip first, do not restart work when detecting the type chip again, detected by parameter reception/transmitting element, parameter comparing unit, visualization result unit.Along with the continuous use of this chip detecting system, the chip that detects increases, internal system at the execute file of each chip detection also increasing, become a system that is constantly expanded according to user's operating position.
The workflow of master control platform as shown in Figure 3.
Step 1: by the chip model of master control platform according to user's input, the IBIS model file of article one record in the removal search software library, and read the model file the inside about the description for the chip model, the situation of coupling, give detection system.
Step 2: judge whether chip to be measured is included in the detection system.When detection system is initial inside do not comprise any chip to be measured and with it corresponding for detection of execute file, execution in step 3; If carried out similar chip testing, then internal system comprises the execute file of this chip, enters step 4.
Step 3: read new IBIS model file, resolve the IBIS model file, extract wherein pin model and performance parameter, form normative document and carry out son file;
Step 4: execute file sends to parameter reception/transmitting element by instruction, and the parameter reception/transmitting element of master control platform issues the execute file corresponding with this chip by USB port, and parameter reception/transmitting element generates test instruction.Namely resolve element analysis by model and go out the model of chip, and analyze the I/O characteristic curve of an input pin, and characteristic curve is translated into testable magnitude of voltage and current value, this magnitude of voltage and current value send to parameter reception/transmitting element by instruction; This instruction is handed down to signal imitation and pick-up unit.Read the I/O characteristic curve of next input pin after finishing, and characteristic curve is translated into testable magnitude of voltage and current value, this magnitude of voltage and current value send to parameter reception/transmitting element by instruction; This instruction is handed down to signal imitation and pick-up unit.
Step 5: the parameter reception/transmitting element of master control platform starts receiving function and receives current group of output information of detection chip and preserve, and the input end that starts next group signal finishing after instructs, set by step 4, step 5 repeats to finishing whole instructions.Parameter reception/transmitting element also can be restarted receiving function after all instructions execute, finish the information that the master control platform receives detection chip output.
Step 6: the master control platform starts the model resolution unit again, the parameter comparing unit reads model and resolve magnitude of voltage and the current value that chip that element analysis goes out should have under perfect condition, the detection chip output pin message file of preserving in the read step 5 contrasts difference on both waveforms, is figure, output result.
Signal imitation and pick-up unit structure are as shown in Figure 4.Comprise that master control platform interface, microprocessor, storage unit, signal source, ADC and chip pin to be measured drive and holding circuit.
The running of each unit on the execution command control device that signal imitation and pick-up unit reception master control platform are sent.
Execution command enters microprocessor and storage unit by the master control platform interface.
Microprocessor is according to exectorial control signal source and the ADC of requiring.
Signal source comprises programmable amplifier and direct supply, the logic level that needs when each voltage that needs during for generation of the detection analog chip and detection digit chip.
Analog to digital converter in the device is High Speed High Precision ADC, with the rise and fall that detect chip output waveform to be measured along the time, test chip is carried out continuous leg signal to be obtained and forms wave file and be stored in storage unit, the end product of wave file and ADC conversion is uploaded through the master control platform interface by parameter reception/transmitting element.
Wherein, during chip testing, obtain the input signal that will add by the IBIS model again, this pumping signal drives through actual level, is added to the input pin of chip, and when input constantly changed, the signal of the output pin of chip also can constantly change.Wave file refers to the output pin by ADC continuous acquisition chip, the output signal that collects can obtain a series of data, if this series data is represented with figure, it is exactly a wave file, if ADC is only when the maximal value of input stimulus and minimum value, the sampling output pin is exactly a spot of ADC transformation result.Sometimes, to the chip fast detecting, only test maximal value and minimum value also is fine.Wave file is used for Performance Detection, and the end product of ADC conversion is used for Function detection.
In chip pin driving to be measured and the holding circuit chip carrier socket is arranged, chip to be measured can be installed on this socket.
Signal imitation and pick-up unit are carried out flow process as shown in Figure 5.
Step 1: receive fill order by the master control platform interface, microprocessor produces aanalogvoltage according to fill order control signal source or logic level drives with holding circuit to chip input pin to be measured through chip pin to be measured;
Step 2: open high-speed ADC, read the magnitude of voltage of chip under test output pin end in real time and be recorded in storage unit;
Step 3: require to continue to test respectively to organize the output signal in the pin and record the result successively to be kept at storage unit according to exectorial sequential or logic;
Step 4: read waveform result and the final ADC transformation result of acquisition from storage unit, be uploaded to the master control platform.
Claims (10)
1. the integrated chip functional performance detection method survey method based on Model Identification is characterized in that: comprise the steps:
Step 1: the IBIS model reading unit by the master control platform reads the IBIS model file, and resolve element analysis by model and go out the model of chip and the I/O characteristic curve of first input pin, and characteristic curve translated into testable magnitude of voltage and current value, this magnitude of voltage and current value send to parameter reception/transmitting element by instruction, again this instruction is handed down to signal imitation and pick-up unit, the microprocessor of signal imitation and pick-up unit produces aanalogvoltage according to fill order control signal source or logic level drives with holding circuit to chip input pin to be measured through chip pin to be measured;
Step 2: open high-speed ADC, read magnitude of voltage or the current value of chip under test output pin end in real time and be recorded in storage unit, the data of this storage unit are as the real output value of chip;
Step 3: return step 1, read the I/O characteristic curve of next input pin, repeat to finishing whole instructions.
2. a kind of integrated chip functional performance detection method based on Model Identification according to claim 1, it is characterized in that: described step 2 also comprises: start-up parameter reception/transmitting element receives current group of output information of detection chip and preserves.
3. a kind of integrated chip functional performance detection method survey method based on Model Identification according to claim 1 and 2, it is characterized in that: described step 2 comprises the steps: that also the master control platform starts the model resolution unit again, the parameter comparing unit reads model and resolve magnitude of voltage and the current value that chip that element analysis goes out should have under perfect condition, and and actual rreturn value compare, contrast ideal value and the difference of actual value on waveform and function of first group of input and output pin, finish the test of one group of input and output.
4. a kind of integrated chip functional performance detection method survey method based on Model Identification according to claim 1 and 2 is characterized in that:
Before described step 1, also comprise judging whether chip to be measured is included in the step in the detection system: be included in the detection system if judge chip to be measured, then enter step 1;
If judging chip to be measured is not included in the detection system, read new IBIS model file, the model resolution unit is extracted pin function statement and the waveform statement in the IBIS model, and wherein chip output pin feature, Wave data are preserved as normative document; The input pin sequence number that the instruction generation unit provides according to the model resolution unit and signal value generate executable instruction and preserve as execute file; Change step 1 over to.
5. a kind of integrated chip functional performance detection method survey method based on Model Identification according to claim 1 and 2 is characterized in that: when only chip functions being detected, the terminal numerical value of the read-only destination file that fetches data compares.
6. a kind of integrated chip functional performance detection method survey method based on Model Identification according to claim 2, it is characterized in that: described master control platform also comprises the visualization result unit, and it shows the comparative result of parameter comparing unit at the interface of man-machine interaction.
7. a kind of integrated chip functional performance detection method survey method based on Model Identification according to claim 4, it is characterized in that: comprise that also the user expands gateway unit, IBIS model reading unit is by expanding the document reader spare IBIS model file of gateway unit input from the user.
8. a kind of integrated chip functional performance detection method based on Model Identification according to claim 4, it is characterized in that: the waveform statement in the described step 4 comprises ramp rate, rising and falling waveform statement.
9. device of surveying based on the integrated chip functional performance detection method of Model Identification: comprise master control platform, signal imitation and pick-up unit, it is characterized in that: described master control platform comprises that IBIS model reading unit, model resolution unit, instruction generation unit, parameter reception/transmitting element, parameter comparing unit and user expand gateway unit
The IBIS model file of the document reader spare of IBIS model reading unit by expanding gateway unit input from the user;
The model resolution unit is extracted pin function statement and the waveform statement in the IBIS model, and wherein chip output pin feature and Wave data are preserved as normative document; Model is resolved element analysis and is gone out the model of chip, and analyzes the I/O characteristic curve of an input pin, and characteristic curve is translated into testable magnitude of voltage and current value, and this magnitude of voltage and current value send to parameter reception/transmitting element by instruction; Read the I/O characteristic curve of next input pin after finishing, and characteristic curve is translated into testable magnitude of voltage and current value, this magnitude of voltage and current value send to parameter reception/transmitting element by instruction;
The input pin sequence number that the instruction generation unit provides according to the model resolution unit and signal value generate executable instruction and preserve as execute file;
Parameter reception/transmitting element takes out the execute file corresponding with chip to be measured, generate execution command, the perform statement of one group of input pin is sent to signal imitation and pick-up unit, the start-up parameter receiving function, receive data result and preservation that the output pin corresponding with this group input pin obtains, transmitting the perform statement of next group input pin after finishing sends to signal imitation and pick-up unit, the start-up parameter receiving function, receive data result and preservation that the output pin corresponding with this group input pin obtains, until all finishing;
The parameter comparing unit obtains data result file and the normative document of chip output and carries out the contrast of function and waveform character;
The running of each unit comprises that master control platform interface, microprocessor, storage unit, signal source, analog to digital converter and chip pin to be measured drive and holding circuit on the execution command control device that described signal imitation and pick-up unit reception master control platform are sent;
Execution command enters microprocessor and storage unit by the master control platform interface;
Microprocessor requires control signal source and analog to digital converter according to instruction;
Signal source comprises programmable amplifier and direct supply, the logic level that needs when each voltage that needs during for generation of the detection analog chip and detection digit chip;
Analog to digital converter is High Speed High Precision ADC, to detect the Wave data of chip output to be measured, test chip is carried out continuous leg signal to be obtained and forms wave file and be stored in storage unit, the data of this storage unit are as the real output value of chip, return to the master control platform by parameter reception/transmitting element, the end product of ADC conversion is uploaded through the master control platform interface; Wave file is used for Performance Detection, and the end product of ADC conversion is used for Function detection;
In chip pin driving to be measured and the holding circuit chip carrier socket is arranged, chip to be measured can be installed on this socket.
10. the device surveyed of a kind of integrated chip functional performance detection method based on Model Identification according to claim 8, it is characterized in that: described waveform statement comprises ramp rate, rising and falling waveform statement.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310164442.5A CN103308846B (en) | 2013-05-07 | 2013-05-07 | Method and device for detecting functional performance of integrated chip based on model identification |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310164442.5A CN103308846B (en) | 2013-05-07 | 2013-05-07 | Method and device for detecting functional performance of integrated chip based on model identification |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103308846A true CN103308846A (en) | 2013-09-18 |
| CN103308846B CN103308846B (en) | 2015-07-08 |
Family
ID=49134274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310164442.5A Expired - Fee Related CN103308846B (en) | 2013-05-07 | 2013-05-07 | Method and device for detecting functional performance of integrated chip based on model identification |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103308846B (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106970312A (en) * | 2016-01-14 | 2017-07-21 | 北京君正集成电路股份有限公司 | A kind of chip detecting method and device |
| CN107741893A (en) * | 2017-09-29 | 2018-02-27 | 北京航天福道高技术股份有限公司 | A kind of command communication simulation system and method |
| CN109298307A (en) * | 2018-09-26 | 2019-02-01 | 广西桂芯半导体科技有限公司 | Semiconductor packages detection system |
| CN111103527A (en) * | 2019-12-31 | 2020-05-05 | 西安翔腾微电子科技有限公司 | Anti-lightning stroke detection method for chip port |
| CN111191409A (en) * | 2018-10-25 | 2020-05-22 | 浙江宇视科技有限公司 | Chip internal silicon chip pin signal simulation method and device |
| CN113552473A (en) * | 2021-09-22 | 2021-10-26 | 北京紫光青藤微系统有限公司 | System for chip test and chip device to be tested |
| CN113568821A (en) * | 2021-07-26 | 2021-10-29 | 北京百度网讯科技有限公司 | Method, device, equipment and medium for testing computation performance of AI chip |
| CN114371993A (en) * | 2021-12-10 | 2022-04-19 | 北京镁伽科技有限公司 | Software debugging method and device based on SCPI instruction, electronic equipment and storage medium |
| CN114441922A (en) * | 2022-04-02 | 2022-05-06 | 深圳市赛元微电子有限公司 | Semiconductor device testing device |
| TWI769484B (en) * | 2020-07-13 | 2022-07-01 | 鴻海精密工業股份有限公司 | Method of displaying connection status of pins of chip, computer device and storage medium |
| CN117031256A (en) * | 2023-10-07 | 2023-11-10 | 紫光同芯微电子有限公司 | Chip testing system and method |
| CN113568821B (en) * | 2021-07-26 | 2024-10-29 | 昆仑芯(北京)科技有限公司 | AI chip calculation performance test method, device, equipment and medium |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1808445A (en) * | 2005-01-21 | 2006-07-26 | 华为技术有限公司 | IBIS model information reading method, high-speed circuit emulation system and its method |
| US20060224374A1 (en) * | 2005-03-31 | 2006-10-05 | Won Ok Kwon | Method for converting IBIS model to spice behavioral model by extracting resistor and capacitor |
| CN1928576A (en) * | 2006-10-13 | 2007-03-14 | 北京中星微电子有限公司 | Chip testing system and method |
| US20070185699A1 (en) * | 2006-02-08 | 2007-08-09 | Fujitsu Limited | IBIS correction tool, IBIS correction method, and waveform simulation device |
| CN101587167A (en) * | 2009-07-08 | 2009-11-25 | 天津渤海易安泰电子半导体测试有限公司 | Multi-functional integrated circuit chip testing machine |
| US7783946B2 (en) * | 2007-11-14 | 2010-08-24 | Oracle America, Inc. | Scan based computation of a signature concurrently with functional operation |
| CN201773169U (en) * | 2010-06-23 | 2011-03-23 | 天津渤海易安泰电子半导体测试有限公司 | Testing system for integrated circuit chip |
| CN102314532A (en) * | 2010-07-02 | 2012-01-11 | 中兴通讯股份有限公司 | IBIS (Input/Output Buffer Information Specification) model verification method and system |
-
2013
- 2013-05-07 CN CN201310164442.5A patent/CN103308846B/en not_active Expired - Fee Related
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1808445A (en) * | 2005-01-21 | 2006-07-26 | 华为技术有限公司 | IBIS model information reading method, high-speed circuit emulation system and its method |
| US20060224374A1 (en) * | 2005-03-31 | 2006-10-05 | Won Ok Kwon | Method for converting IBIS model to spice behavioral model by extracting resistor and capacitor |
| US20070185699A1 (en) * | 2006-02-08 | 2007-08-09 | Fujitsu Limited | IBIS correction tool, IBIS correction method, and waveform simulation device |
| CN1928576A (en) * | 2006-10-13 | 2007-03-14 | 北京中星微电子有限公司 | Chip testing system and method |
| US7783946B2 (en) * | 2007-11-14 | 2010-08-24 | Oracle America, Inc. | Scan based computation of a signature concurrently with functional operation |
| CN101587167A (en) * | 2009-07-08 | 2009-11-25 | 天津渤海易安泰电子半导体测试有限公司 | Multi-functional integrated circuit chip testing machine |
| CN201773169U (en) * | 2010-06-23 | 2011-03-23 | 天津渤海易安泰电子半导体测试有限公司 | Testing system for integrated circuit chip |
| CN102314532A (en) * | 2010-07-02 | 2012-01-11 | 中兴通讯股份有限公司 | IBIS (Input/Output Buffer Information Specification) model verification method and system |
Non-Patent Citations (1)
| Title |
|---|
| 蔡兴建等: "基于IBIS模型的高速数字I/O缓冲器的瞬态行为建模", 《上海交通大学学报》, vol. 35, no. 01, 31 January 2001 (2001-01-31) * |
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106970312A (en) * | 2016-01-14 | 2017-07-21 | 北京君正集成电路股份有限公司 | A kind of chip detecting method and device |
| CN107741893A (en) * | 2017-09-29 | 2018-02-27 | 北京航天福道高技术股份有限公司 | A kind of command communication simulation system and method |
| CN109298307A (en) * | 2018-09-26 | 2019-02-01 | 广西桂芯半导体科技有限公司 | Semiconductor packages detection system |
| CN111191409A (en) * | 2018-10-25 | 2020-05-22 | 浙江宇视科技有限公司 | Chip internal silicon chip pin signal simulation method and device |
| CN111191409B (en) * | 2018-10-25 | 2023-08-18 | 浙江宇视科技有限公司 | Method and device for simulating chip internal silicon chip pin signals |
| CN111103527B (en) * | 2019-12-31 | 2022-05-10 | 西安翔腾微电子科技有限公司 | Anti-lightning-strike detection method for chip port |
| CN111103527A (en) * | 2019-12-31 | 2020-05-05 | 西安翔腾微电子科技有限公司 | Anti-lightning stroke detection method for chip port |
| TWI769484B (en) * | 2020-07-13 | 2022-07-01 | 鴻海精密工業股份有限公司 | Method of displaying connection status of pins of chip, computer device and storage medium |
| CN113568821A (en) * | 2021-07-26 | 2021-10-29 | 北京百度网讯科技有限公司 | Method, device, equipment and medium for testing computation performance of AI chip |
| US12072780B2 (en) | 2021-07-26 | 2024-08-27 | Kunlunxin Technology (Beijing) Company Limited | Method and apparatus for testing AI chip computing performance, and non-transitory computer-readable storage medium |
| CN113568821B (en) * | 2021-07-26 | 2024-10-29 | 昆仑芯(北京)科技有限公司 | AI chip calculation performance test method, device, equipment and medium |
| CN113552473B (en) * | 2021-09-22 | 2021-12-28 | 北京紫光青藤微系统有限公司 | System for chip test and chip device to be tested |
| CN113552473A (en) * | 2021-09-22 | 2021-10-26 | 北京紫光青藤微系统有限公司 | System for chip test and chip device to be tested |
| CN114371993A (en) * | 2021-12-10 | 2022-04-19 | 北京镁伽科技有限公司 | Software debugging method and device based on SCPI instruction, electronic equipment and storage medium |
| CN114441922A (en) * | 2022-04-02 | 2022-05-06 | 深圳市赛元微电子有限公司 | Semiconductor device testing device |
| CN114441922B (en) * | 2022-04-02 | 2022-06-14 | 深圳市赛元微电子有限公司 | Semiconductor device testing device |
| CN117031256A (en) * | 2023-10-07 | 2023-11-10 | 紫光同芯微电子有限公司 | Chip testing system and method |
| CN117031256B (en) * | 2023-10-07 | 2024-03-01 | 紫光同芯微电子有限公司 | Chip testing system and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103308846B (en) | 2015-07-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103308846B (en) | Method and device for detecting functional performance of integrated chip based on model identification | |
| CN102169846B (en) | Method for writing multi-dimensional variable password in parallel in process of testing integrated circuit wafer | |
| CN104408264B (en) | It is a kind of that system and method is verified based on the Embedded Storage Controller asserted | |
| CN102928772B (en) | Timing sequence test system and method for testing thereof | |
| CN109783340B (en) | SoC test code programming method, IP test method and device | |
| CN114662427B (en) | Debugging method and device for logic system design | |
| US8407522B2 (en) | Test apparatus and recording medium | |
| US20140058699A1 (en) | Information processing apparatus, test data generating apparatus, and test data generating method | |
| CN112526319B (en) | Chip testing method and device, processor chip and server | |
| CN106598834A (en) | UI (User Interface) testing method and device | |
| CN102565683B (en) | Generation and verification method of test vector | |
| CN105070321A (en) | Quick test circuit and method for memory device | |
| CN116486892A (en) | Memory function verification and data acquisition system, test method and electronic equipment | |
| CN107728045A (en) | FPGA method of testings based on Ultra Flex | |
| CN113704099A (en) | Test script generation method and equipment for spacecraft power system evaluation | |
| CN202404912U (en) | Neural network test module and test system of smart card chip memory | |
| CN115630594B (en) | Method and system for converting chip design simulation file into Pattern file | |
| US8341579B2 (en) | Method, apparatus, and system for analyzing operation of semiconductor integrated circuits | |
| CN102058430B (en) | Automatic test equipment (ATE) of multi-parameter monitor and test method thereof | |
| CN101814051A (en) | Computer testing system capable of combining testing items at will and method thereof | |
| JP2016164577A (en) | Apparatus for acquiring data of fast fail memory and method thereof | |
| CN103165405A (en) | Mutli-dimensional variable code real-time generation method through general purpose interface bus (GPIB) interface | |
| CN114121137B (en) | Nand Flash particle power consumption testing system and method | |
| US6434503B1 (en) | Automated creation of specific test programs from complex test programs | |
| CN105551527B (en) | Test circuit, test method and the device of CAM |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20130918 Assignee: Jiangsu Nanyou IOT Technology Park Ltd. Assignor: Nanjing Post & Telecommunication Univ. Contract record no.: 2016320000210 Denomination of invention: Method and device for detecting functional performance of integrated chip based on model identification Granted publication date: 20150708 License type: Common License Record date: 20161114 |
|
| LICC | Enforcement, change and cancellation of record of contracts on the licence for exploitation of a patent or utility model | ||
| EC01 | Cancellation of recordation of patent licensing contract | ||
| EC01 | Cancellation of recordation of patent licensing contract |
Assignee: Jiangsu Nanyou IOT Technology Park Ltd. Assignor: Nanjing Post & Telecommunication Univ. Contract record no.: 2016320000210 Date of cancellation: 20180116 |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150708 Termination date: 20180507 |