CN111191409A - Chip internal silicon chip pin signal simulation method and device - Google Patents
Chip internal silicon chip pin signal simulation method and device Download PDFInfo
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- CN111191409A CN111191409A CN201811251656.5A CN201811251656A CN111191409A CN 111191409 A CN111191409 A CN 111191409A CN 201811251656 A CN201811251656 A CN 201811251656A CN 111191409 A CN111191409 A CN 111191409A
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Abstract
The invention discloses a method and a device for simulating a pin signal of an internal silicon chip, which are used for acquiring data of a TDR impedance curve of an internal circuit of the chip; obtaining an equivalent circuit model of the chip internal circuit according to the data of the TDR impedance curve; acquiring data of a test signal required to be applied to an external pin of the chip; and calculating simulation waveform data of the test signal conducted to the chip internal silicon chip pin through the chip internal circuit according to the equivalent circuit model and the data of the test signal. The method provides a method for simulating the signal transmitted to the pin of the silicon chip in the chip by the test signal through the signal test system under the condition that the detailed packaging information in the chip can not be obtained, and further judging whether the signal quality meets the design requirement or not. The method well solves the technical difficulty that the pin signal of the silicon chip in the chip can not be directly measured, and has great popularization value.
Description
Technical Field
The present invention relates to the field of signal processing, and in particular, to a method and an apparatus for simulating a pin signal of an internal silicon chip of a chip.
Background
In circuit design, it is often necessary to determine whether a designed circuit is actually acceptable according to the quality of signals obtained from chip pins. As shown in fig. 1, there is a section of chip internal circuit package between the chip internal silicon chip 300 pin and the chip external pin 303 for actually processing signals. Some chip-packaged chip internal circuits 301 are very long, some chip-packaged chip internal circuits are even more than 1 inch, and when a signal is transmitted from a chip external pin 303 to a pin of a chip internal silicon chip 300 through the chip internal circuit 301, an inductance, a capacitance or a resistance on the internal circuit of the segment may have a certain influence on a signal transmission process, so that a measured signal on the chip external pin 303 on the PCB substrate 302 cannot truly reflect the signal quality on the chip internal pin. Thereby causing certain difficulties in the design of the circuit. In order to simulate the signals received by the internal silicon pins of the chip, the prior art IBIS (Input/Output Buffer Information Specification) adopts the I/V and V/t table form to describe the characteristics of the I/O unit and the pins of the digital integrated circuit. However, when the IBIS model is used for simulating the signal quality of the chip, the correctness of the signal in the chip cannot be inferred from the simulation result when the chip packaging information cannot be obtained.
Disclosure of Invention
In order to overcome the above disadvantages in the prior art, an object of the present application is to provide a method for simulating a pin signal of an internal silicon chip, which is applied to a signal testing system, wherein the internal silicon chip pin of a chip is connected to an external pin of the chip through an internal circuit of the chip, and the method includes:
acquiring data of a TDR impedance curve of the chip internal circuit;
obtaining an equivalent circuit model of the chip internal circuit according to the data of the TDR impedance curve;
acquiring data of a test signal required to be applied to an external pin of the chip;
and calculating simulation waveform data of the test signal conducted to the chip internal silicon chip pin through the chip internal circuit according to the equivalent circuit model and the data of the test signal.
Optionally, the signal testing system comprises a TDR testing instrument; the step of obtaining the data of the TDR impedance curve of the chip internal circuit comprises the following steps:
sending a test signal to the chip external pin through the TDR test instrument;
and receiving a reflected signal generated by the test signal through the chip internal circuit from the chip external pin through the TDR test instrument, and obtaining data of a TDR impedance curve of the chip internal circuit according to the reflected signal.
Optionally, the step of obtaining, according to the equivalent circuit model and the data of the test signal, simulation waveform data of the test signal conducted to the chip internal silicon chip pin through the chip internal circuit by calculation includes:
acquiring simulation precision preset by a signal testing system, wherein the simulation precision is used for representing time precision when the signal testing system simulates;
acquiring a transmission delay parameter of an equivalent circuit model in the chip;
and calculating simulation waveform data of the test signal transmitted to the chip internal silicon chip pin through the chip internal circuit according to the equivalent circuit model of the chip internal circuit, the waveform data of the test signal, the preset simulation precision and the transmission delay parameter.
Optionally, the step of obtaining the transmission delay parameter of the equivalent circuit model inside the chip includes:
and calculating the transmission delay parameter of the equivalent circuit model according to the data of the TDR impedance curve.
Optionally, the step of calculating, according to the equivalent circuit model of the chip internal circuit, the waveform data of the test signal, the preset simulation precision, and the transmission delay parameter, simulation waveform data of the test signal transmitted to the chip internal silicon chip pin through the chip internal circuit includes:
obtaining a plurality of nodes of the equivalent circuit model according to the equivalent circuit model of the chip internal circuit, wherein the nodes represent positions of reflected waves generated when signals in the equivalent circuit model are conducted along the equivalent circuit model;
acquiring the time of the test signal and the time of the reflected wave to each node according to the change relation of the data of the impedance curve along with the time;
and sequentially calculating simulation waveform data generated when the test signal passes through each node according to the time for the test signal to be conducted to each node.
Optionally, the step of sequentially calculating the simulated waveform data of the nodes through which the test signal passes according to the time for the test signal to be conducted to each node includes:
taking the node to which the test signal is conducted as a target node according to the time for the test signal to be conducted to each node;
calculating simulation waveform data and reflected waves of the target node under the action of the test signal;
judging whether the reflected wave of the last node along the conduction direction of the test signal is conducted to the target node;
and if the reflected wave of the last node is conducted to the target node, superposing the conducted reflected wave and the simulation waveform of the target node under the action of the test signal.
If the reflected wave of the last node is not transferred to the target node, calculating the simulation waveform data and the reflected wave of the next node of the target node along the test signal transfer direction according to the time when the test signal is transferred to each node.
Optionally, the signal testing system includes a signal testing apparatus, the test signal is sent by a signal generating chip, and the step of acquiring data of the test signal to be applied to the external pin of the chip includes:
sending a preset test signal through the signal generating chip;
conducting the test signal into the signal testing instrument through a test probe;
and acquiring the test signal in real time through the signal test instrument to obtain waveform data of the test signal.
Optionally, the signal testing system comprises a signal receiving measuring tool, the signal receiving measuring tool comprises a circuit board, a testing chip area, a receiving end testing point, a ground plane bright copper area and a signal receiving chip, and the signal receiving measuring tool is used for simulating a real working environment of the signal receiving chip.
Optionally, the signal testing system comprises a signal generation measuring tool, and the signal generation measuring tool comprises a circuit board, a testing chip area, a sending end testing point, a power supply, a clock, a reset and debugging circuit, a ground plane bright copper area and a signal generation chip; the signal generation measurement tool is used for simulating the real working environment of the signal generation chip.
Another objective of the present application is to provide a device for simulating a pin signal of an internal silicon chip, where the device includes a TDR impedance curve obtaining module, a chip internal circuit equivalent model obtaining module, a test signal obtaining module, and a chip internal silicon chip pin simulation signal waveform calculating module;
the TDR impedance curve acquisition module is used for acquiring a TDR impedance curve of a chip internal circuit;
the chip internal circuit equivalent model obtaining module is used for obtaining a chip internal circuit equivalent model according to the TDR impedance curve data;
the test signal acquisition module is used for acquiring data of a test signal required to be applied to the external pin of the chip;
and the chip internal silicon chip pin simulation signal waveform calculation module is used for calculating simulation waveform data of the test signal transmitted to the chip internal silicon chip pin through the chip internal circuit according to the equivalent circuit model and the data of the test signal.
Compared with the prior art, the method has the following beneficial effects:
according to the chip internal silicon chip pin signal simulation method and device provided by the invention, under the condition that the detailed packaging information in the chip cannot be obtained, an equivalent circuit model of a chip internal circuit is obtained based on a TDR principle, a signal transmitted to the chip internal silicon chip pin by a test signal is simulated through a signal test system, and then whether the signal quality meets the design requirement or not is judged. The method well solves the technical difficulty that the pin signal of the silicon chip in the chip can not be directly measured, and has great popularization value.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic diagram of a chip internal silicon chip and a chip external pin connection circuit provided in an embodiment of the present application;
FIG. 2 is a schematic diagram of a chip internal silicon chip pin signal simulation procedure provided in an embodiment of the present application;
fig. 3 is a schematic view of a signal receiving chip measurement tool provided in the embodiment of the present application;
fig. 4 is a schematic view of a signal generating chip measurement tool provided in an embodiment of the present application.
Icon: 300-chip internal silicon chip; 301-chip internal circuitry; 302-a PCB substrate; 303-chip external pins; 601-a first circuit board; 602-a first ground plane bright copper area; 603-a receiving end test point; 604-target chip; 605-a first test chip region; 501-a second circuit board; 502-second ground plane bright copper area; 503-a transmitting end test point; 504-signal generating chip; 505-second test chip area.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present application, it is noted that the terms "first", "second", "third", and the like are used merely for distinguishing between descriptions and are not intended to indicate or imply relative importance.
In the description of the present application, it is further noted that, unless expressly stated or limited otherwise, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
Referring to fig. 2, fig. 2 is a flowchart illustrating a method for simulating a pin signal of an internal silicon chip 300 according to the present invention, which is applied to a signal testing system, and the steps included in the method will be described in detail below.
Step S100, obtaining the TDR impedance curve data of the chip internal circuit 301.
Specifically, in this embodiment, the signal testing system includes a TDR testing apparatus. For example, the TDR test instrument may be a network analysis meter.
Optionally, the network analysis and measurement instrument sends a test signal with a preset frequency to the chip internal silicon chip 300 through an external pin of the chip. In the process of transmitting the test signal to the pin of the chip internal silicon chip 300 through the chip internal circuit 301, a reflection signal is generated at the position where the impedance of the chip internal circuit 301 changes.
The network analysis and measurement instrument obtains the frequency response parameters of the chip internal circuit 301 to the test signals from the chip external pin 303.
In order to obtain the TDR impedance curve of the time domain, the signal testing system performs inverse fourier transform on the frequency response parameter to obtain the TDR impedance curve of the time domain of the chip internal circuit 301. In order to reduce the calculation time of the signal testing system for performing the inverse fourier transform, the inverse fourier transform calculation method in this embodiment is inverse fast fourier transform.
Optionally, as shown in fig. 3, when the TDR impedance curve of the chip internal circuit 301 is obtained by a TDR testing instrument, in order to obtain a TDR impedance curve inside the chip that is close to the TDR impedance curve in the real working environment of the chip, the target chip 604 is tested by a signal receiving chip measurement tool.
The signal receiving chip measuring tool comprises a first circuit board 601, a first test chip area 605, a receiving end test point 603 and a first ground plane bright copper area 602. The first circuit board 601 is used for assembling the target test chip, and test points are led out on the first circuit board 601. The first test chip area 605 is used for placing the target chip 604. The receiving end test point 603 is used for electrically connecting with a test probe of a TDR test instrument. The first bright copper area is used for grounding the network analyzer test probe.
Step S200, obtaining an equivalent circuit of the chip internal circuit 301 according to the data of the TDR impedance curve.
In this embodiment, the signal testing system obtains the equivalent circuit of the chip internal circuit 301 through calculation based on the TDR principle. Specifically, by sending a pulse or a step signal to the transmission conductor, when an impedance change occurs in the transmission path, part of energy will be reflected, and the rest of energy will continue to be transmitted, and a reflection coefficient ρ can be calculated by the amplitude of the step signal and the amplitude of the reflected signal, where the reflection coefficient ρ can be expressed as:
wherein Z is0Representing the impedance of the source of the test signal, Z representing the impedance of the node to be tested, VincidentRepresenting the amplitude, V, of the stepped-over signalreflectedRepresenting the amplitude of the reflected signal. Because of the amplitude V of the incident step signalincidentIs a known variable, so that only the amplitude V of the reflected step impulse is measuredreflectedThe transmission coefficient p can be calculated. And because of the output impedance Z of the TDR test instrument0As a known variable, the impedance Z of the node under test can be expressed as:
in step S300, data of a test signal to be applied to the chip external pin 303 is acquired.
Specifically, the signal test system comprises a signal measuring device and a signal generating chip, wherein the signal generating chip is used for generating a test signal. Alternatively, the signal testing device may be an oscilloscope, and a test probe of the oscilloscope detects the test signal sent by the signal generating chip 504. And the oscilloscope performs rapid sampling on the test signal so as to obtain waveform data of the test signal.
As shown in fig. 4, the test signal generating device is part of a signal generating measurement tool. The signal generation measurement tool is used for simulating the real working environment of a chip for sending signals. The signal generation test tool comprises a second circuit board 501, a second test chip area 505, a sending end test point 503, a power supply, a clock, a reset circuit, a debugging circuit and a second ground plane bright copper area 502.
The second circuit board 501 is used for assembling a signal generation test chip, a power supply, a clock and reset circuit, and a debugging interface circuit, and a signal sending test point is led out from the second circuit board 501. Wherein the second test chip area 505 is used for mounting the signal generating chip 504. The sending end test point 503 is used to facilitate the signal test instrument to perform signal test through the sending end test point 503. The second ground plane bright copper area 502 is used to facilitate grounding of the test probe of the signal testing apparatus.
The signal generation test chip is connected with a power supply, a clock, a reset circuit and a debugging interface on the second circuit board 501, and a minimum system is formed together. Wherein the power supply is used for providing power supply required by the operation for the signal generating chip 504. The clock circuit provides a clock driving signal for the signal generating chip 504, and the reset circuit is used for resetting the signal generating chip 504 when the signal generating chip fails in operation. The debug interface circuit is used for the signal test system to send a debug command to the signal generation chip 504 to control the signal generation chip 504.
Step S400, calculating, according to the equivalent circuit model and the data of the test signal, simulation waveform data of the test signal conducted to the pin of the chip internal silicon chip 300 through the chip internal circuit 301.
Specifically, the signal testing system obtains a simulation precision preset by the signal testing system, where the simulation precision is used to represent a time precision when a pin of the chip internal silicon chip 300 is simulated. And meanwhile, the signal test system obtains the equivalent circuit model signal transmission delay parameter through the change relation of the data of the TDR impedance curve along with time.
The signal testing system obtains the number of nodes in the equivalent circuit model according to the equivalent circuit model of the chip internal circuit 301. The node represents the location where the circuit impedance changes as the test signal is conducted along the equivalent circuit.
The signal testing system obtains the time for the test signal to be conducted to each node according to the time-varying relation of the TDR impedance curve data of the chip internal circuit 301. The signal testing system sequentially calculates simulation waveform data of the testing signal transmitted to each node according to the time of the testing signal transmitted to each node, so that simulation of the pin signal of the silicon chip 300 in the chip is realized.
The step of sequentially calculating the simulation waveform data of the test signal transmitted to each node according to the time of the test signal transmitted to each node, thereby realizing the simulation of the pin signal of the silicon chip 300 inside the chip comprises the following steps:
and the signal testing system takes the nodes to which the test signals are conducted as target nodes in sequence according to the time for the test signals to be conducted to each node.
And the signal test system calculates simulation waveform data of the target node under the action of the test signal.
The signal test system determines whether a reflected wave of a last node of the nodes is conducted to the target node along the test signal conducting direction.
If the reflected wave of the next node is conducted to a target node, the signal testing system superimposes the conducted reflected wave and the waveform of the target node on each other.
For example, when the test signal is transmitted to a certain node of the chip internal equivalent circuit model, a reflected wave in the test signal transmission direction and a reflected wave in the test transmission direction opposite to the test signal transmission direction are generated, and the reflected wave in the test signal transmission direction is defined as a forward reflected wave and the reflected wave in the test transmission direction opposite to the test signal transmission direction is defined as a backward reflected wave. Assuming that a test signal is conducted to a node b, calculating a simulation waveform b1 of the node b according to the impedance value of the node b, wherein the simulation waveform b1 is used as the test signal of the node c, the negative and positive waveform 1 is transmitted to the node c, calculating a simulation waveform c1 of the node c according to the impedance of the node c, and so on, sequentially calculating a simulation waveform d1 and a simulation waveform e1 generated by the test signal passing through each node along the signal conduction direction, wherein a backward reflection wave in the simulation waveform generated by the last node is specified to be called a backward incident wave. The backward incident wave is transmitted along the direction of the test signal source end, sequentially passes through each node, and generates a simulation waveform d2, a simulation waveform c2, a simulation waveform b2 and a simulation waveform a2 at each node. And superposing the simulation waveform generated by the backward incident wave at the target node and the simulation waveform generated by the source end test signal at each node, thereby obtaining the final simulation waveform of each node.
According to the chip internal silicon chip pin signal simulation method and device provided by the invention, the signal test system obtains the data of the TDR impedance curve of the chip internal circuit 301; obtaining an equivalent circuit model of the chip internal circuit 301 according to the data of the TDR impedance curve; acquiring data of a test signal required to be applied to the chip external pin 303; and calculating simulation waveform data of the test signal transmitted to the pin of the chip internal silicon chip 303 through the chip internal circuit 301 according to the equivalent circuit model and the data of the test signal. The method and the device provide a method for simulating the signal transmitted to the pin 303 of the silicon chip in the chip by the test signal through the signal test system under the condition that the detailed packaging information in the chip can not be obtained, and further judge whether the signal quality meets the design requirement. The method well solves the technical difficulty of direct measurement of the chip internal silicon chip 303 pin signal method, and has great popularization value.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A chip internal silicon chip pin signal simulation method is applied to a signal test system, and is characterized in that a chip internal silicon chip pin is connected with a chip external pin through a chip internal circuit, and the method comprises the following steps:
acquiring data of a TDR impedance curve of the chip internal circuit;
obtaining an equivalent circuit model of the chip internal circuit according to the data of the TDR impedance curve;
acquiring data of a test signal required to be applied to an external pin of the chip;
and calculating simulation waveform data of the test signal conducted to the chip internal silicon chip pin through the chip internal circuit according to the equivalent circuit model and the data of the test signal.
2. The method for simulating a pin signal of a silicon chip in a chip according to claim 1, wherein the signal testing system comprises a TDR testing device; the step of obtaining the data of the TDR impedance curve of the chip internal circuit comprises the following steps:
sending the test signal to the chip external pin through the TDR test device;
and receiving a reflected signal generated by the test signal through the chip internal circuit from the chip external pin through the TDR test device, and obtaining the data of the TDR impedance curve of the chip internal circuit according to the reflected signal.
3. The method for simulating the pin signal of the silicon chip in the chip according to claim 2, wherein the signal testing system comprises a signal receiving measuring tool for simulating the real working environment of the signal receiving chip, and the signal receiving measuring tool comprises a first circuit board, a first testing chip area, a receiving end testing point, a first ground plane bright copper area and the signal receiving chip.
4. The method according to claim 1, wherein the step of calculating the simulation waveform data of the test signal conducted to the chip internal silicon chip pin through the chip internal circuit according to the equivalent circuit model and the data of the test signal comprises:
acquiring simulation precision preset by a signal testing system, wherein the simulation precision is used for representing time precision when the signal testing system simulates;
acquiring a transmission delay parameter of an equivalent circuit model in the chip;
and calculating simulation waveform data of the test signal transmitted to the chip internal silicon chip pin through the chip internal circuit according to the equivalent circuit model of the chip internal circuit, the data of the test signal, the preset simulation precision and the transmission delay parameter.
5. The chip internal silicon chip pin signal simulation method according to claim 4, wherein the step of obtaining the transmission delay parameter of the chip internal equivalent circuit model comprises:
and calculating the transmission delay parameter of the equivalent circuit model according to the data of the TDR impedance curve.
6. The method according to claim 5, wherein the step of calculating the simulation waveform data of the test signal transmitted to the pin of the chip internal silicon chip through the chip internal circuit according to the equivalent circuit model of the chip internal circuit, the data of the test signal, the preset simulation precision and the transmission delay parameter comprises:
obtaining the number of nodes of the equivalent circuit model according to the equivalent circuit model of the chip internal circuit, wherein the nodes represent the positions of impedance changes in the equivalent circuit model;
acquiring the time of the test signal conducted to each node and the time of the reflected wave conducted to each node according to the change relation of the data of the impedance curve along with the time;
and sequentially calculating simulation waveform data generated when the test signal is conducted to each node according to the time of conducting the test signal to each node.
7. The method for simulating the pin signal of the silicon chip in the chip according to claim 6, wherein the step of sequentially calculating the simulation waveform data of the nodes through which the test signal passes according to the time of the test signal being conducted to each node comprises:
according to the time for the test signal to be conducted to each node, sequentially taking the node to which the test signal is conducted as a target node;
calculating simulation waveform data of the target node under the action of the test signal;
judging whether a reflected wave of a last node in the test signal conduction direction is conducted to the target node;
and if the reflected wave of the last node is conducted to the target node, superposing the conducted reflected waveform data and the simulated waveform data of the target node.
8. The method for simulating the pin signal of the silicon chip in the chip according to claim 1, wherein the signal testing system comprises a signal acquisition device and a signal generation chip, and the step of acquiring the data of the test signal to be applied to the pin outside the chip comprises:
sending a preset test signal through the signal generating chip, wherein the test signal enters the signal acquisition device through a probe of the signal acquisition device;
and sampling the test signal through the signal acquisition device.
9. The method for simulating the pin signal of the silicon chip in the chip according to claim 8, wherein the signal generating chip is a part of a signal generating and measuring tool, the signal generating and measuring tool is used for simulating the real working environment of the signal generating chip, and the signal generating and measuring tool comprises a second circuit board, a second testing chip area, a sending end testing point, a power supply, a clock, a reset circuit, a debugging circuit, a second ground plane bright copper area and the signal generating chip.
10. A chip internal silicon chip pin signal simulation device is characterized by comprising a TDR impedance curve acquisition module, a chip internal circuit equivalent model acquisition module, a test signal acquisition module and a chip internal silicon chip pin simulation signal waveform calculation module;
the TDR impedance curve acquisition module is used for acquiring a TDR impedance curve of a chip internal circuit;
the chip internal circuit equivalent model obtaining module is used for obtaining the chip internal circuit equivalent model according to the data of the TDR impedance curve;
the test signal acquisition module is used for acquiring data of a test signal required to be applied to the external pin of the chip;
and the simulation calculation module is used for calculating simulation waveform data of the test signal transmitted to the chip internal silicon chip pin through the chip internal circuit according to the equivalent circuit model and the data of the test signal.
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Cited By (2)
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| CN114062896A (en) * | 2021-11-11 | 2022-02-18 | 深圳市慧邦电子科技有限公司 | Finished product testing method of integrated circuit and storage medium |
| TWI769484B (en) * | 2020-07-13 | 2022-07-01 | 鴻海精密工業股份有限公司 | Method of displaying connection status of pins of chip, computer device and storage medium |
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