CN104076270B - The tester table set for voltage - Google Patents
The tester table set for voltage Download PDFInfo
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- CN104076270B CN104076270B CN201310096110.8A CN201310096110A CN104076270B CN 104076270 B CN104076270 B CN 104076270B CN 201310096110 A CN201310096110 A CN 201310096110A CN 104076270 B CN104076270 B CN 104076270B
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- voltage
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- resistor
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Abstract
A kind of tester table set for voltage, described tester table comprises control unit and filter circuit, and wherein control unit is electrically connected with filter circuit.Control unit comprises field programmable gate array (FPGA), in order to provide a pulse-width modulation control signal；Filter circuit is in order to receive pulse-width modulation control signal, and exports at least one DC voltage.The present invention uses the FPGA of a low cost to accomplish to set the voltage of pin driver and receptor in Per Pin framework mode, and pin card (Pin Card) cost of Per Pin framework is greatly reduced.
Description
[technical field]
The invention relates to a kind of electronic equipment, and set for voltage in particular to a kind of
Tester table.
[background technology]
At present at the pin card (Pin Card) of tester table, setting pin driver and receptor
The voltage (such as: Vih/Vterm/Voh/Vol) of (Pin Driver/Pin Receiver) is to make
Set with digital-to-analog conversion chip (DAC IC), if pin card (Pin Card) is to use Per Group
Framework, is i.e. to be a group (Group) with multiple pin drivers and receptor, and this group is i.e.
Set the voltage of identical pin driver and receptor, so the digital-to-analog conversion chip needed is also
Will not be too many；If pin card (Pin Card) uses the mode of Per Pin framework, i.e. each connects
The foot driver voltage (such as: Vih/Vterm/Voh/Vol) that sets required with receptor all can independently set
Fixed, the quantity of required digital-to-analog conversion chip can increase, so at pin card (Pin Card)
On cost also can be significantly increased.
As can be seen here, above-mentioned existing framework, it is clear that still suffer from inconvenience and defect, and need into
One step is improved.In order to solve the problems referred to above, association area seeks solution the most painstakingly,
But the mode having no applicable has been developed the most always.Therefore, how to be effectively reduced into
This, one of current important research and development problem of real genus, also become currently associated field and need the target of improvement badly.
[summary of the invention]
Therefore, a purpose of the present invention is to be to provide a kind of tester table set for voltage, with
Solve problem of the prior art.
According to one embodiment of the invention, a kind of tester table set for voltage comprise control unit with
Filter circuit, wherein control unit is electrically connected with filter circuit.Control unit comprises field programmable gate
Array (FPGA), in order to provide a pulsewidth modulation (PWM) control signal；Filter circuit is in order to receive this
Pulse-width modulation control signal, and export at least one DC voltage.
Above-mentioned tester table also can comprise pin driver and receptor (Pin Driver/Pin
Receiver).Filter circuit is electrically connected with pin driver and receptor；Pin driver and reception
Device is in order to receive DC voltage, to test circuit under test.
Above-mentioned control unit also can comprise at least one inverter (Inverter), field programmable gate
Array is electrically connected with inverter, and inverter is in order to export pulse-width modulation control signal to filter circuit.
Furthermore, above-mentioned filter circuit can be low pass filter, and low pass filter is in order to by pulsewidth modulation
The high-frequency components of control signal filters to export DC voltage.
Furthermore, above-mentioned low pass filter can be RC low pass filter (RC low pass filter).
Furthermore, above-mentioned RC low pass filter can comprise the first resistor, the first capacitor, the second electricity
Resistance device and the second capacitor.First end of the first resistor connects the outfan of pulse wave transmitter unit；The
First end of one capacitor connects the second end of the first resistor, the second end ground connection of the first capacitor；
First end of the second resistor connects the first end of the first capacitor；First end of the second capacitor connects
Second end of the second resistor and load, the second end ground connection of the second capacitor.
In sum, technical scheme compared with prior art has clear advantage and useful
Effect.By technique scheme, can reach suitable technological progress, and have in industry extensive
Value, it at least has the advantage that
1. Per Pin sets pin driver and receptor to use the FPGA of a low cost to accomplish
Voltage, is greatly reduced pin card (Pin Card) cost of Per Pin framework；And
2. reduce the area taking printed circuit board (PCB) (PCB).
With embodiment, above-mentioned explanation will be explained in detail below, and the technical side to the present invention
Case provides and further explains.
[accompanying drawing explanation]
For the above and other purpose of the present invention, feature, advantage can be become apparent with embodiment,
Being described as follows of appended accompanying drawing:
Fig. 1 is the block chart of a kind of tester table set for voltage according to one embodiment of the invention；
Fig. 2 is the square of a kind of tester table set for voltage according to another embodiment of the present invention
Figure；And
Fig. 3 is the circuit diagram of a kind of tester table set for voltage according to one embodiment of the invention.
[detailed description of the invention]
In order to the narration making the present invention is more detailed with complete, can refer to appended accompanying drawing and the following stated
Various embodiments, reference identical in accompanying drawing represents same or analogous element.On the other hand,
Well-known element and step are not described in embodiment, unnecessary to avoid causing the present invention
Restriction.
" about " used herein, " about " or " substantially " be modify any can be slightly
The quantity of change, but this slight variations can't change its essence.If without especially in embodiment
Illustrate, then represent the range of error one of the numerical value modified with " about ", " about " or " substantially "
As be allowed in 20 percent within, preferably within 10, the most then be
Within 5 percent.
The technical scheme is that a kind of tester table set for voltage, it can be applicable to circuit
Test, or it is used in relevant sport technique segment widely.It should be noted that the technical program
Tester table is to use field programmable gate array (FPGA) to realize pulsewidth modulation (PWM) to control letter
Number output.The detailed description of the invention of tester table is described below with reference to Fig. 1 to Fig. 3.
Fig. 1 is the side of a kind of tester table 100 set for voltage according to one embodiment of the invention
Block figure.As it is shown in figure 1, tester table 100 comprises control unit 110 and filter circuit 120.At frame
On structure, control unit 110 is electrically connected with filter circuit 120.Control unit 110 comprises field-programmable
Gate array (FPGA) 111, in order to provide pulse-width modulation control signal；Filter circuit 120 is in order to receive
This pulse-width modulation control signal, and export at least one DC voltage.Whereby, the present invention uses low cost
FPGA replace high price digital-to-analog conversion chip so that cost is greatly reduced.
In the present embodiment, filter circuit 120 can be low pass filter, and low pass filter is in order to by arteries and veins
The high-frequency components of wide modulator control signal filters to export DC voltage.In practice, when pulsewidth modulation control
The frequency of signal processed is the highest, then the ripple (Ripple) of DC voltage is the least；Otherwise, when pulsewidth is adjusted
The frequency of control signal processed is the lowest, then the ripple of DC voltage is the biggest.It addition, work as pulse width modulation controlled
The dutycycle (duty cycle) of signal is bigger (such as: 246/256) or the least (such as: 10/256),
Then the ripple of DC voltage is the least；Otherwise, when the frequency of pulse-width modulation control signal more approaches intermediate value
(such as: 128/256), then the ripple of DC voltage is the biggest.Therefore, those skilled in the art should regard and work as
Time need the frequency of pulse-width modulation control signal and the duty of elasticity design field programmable gate array 111
Ratio.
Fig. 2 is a kind of tester table 100 set for voltage according to another embodiment of the present invention
Block chart.As in figure 2 it is shown, except above-mentioned field programmable gate array 111 and filter circuit 120 with
Outward, tester table 100 also comprises pin driver and receptor (Pin Driver/Pin Receiver)
130.Architecturally, filter circuit 120 is electrically connected with pin driver and receptor 130.In use
Time, pin driver and receptor (Pin Driver/Pin Receiver) 130 are in order to receive filter
The exported DC voltage of wave circuit 120, according to this test circuit under test 210.Whereby, the present invention uses existing
Field programmable gate array realizes the output of pulse-width modulation control signal, completes pin driver and reception
The voltage (such as: Vih/Vterm/Voh/Vol) of device 130 sets.As for pin driver and receptor
Hardware structure in 130 is for having technology well known to usually intellectual in the art, and non-invention
Be intended to protection domain, no longer describes it in detail in this.
Fig. 3 is the electricity of a kind of tester table 100 set for voltage according to one embodiment of the invention
Lu Tu.As it is shown on figure 3, control unit 110 comprises at least one inverter (Inverter) 112, existing
Field programmable gate array 111 is electrically connected with inverter 112, and inverter 112 is in order to by pulse width modulation controlled
Signal exports to filter circuit 120.For example, inverter 112 can be hex inverter (hex
Inverter), its model is 74AC04.Or, in other embodiments, it is possible to omit inverter
112, those skilled in the art optionally ought flexibly choose whether inverter 112 to be arranged.
Furthermore, filter circuit 120 can be low pass filter, and specifically, this low pass filter is RC
Low pass filter (RC low pass filter).
Above-mentioned RC low pass filter can comprise the first resistor R1, the first capacitor C1, the second electricity
Resistance device R2 and the second capacitor C2.Architecturally, first end of the first resistor R1 connects control list
The outfan of unit 110；First end of the first capacitor C1 connects second end of the first resistor R1,
The second end ground connection of the first capacitor C1；First end of the second resistor R2 connects the first capacitor C1
The first end；First end of the second capacitor C2 connects the second end and the load 310 of the second resistor R2,
The second end ground connection of the second capacitor C2.In time using, first end of the first capacitor C1 can conduct
One voltage output end, first end of the second capacitor C2 can be as another voltage output end.
In practice, if the resistance value that the resistance value of the first resistor R1 is equal to the second resistor R2, and
The capacitance of the first capacitor C1 capacitance equal to the second capacitor C2, when capacitance is the biggest,
Then the ripple of DC voltage is the least；Otherwise, when capacitance more hour, then the ripple of DC voltage is the biggest.
It addition, RC low pass filter also can comprise the 3rd capacitor NC, the 3rd capacitor NC and second
Capacitor C2 is in parallel.Load 310 can be equivalent to electrical switch, as shown in Figure 3.
About the first resistor R1, the first capacitor C1, the second resistor R2 and the second capacitor C2
Numerical value generally, for example, can refer to following table one:
| R1；R2(ohm) | C1；C2 | fclk；fPWM |
| 50；21.5k | 100nF；21.5pF | 100MHz；390kHz |
＜ table one ＞
As for the result of the output DC voltage of filter circuit 120, can refer to following table two:
＜ table two ＞
It will be understood that the data in above table one, table two are only and illustrate, it is not limiting as the present invention, real
In business, those skilled in the art should be depending on needing elastic design at that time.
Although the present invention is disclosed above with embodiment, so it is not limited to the present invention, ability
Field technique personnel, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations,
Therefore protection scope of the present invention should be as defined in claim.
Claims (5)
1. the tester table set for voltage, it is characterised in that: this tester table comprises:
Control unit, comprises field programmable gate array, in order to provide pulse-width modulation control signal；With
And
Filter circuit, is electrically connected with this control unit, in order to receive this pulse-width modulation control signal, and
Output at least one DC voltage,
This control unit also comprises: at least one inverter, is electrically connected with this field programmable gate array,
In order to this pulse-width modulation control signal is exported to this filter circuit.
2. the tester table set for voltage as claimed in claim 1, it is characterised in that: also wrap
Contain:
Pin driver and receptor, be electrically connected with this filter circuit, in order to receive this DC voltage,
To test circuit under test.
3. the tester table set for voltage as claimed in claim 1, it is characterised in that: this filter
Wave circuit is low pass filter, and this low pass filter is in order to become the high frequency of this pulse-width modulation control signal
Part filters to export this DC voltage.
4. the tester table set for voltage as claimed in claim 3, it is characterised in that: this is low
Bandpass filter is RC low pass filter.
5. the tester table set for voltage as claimed in claim 4, it is characterised in that: this RC
Low pass filter comprises:
First resistor, the first end of this first resistor connects the outfan of this control unit；
First capacitor, the first end of this first capacitor connects the second end of this first resistor, should
Second end ground connection of the first capacitor；
Second resistor, the first end of this second resistor connects the first end of this first capacitor；With
And
Second capacitor, the first end of this second capacitor connects second end and of this second resistor
Load, the second end ground connection of this second capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310096110.8A CN104076270B (en) | 2013-03-25 | 2013-03-25 | The tester table set for voltage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310096110.8A CN104076270B (en) | 2013-03-25 | 2013-03-25 | The tester table set for voltage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104076270A CN104076270A (en) | 2014-10-01 |
| CN104076270B true CN104076270B (en) | 2016-09-28 |
Family
ID=51597662
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310096110.8A Active CN104076270B (en) | 2013-03-25 | 2013-03-25 | The tester table set for voltage |
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| Country | Link |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200403445A (en) * | 2002-07-11 | 2004-03-01 | Sharp Kk | Semiconductor testing apparatus and semiconductor testing method |
| CN1786728A (en) * | 2004-12-08 | 2006-06-14 | 中兴通讯股份有限公司 | Method and apparatus for testing UPS control unit |
| CN101587167A (en) * | 2009-07-08 | 2009-11-25 | 天津渤海易安泰电子半导体测试有限公司 | Multi-functional integrated circuit chip testing machine |
| CN101592707A (en) * | 2009-07-08 | 2009-12-02 | 天津渤海易安泰电子半导体测试有限公司 | Analog and digital mixed signal chip test card |
| CN201434902Y (en) * | 2009-07-08 | 2010-03-31 | 天津渤海易安泰电子半导体测试有限公司 | Test card for analog and digital mixed signal chip on chip tester |
| CN201434900Y (en) * | 2009-07-08 | 2010-03-31 | 天津渤海易安泰电子半导体测试有限公司 | Novel tester for integrated-circuit chip |
| TW201134083A (en) * | 2010-03-22 | 2011-10-01 | Nzxt Corp | DC motor with dual power supply method for speed control |
-
2013
- 2013-03-25 CN CN201310096110.8A patent/CN104076270B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200403445A (en) * | 2002-07-11 | 2004-03-01 | Sharp Kk | Semiconductor testing apparatus and semiconductor testing method |
| CN1786728A (en) * | 2004-12-08 | 2006-06-14 | 中兴通讯股份有限公司 | Method and apparatus for testing UPS control unit |
| CN101587167A (en) * | 2009-07-08 | 2009-11-25 | 天津渤海易安泰电子半导体测试有限公司 | Multi-functional integrated circuit chip testing machine |
| CN101592707A (en) * | 2009-07-08 | 2009-12-02 | 天津渤海易安泰电子半导体测试有限公司 | Analog and digital mixed signal chip test card |
| CN201434902Y (en) * | 2009-07-08 | 2010-03-31 | 天津渤海易安泰电子半导体测试有限公司 | Test card for analog and digital mixed signal chip on chip tester |
| CN201434900Y (en) * | 2009-07-08 | 2010-03-31 | 天津渤海易安泰电子半导体测试有限公司 | Novel tester for integrated-circuit chip |
| TW201134083A (en) * | 2010-03-22 | 2011-10-01 | Nzxt Corp | DC motor with dual power supply method for speed control |
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| Publication number | Publication date |
|---|---|
| CN104076270A (en) | 2014-10-01 |
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