CN101577792A - Judgment device of operation mode and judgment method thereof - Google Patents
Judgment device of operation mode and judgment method thereof Download PDFInfo
- Publication number
- CN101577792A CN101577792A CN 200810097261 CN200810097261A CN101577792A CN 101577792 A CN101577792 A CN 101577792A CN 200810097261 CN200810097261 CN 200810097261 CN 200810097261 A CN200810097261 A CN 200810097261A CN 101577792 A CN101577792 A CN 101577792A
- Authority
- CN
- China
- Prior art keywords
- push button
- delay
- button signalling
- clock pulse
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
The invention discloses a judgment device of an operation mode and a judgment method thereof. The judgment device consists of a pulse generating unit and a hold up unit, wherein the pulse generating unit is used for responding a plurality of key signals so as to respectively output a one shot pulse signal; and the hold up unit receives a plurality of key signals so as to respectively generate a plurality of delay key signals corresponding to the key signals in a clock pulse delay way. The one shot pulse signals and the delay key signals are used for judging in which operation mode a system is.
Description
Technical field
The invention relates to a kind of judgment means of operator scheme, particularly a kind ofly be in the judgment means of which kind of operator scheme with the push button signalling of delay system to judge a system by holding unit.
Background technology
Digital camera has developed into consumption electronic products, therefore, be different from traditional camera, digital camera has existed various states and operator scheme in operation, as open state (Power ON status), off-mode (Power OFF status), preview mode (Preview Mode), recording playback pattern (Playback Mode), universal serial bus existence (USB in Status) ... Deng.Therefore internal system must clearly be judged various states, and then correctly carries out various pattern operations.
Please refer to Figure 1A, disclose the decision circuitry 100 of the operator scheme that is applied to digital camera for prior art.This decision circuitry 100 produces circuit 110, a plurality of key press detecting circuit 130 and peripheral unit testing circuit 150 by a pulse wave and forms.The composition and the running of these circuit below are described respectively.
When battery is mounted in the camera, the high pass filter filters that cell voltage Vbat can be made up of capacitor C 1 and resistance R 1 earlier, produce one in node N1 subsequently and click (One shot) pulse wave signal, this voltage amplitude peak value of clicking pulse wave signal is equal to cell voltage Vbat.Therefore, when the amplitude of clicking pulse wave signal (being cell voltage Vbat) when being higher than the threshold voltage of switch S 1, switch S 1 is with conducting, and this moment, the voltage quasi position of node N2 will be dragged down, with actuating switch S2.After switch S 2 conductings, the voltage of node N3 is set up thereupon, and the high pass filter filters of forming via capacitor C 2 and resistance R 2 and export and click pulse wave signal to pin position Power_ON/OFF.
In some digital camera, can further handle again and click pulse wave signal to finish start.For example, after pulse wave signal is clicked in Power_ON/OFF reception in pin position, can again this be clicked the digital signal processor that pulse wave signal is sent to system.After digital signal processor receives this pulse wave signal, a multichannel (Multi-channel) transducer can be opened, to produce the voltage of 3.3V.The multichannel transducer mainly in order to the voltage of conversion camera system, is exported with the voltage that many groups are provided.
Usually can be provided with a plurality of operation push-buttons on the digital camera, for example be used for opening and closing camera switch key, be used for the captured photo of preview the preview button, be used for recording a video and the recording playback button play etc.The quantity of key press detecting circuit 130 respective operations buttons and being provided with.In addition, digital camera also can be provided with the peripheral unit connecting interface, for example universal serial (Universal Serial Bus; USB), link with storage device with the outside.
After camera was finished boot action, if the button B1 of camera is triggered, this moment was with actuating switch S3 and switch S 4.This moment, the voltage quasi position of node N2 was dragged down again, so that switch S 2 conducting once again makes pin position Power_ON/OFF promptly can export one again and click pulse wave signal, and the corresponding detection pin position B1_D of button B1 can export and trigger the reverse signal in pin position.The firmware of digital camera system (Firm Ware) just can enter corresponding operator scheme, for example: open state, off-mode, preview mode, recording playback pattern etc. according to the pulse wave signal of pin position Power_ON/OFF and the output signal that detects the pin position.
If when having a peripheral unit to be connected to USB (USB) interface of system, input U50 on the testing circuit 150 will receive a logic high levle signal, make switch S 51 conductings, pin position Power_ON/OFF can export one similarly and click pulse wave signal.
In Figure 1A, the signal level of corresponding detection pin position B1_D can keep a period of time because of the time delay circuit that resistance R 3 and capacitor C 3 are formed.Please refer to Figure 1B, when the button B1 in key press detecting circuit 130 is depressed (time point t1), cross-pressure VC3 on the capacitor C 3 is charged to 3.3V (volt) rapidly, and switch S 3 and switch S 4 detect the detection signal SB1_D that pin position B1_D can produce a logic low level this moment with conducting.When button B1 is bled off (time point t2), the electric charge that is accumulated on the capacitor C 3 begins discharge, when the cross-pressure VC3 of capacitor C 3 is lower than the conducting threshold voltage Vth of switch S 4 (time point t3), switch S 4 will be closed, and detection signal SB1_D can transition be the logic high levle.Time point t2 in the time of can finding out that by Figure 1B button B1 is bled off and detection signal SB1_D transition are the two one retention time of time gap of time point t3 of logic high levle, (Hold up time) makes the firmware of digital camera system that time enough can be arranged by this retention time, clicks pulse wave signal and a detection signal judges camera system is to be in which kind of operator scheme according to one.
Yet the decision circuitry shown in the 1A figure may have following problem.Because button B1 adopts the positive logic operation, that is operation push-button system is electrically connected to power supply, therefore when with the decision circuitry integrated circuit shown in Figure 1A, need extra pin and be connected to power supply, may cause the volume of single unit system to increase thus.
And capacitor C 3 is except the composition assembly as time delay circuit, and the undesired energy that also is used for preventing static discharge is scurried into and caused the misoperation of switch S 3, therefore generally makes the big electric capacity of electricity capacity greater than 10uF.Because capacitor C 3 is a discrete component with resistance R 3, general components values all can have error, therefore can cause error time of delay, and reduces the reliability of circuit.
In addition, use transistor (NMOS or BJT), so the accurate position of the threshold voltage of each switch (Threshold voltage) may be not quite similar as switch.Because the error that has of assembly itself, thus transistor may not can conducting under predetermined voltage, this phenomenon is called time door phenomenon (Sub-threshold), this phenomenon has more increased the error that state is judged.
Except above reliability issues, the circuit shown in Figure 1A must utilize capacitor C 1 and resistance R 1, capacitor C 2 to form high pass filter with resistance R 2, to reach the effect that pulse wave is clicked in output one.But the negative voltage when needing diode D1, D2 inhibition RC to discharge and recharge is in order to avoid damage back level switch and circuit.Therefore, cause the part of circuit to increase, also make the cost of circuit rise.
Summary of the invention
The present invention discloses a kind of judgment means of operator scheme, in order to judge the operator scheme of a system.
Judgment means according to the disclosed operator scheme of embodiments of the invention, keep (hold up) unit to form by a pulse wave generating unit and, wherein pulse wave generating unit is clicked (one shot) pulse wave signal in order to respond a plurality of push button signallings to export one respectively; And keep (hold up) unit to receive these a plurality of push button signallings, produce a plurality of delay push button signallings respectively with the clock pulse delayed mode corresponding to these a plurality of push button signallings.In an embodiment, click pulse wave signal and to postpone push button signalling be in order to judge which kind of operator scheme is a system be in.
According to the determination methods of the disclosed operator scheme of embodiments of the invention, it provides a plurality of buttons that can produce a plurality of push button signallings respectively earlier; Then respond a wherein push button signalling, click (one shot) pulse wave signal to export one; Produce corresponding to one of this push button signalling with a clock pulse delayed mode again and postpone push button signalling; Click pulse wave signal according to this at last and this delay push button signalling judges which kind of operator scheme is a system be in; In an embodiment, this clicks pulse wave signal and this delay push button signalling is in order to judge which kind of operator scheme is a system be in.
Above about content of the present invention explanation and the explanation of following execution mode be in order to demonstration with explain spirit of the present invention and principle, and provide claim protection range of the present invention further to explain.
Description of drawings
Figure 1A is the circuit diagram of the judgment means of the disclosed operator scheme of prior art;
Figure 1B is the disclosed retention time schematic diagram of prior art;
Fig. 2 is the circuit diagram of the judgment means of the disclosed operator scheme of the present invention;
Fig. 3 A is the holding circuit in the judgment means of the disclosed operator scheme of the present invention;
Fig. 3 B is push button signalling of the present invention, the clock pulse schematic diagram of delay push button signalling, detection signal and retention time;
Fig. 4 is another embodiment of the holding circuit in the judgment means of the disclosed operator scheme of the present invention;
Fig. 5 is integrated in the schematic diagram of chip for the disclosed status determination circuit of the present invention;
Fig. 6 is the time-pulse signal generator in the judgment means of the disclosed operator scheme of the present invention.
[primary clustering symbol description]
100................................. decision circuitry
110................................. pulse wave produces circuit
130................................. key press detecting circuit
150................................. peripheral unit testing circuit
200................................. pulse wave generating unit
201................................. one shots
202................................. logic lock
203................................. logic lock
204................................. logic lock
205................................. one shots
300................................. holding unit
310................................. latch circuit
320................................. clock pulse delay circuit
3211................................ first flip-flop
3212................................ second flip-flop
321N................................ flip-flop
330.................................AND lock
400................................. supply voltage
401................................. switch
402................................. switch
403................................. switch
404................................. comparator
405................................. noise canceller circuit
406................................. noise canceller circuit
407................................. noise canceller circuit
408................................. noise canceller circuit
409................................. clock signal produces circuit
412................................. current source
413................................. switch
414................................. comparator
500................................. input
501................................. button
502................................. button
503................................. button
501a................................ push button signalling
501b................................ delay push button signalling
501c................................ detection signal
502a................................ push button signalling
502b................................ delay push button signalling
502c................................ detection signal
503a................................ push button signalling
503b................................ delay push button signalling
503c................................ detection signal
504................................. inverter
505................................. inverter
506................................. inverter
511～520............................ pin
Vbat................................ cell voltage
S1.................................. switch
S2.................................. switch
S3.................................. switch
S4.................................. switch
S51................................. switch
N1.................................. node
N2.................................. node
N3.................................. node
C................................... electric capacity
C1.................................. electric capacity
C2.................................. electric capacity
C3.................................. electric capacity
R1.................................. resistance
R2.................................. resistance
R3.................................. resistance
D1.................................. diode
D2.................................. diode
B1_D................................ detect the pin position
Power_ON/OFF........................ pin position
U50................................. input
B1.................................. button
T1.................................. time point
T2.................................. time point
T3.................................. time point
SB1_D............................... detection signal
CLOCK............................... clock signal
R................................... first input end
S................................... second input
Q................................... output
D................................... second input
CLK................................. the 3rd input
E0.................................. falling edge
E1.................................. rising edge
E2.................................. rising edge
Vcc............................... logic high levle signal
Embodiment
Below in execution mode, be described in detail detailed features of the present invention and advantage; its content is enough to make any related art techniques person of haveing the knack of to understand technology contents of the present invention and implements according to this; and according to the disclosed content of this specification, claim protection range and accompanying drawing, any correlation technique person of haveing the knack of can understand purpose and the advantage that the present invention is correlated with easily.
Following embodiment further describes viewpoint of the present invention, but non-to limit category of the present invention anyways.
Please refer to Fig. 2, be the judgment means schematic diagram of the disclosed operator scheme of the present invention, it mainly is made up of with keeping (hold up) unit 300 pulse wave generating unit 200.Pulse wave generating unit 200 is clicked (one shot) pulse wave signal in order to respond the push button signalling that a plurality of operation push-button produces to export one respectively.Holding unit 300 is in order to receiving a plurality of push button signallings that a plurality of operation push-button produces, and produces a plurality of delay push button signallings corresponding to a plurality of push button signallings respectively with the clock pulse delayed mode.Pulse wave generating unit 200 is produced clicks delay push button signalling that pulse wave signal and holding unit 300 produced in order to judge which kind of operator scheme is a system be in.In one embodiment, this system can be a camera system.Certainly also can be the system of other kind.
In this embodiment, be provided with three buttons 501,502,503, each operation push-button is to electrically connect with earth point.Therefore be depressed when bleeding off again when any operation push-button wherein, will produce the push button signalling of a tool logic low level pulse wave.Produce in order to make pulse wave generating unit 200 accurately respond push button signalling and to click pulse wave signal, each button 501,502,503 equal correspondence is provided with an inverter 504,505,506, with push button signalling anti-phase be the push button signalling of a tool logic high levle pulse wave.
The judgment means of present embodiment includes a comparator 404, supply voltage 400 is supplied by a battery, when cell voltage is higher than an accurate position of triggering (Trigger Level), 1.7 volts shown in the figure for example, the output signal of comparator 404 will be changeed the logic high levle by the logic low level, thereby triggering one shots 201 in the pulse wave generating unit 200, one shots 201 is triggered and produces one and click pulse wave signal, and is received by logic lock 202.In this embodiment, be with or the door as logic lock 202, no matter therefore the accurate position of the input signal of logic lock 202 another inputs why, the pulse wave signal of clicking of the tool logic high levle that logic lock 202 all can be produced one shots 201 exports one shots 205 to.Since logic lock 202 output to click that pulse wave signal has by the transition of logic low level be rising edge (rising edge) signal of logic high levle, therefore will trigger one shots 205, click pulse wave signal to export another.
In this embodiment, be provided with three buttons 501,502,503, each button is to electrically connect with earth point.Therefore be depressed when bleeding off again when any button wherein, will produce the push button signalling of a tool logic low level pulse wave.Each button 501,502,503 equal correspondence is connected to an inverter 504,505,506, with push button signalling anti-phase be the push button signalling of a tool logic high levle pulse wave.When arbitrary input of logic lock 203 receives the push button signalling of tool logic high levle pulse wave, the push button signalling of tool logic high levle pulse wave will export logic lock 204 to via logic lock 203.Trigger accurate position because the supply voltage 400 of system has been higher than this moment, therefore another input of logic lock 204 also can receive the signal of a logic high levle of being exported from comparator 404, makes the push button signalling of tool logic high levle pulse wave export logic lock 202 to via logic lock 204 again.The push button signalling of tool logic high levle pulse wave exports one shots 205 to via logic lock 202 again, exports one and clicks pulse wave signal to trigger one shots 205.
In addition, when a peripheral device connect to be gone up the USB interface of system, input 500 will receive the detection signal of a logic high levle to logic lock 203, and pulse wave generating unit 200 is exported a mode of clicking pulse wave signal as hereinbefore, does not repeat them here.
Above pulse wave generating unit 200 described logic locks only are exemplary illustration, anyly be familiar with this operator and all can form the circuit with identical function by logic lock arbitrarily or impartial circuit, make pulse wave generating unit 200 all exportable one click pulse wave signal when following situation takes place: (1) has arbitrary push button signalling generation; (2) supply voltage is greater than a predetermined voltage; (3) one peripheral devices connect the USB interface of the system of going up.
In the embodiment shown in Figure 2, more include a plurality of noise canceller circuits 405,406,407, electrically connect with button 501,502,503 respectively, in order to the noise of a plurality of push button signallings of difference filtering.Similarly, input 500 also can be provided with noise canceller circuit 408, to eliminate noise.
In the embodiment shown in Figure 2, more include a clock pulse signal generating circuit 409, give holding unit 300 in order to produce a clock pulse signal CLOCK.
The holding unit 300 of present embodiment includes three identical holding circuits, in order to receive three push button signallings respectively, to produce three delay push button signallings corresponding to three push button signallings respectively.As shown in Figure 3A, a holding circuit is made up of a latch circuit 310 and a clock pulse delay circuit 320.
The clock pulse delay circuit 320 of present embodiment is to realize that with an offset buffer (Shift Register) circuit clock pulse delay circuit 320 comprises N flip-flop, and the first input end R of first flip-flop 3211 receives the corresponding key signal.The second input D (data input pin) of first flip-flop 3211 is connected with a logic high levle signal Vcc, output Q then is connected with the second input D of second flip-flop 3212, and the output Q of last flip-flop 321N then is connected with the second input S that fastens lock circuit 310.The clock signal that the 3rd input CLK (clock pulse input) of each flip-flop receives as shown in Figure 2 produces the clock signal CLOCK that circuit 409 is produced.
Please refer to Fig. 2 and Fig. 3 A, with button 501 is example, button 501 is depressed when bleeding off again, the push button signalling 501a of a tool logic low level pulse wave will be produced, shown in Fig. 3 B, the first input end R of latch circuit 310 is triggered by the falling edge (e0) of this push button signalling 501a, makes latch circuit 310 export the delay push button signalling 501b of a logic low level in output Q, when push button signalling 501a is in the logic low level, postpone push button signalling 501b bolt-lock in the logic low level.Similarly, button 502,503 is depressed when bleeding off again, will produce push button signalling 502a, the 503a of a tool logic low level pulse wave respectively.
After push button signalling 501a transfers the logic high levle to, clock pulse delay circuit 320 is triggered by the rising edge (e1) of push button signalling 501a, after clock signal CLOCK is through N, last flip-flop 321N is passed to the second input S of latch circuit 310 with logic high levle signal Vcc, makes that to postpone push button signalling 501b transition be the logic high levle.
Can find out the two i.e. retention time of time gap of the rising edge of push button signalling 501a (e1) and the rising edge (e2) that postpones push button signalling 501b by Fig. 3 B.In an embodiment, three holding circuits are all identical corresponding to three retention times that push button signalling produced, and just clock pulse postpones all the same.
Clock pulse delay circuit 320 of the present invention is not limited to a shift cache circuit, for example also can realize clock pulse delay circuit 320 with a frequency eliminator circuit, and flip-flop that so can less mutual serial connection reaches the bigger retention time.
In this embodiment, latch circuit 310 is to decide according to the quantity of button with the quantity of clock pulse delay circuit 320.For example when the number of button is three, three groups of latch circuits and three groups of clock pulse delay circuits are set.
In another embodiment, share, as shown in Figure 4, only need configuration one AND lock 330 this moment no matter the quantity of latch circuit 310, also can only be provided with one group of clock pulse delay circuit 320 why.
In the embodiment shown in Figure 2, can include a plurality of switches 401,402,403 in addition, in order to receive a plurality of delay push button signalling 501b, 502b, the 503b that holding unit 300 is exported respectively, with difference output detection signal 501c, 502c, 503c.In one embodiment, be example with button 501, button 501 is depressed when bleeding off again, with the detection signal 501c that produces as shown in Figure 2.Pulse wave signal also can be clicked and a detection signal is to judge which kind of operator scheme is this system be in by one by system.
The disclosed status determination circuit of the present invention can be integrated in the chip, and schematic diagram as shown in Figure 5 in the time of in being integrated in chip, can be provided with a plurality of pins.For example pin 511,512,513,514,515 is used for receiving inputted signal, for example pin 511 receives power supply signal, pin 512,513,514 is used for receiving respectively a push button signalling, and pin 515 is used for receiving a peripheral device and connects the detection signal of going up USB interface.Pin 516 is used for exporting the pulse wave signal of clicking of pulse wave generating unit 200 outputs.Pin 517,518,519 is used for exporting the detection signal corresponding to a push button signalling respectively.
Please refer to Fig. 6, produce the circuit diagram of an embodiment of circuit 409 for clock signal.Clock signal produces circuit 409 and is made up of a current source 412, a switch 413, a comparator 414 and a capacitor C.Current source 412 is in order to the capacitor C charging, and when switch 413 not conductings, 412 pairs of capacitor C of current source are charged, and when switch 413 conductings, the electric charge that is accumulated on the capacitor C discharges over the ground, so capacitor C can produce the cross-pressure of a triangular wave.414 signal and predetermined voltages with triangular wave of comparator compare, and with the clock signal CLOCK of output preset frequency, the concussion frequency of clock signal CLOCK can be adjusted by the capacitance that changes capacitor C.
In embodiment as shown in Figure 5, capacitor C can be disposed at outside the chip, be connected with pin 520.
According to embodiments of the invention, if button is operated in the negative logic mode, after the circuit integrated circuit, need not remove to receive 3.3V in additionally many pin positions, can save the space of a pin position.
In addition, see through the setting of noise canceller circuit, can will be built in the circuit in the noise jamming eliminating mechanism, (Electrostatic Discharge, when ESD) testing, undesired energy is scurried into and is caused the misoperation of IC output signal can to avoid doing static discharge.
According to embodiments of the invention, hold time (the Hold up time) of its detection signal can adjust, and only need use smaller capacitive, and general 10nF can reach constant time of delay as precedent.The error of holding time in addition is little, can be controlled in 10%.In the circuit of Fig. 1, its error may surpass 50%.
When the disclosed embodiment of the present invention was implemented with chip form, the whole standby current maximum of IC was no more than 5 μ A, therefore can significantly reduce overall power dissipation.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (10)
1. the judgment means of an operator scheme is characterized in that, includes:
One pulse wave generating unit in order to respond a plurality of push button signallings, is clicked pulse wave signal to export one respectively; And
One holding unit in order to receiving these a plurality of push button signallings, produces a plurality of delay push button signallings corresponding to these a plurality of push button signallings respectively with the clock pulse delayed mode;
Wherein this clicks pulse wave signal and this delay push button signalling is in order to judge which kind of operator scheme is a system be in.
2. judgment means according to claim 1, it is characterized in that, this device includes a plurality of switches in addition, receive these a plurality of delay push button signallings respectively, to export a plurality of detection signals corresponding to these a plurality of delay push button signallings respectively, wherein this clicks pulse wave signal and this detection signal is in order to judge which kind of operator scheme is this system be in.
3. judgment means according to claim 1 is characterized in that this holding unit includes a plurality of holding circuits, in order to receive these a plurality of push button signallings respectively, to produce a plurality of delay push button signallings corresponding to these a plurality of push button signallings respectively.
4. judgment means according to claim 3 is characterized in that, one of them includes these a plurality of holding circuits:
One latch circuit, in order to produce a corresponding push button signalling that postpones, an input of this latch circuit is triggered by one first edge of a corresponding push button signalling, the accurate position that makes this correspondence postpone push button signalling change and bolt-lock in one first accurate; And
One clock pulse delay circuit, receive a clock pulse signal, by being triggered at one second edge of this correspondence push button signalling, behind the clock pulse of a predetermined number, this clock pulse delay circuit triggers another input of this latch circuit, and one second accurate position is changed in the accurate position that makes this correspondence postpone push button signalling.
5. judgment means according to claim 4 is characterized in that, this device includes a clock pulse signal generator in addition, in order to produce this clock signal.
6. judgment means according to claim 4 is characterized in that, this clock pulse delay circuit is a shift cache circuit.
7. judgment means according to claim 4 is characterized in that, this clock pulse delay circuit is a frequency eliminator circuit.
8. judgment means according to claim 1 is characterized in that, these a plurality of holding circuits postpone all the same for the clock pulse that this a plurality of push button signalling caused.
9. the determination methods of an operator scheme is characterized in that, includes:
A plurality of buttons that can produce a plurality of push button signallings respectively are provided;
Response is a push button signalling wherein, clicks pulse wave signal to export one;
Postpone push button signalling with clock pulse delayed mode generation corresponding to one of this push button signalling; And
Click pulse wave signal and this delay push button signalling judges which kind of operator scheme is a system be in according to this.
10. determination methods according to claim 9 is characterized in that, this clock pulse delayed mode produces in the step of this delay push button signalling and includes:
Provide a latch circuit to produce this delay push button signalling;
With one first this latch circuit of edge-triggered of this push button signalling with the accurate position that changes this delay push button signalling and bolt-lock in one first accurate position;
A clock pulse delay circuit that receives a clock pulse signal is provided; And
With this arteries and veins delay circuit of one second edge-triggered of this push button signalling, behind the clock pulse of a predetermined number, this clock pulse delay circuit triggers this latch circuit, makes the accurate position of this delay push button signalling change into one second accurate position.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810097261 CN101577792B (en) | 2008-05-06 | 2008-05-06 | Judgment device of operation mode and judgment method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810097261 CN101577792B (en) | 2008-05-06 | 2008-05-06 | Judgment device of operation mode and judgment method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101577792A true CN101577792A (en) | 2009-11-11 |
| CN101577792B CN101577792B (en) | 2011-01-19 |
Family
ID=41272561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200810097261 Expired - Fee Related CN101577792B (en) | 2008-05-06 | 2008-05-06 | Judgment device of operation mode and judgment method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101577792B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102281064A (en) * | 2010-06-13 | 2011-12-14 | 普诚科技股份有限公司 | Click circuit, transmitter and method for saving starting time of transmitter |
| CN106648911A (en) * | 2016-11-28 | 2017-05-10 | 武汉斗鱼网络科技有限公司 | Method and device for keystroke buffeting elimination |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100220672B1 (en) * | 1994-10-31 | 1999-09-15 | 전주범 | Time interval measurer having parallel architecture |
| JP3815209B2 (en) * | 2000-11-20 | 2006-08-30 | セイコーエプソン株式会社 | Generation of pulse signal from clock signal |
| DE102004016073B4 (en) * | 2004-03-30 | 2010-12-23 | Texas Instruments Deutschland Gmbh | A method of generating a pulse output signal from a periodic sawtooth signal and a reference voltage, and a clocked current transformer |
| CN200947595Y (en) * | 2006-08-24 | 2007-09-12 | 深圳市科陆电子科技股份有限公司 | Key-press circuit for switch |
-
2008
- 2008-05-06 CN CN 200810097261 patent/CN101577792B/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102281064A (en) * | 2010-06-13 | 2011-12-14 | 普诚科技股份有限公司 | Click circuit, transmitter and method for saving starting time of transmitter |
| CN102281064B (en) * | 2010-06-13 | 2014-12-17 | 普诚科技股份有限公司 | Click circuit, transmitter and method for saving starting time of transmitter |
| CN106648911A (en) * | 2016-11-28 | 2017-05-10 | 武汉斗鱼网络科技有限公司 | Method and device for keystroke buffeting elimination |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101577792B (en) | 2011-01-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103107528B (en) | Power clamping electrostatic discharge protection circuit | |
| US6535057B2 (en) | Programmable glitch filter | |
| CN101373199B (en) | Method of forming ESD detector and structure thereof | |
| CN101673136B (en) | Power control unit and on/off method | |
| CN103280962A (en) | Short circuit recovery soft starting circuit | |
| JP3484212B2 (en) | Power loss sensor | |
| CN103684374A (en) | Zero or ultra-low dc current consumption power-on and brown-out detector | |
| JP2007529983A (en) | Intelligent battery switching circuit block for portable devices | |
| CN102255304A (en) | ESD (Electro Spark Detector) power clamping circuit | |
| CN101577792B (en) | Judgment device of operation mode and judgment method thereof | |
| CN103208980A (en) | Window voltage comparison device | |
| US6507221B2 (en) | Circuit for the filtering of parasitic logic signals | |
| CN206270863U (en) | Cmos data remove device and computer | |
| TWI389458B (en) | Detecting device for detecting an operating mode of a system and detecting method thereof | |
| CN211478984U (en) | Low-power consumption monostable circuit capable of being triggered repeatedly | |
| TWI625904B (en) | Audio jack detection structure and method thereof | |
| US7081780B2 (en) | Reset circuitry for an integrated circuit | |
| CN203590181U (en) | Audio frequency power amplifier starting charging circuit | |
| CN1560996A (en) | Short pulse canel circuit | |
| CN203840306U (en) | Power source start-up reset circuit | |
| US20240056055A1 (en) | Glitch-free low-pass filter circuit and system circuit using the same | |
| CN207249602U (en) | Reset circuit | |
| CN111338414B (en) | Low-power consumption monostable circuit capable of being triggered repeatedly | |
| CN112290612B (en) | Light-load detection circuit | |
| CN101082874A (en) | Signal treating system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110119 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |