CN1560996A - Short pulse canel circuit - Google Patents
Short pulse canel circuit Download PDFInfo
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- CN1560996A CN1560996A CNA2004100074459A CN200410007445A CN1560996A CN 1560996 A CN1560996 A CN 1560996A CN A2004100074459 A CNA2004100074459 A CN A2004100074459A CN 200410007445 A CN200410007445 A CN 200410007445A CN 1560996 A CN1560996 A CN 1560996A
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- 238000001514 detection method Methods 0.000 claims abstract description 11
- 238000007600 charging Methods 0.000 claims description 25
- 238000006243 chemical reaction Methods 0.000 claims description 9
- 230000008676 import Effects 0.000 claims 1
- 230000008030 elimination Effects 0.000 abstract description 2
- 238000003379 elimination reaction Methods 0.000 abstract description 2
- 230000009466 transformation Effects 0.000 abstract 2
- 239000013256 coordination polymer Substances 0.000 description 10
- 238000001914 filtration Methods 0.000 description 5
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- 101150110971 CIN7 gene Proteins 0.000 description 2
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Abstract
A short pulse eliminating circuit includes a signal transform detection circuit for detecting the digit transformation of a first input signal, a detection pulse is generated when digit transformation appears in the input signals, a control signal generation circuit providing a first and a second control signals, a reset and charge circuit containing a p-transistor, a n-transistor and a condenser, among which n is parallel to the condenser connecting to the earth, p is overlapped above n and the two control signals control the charger and reset of the condenser and a capacitor pulse detection and signal output circuit connected to the output end of the charge and reset circuit, when they are reset and charged and time is over a set value, it responds the input signal to generate an output of a short pulse elimination signal.
Description
Technical field
The present invention relates to a kind of circuit, particularly relate to a kind of utilize signal deteching circuit, control signal generation circuit and reset circuit combination and reach can eliminate the following short pulse of certain pulses width but allow to surpass the circuit that the above signal of certain pulses width is imported.
Background technology
Exporting/go into pad (I/O pad) generally speaking is the bridge that integrated circuit (IC) chip and other chip are linked up.Purely just as a buffer, as shown in Figure 1a.A is the input signal end, and Z then is an output.When A end input be a pulse, input to buffer, for example constitute by even number of inverters, input after postpone several how second after, output Z also should export the pulse of same widths.
Allow when exporting/going into pad generation filter function if add the low pass assembly, might produce capability error on the contrary.See also Fig. 1 b.Form the low-pass filtering assembly by two inverters and a capacitor C.Shown in Fig. 1 b, A is an input, V
CPBe capacitor C terminal voltage over the ground.Imagine above-mentioned low pass circuit and desire any pulse signal of filtering less than 20ns.Therefore, as pulse H1 of A input, and pulse duration is 15ns, and this pulse is by just charging to capacitor C behind the first inverter INV1, but V
CPVoltage do not have to surpass the start voltage V of the second inverter INV2
THSo V
Z=0, success filter first pulse H1.Afterwards, at V
A=0 o'clock, capacitor C was slowly discharged via the first inverter INV1.If capacitor C is not fully discharged and when having new pulse H2 to produce, the width of H2 pulse need just to be not limited to 20ns just can cross V
TH, but relevant with the residual charge of previous capacitor C, promptly relevant with L blanking time of H2 and H1.Therefore, as icon, if L such as icon are that then the back segment time of H2 (about 10ns) just may make V to 5ns
CP＞V
TH, and make output produce a not signal of filtering.
In view of this, the present invention will provide a circuit, and this circuit utilizes the feedback signal clock of resetting, and the bond oxide semi conductor transistor can drive the ability of big electric current, carries out fast charging and discharging, and keep away the problem that residual charge is held in power down.
Summary of the invention
The present invention discloses a kind of short pulse and eliminates circuit, comprises at least: a conversion of signals testing circuit in order to detect the digital translation of first input signal, produces one and detects pulse when input signal has digital translation; One control signal generation circuit provides one first control signal, and one second control signal; One resets and charging circuit, comprise a p transistor npn npn, a n transistor npn npn and an electric capacity, wherein n transistor npn npn and this electric capacity ground connection in parallel, the p transistor npn npn repeatedly is connected on the n transistor npn npn, and respectively by the charging and the replacement of this first control signal and this second control signal control capacitance; And a capacitor pulse detects and signal output apparatus, be connected in the output of this replacement and charging circuit, recharge, and the charging interval is when surpassing a set point when this replacement and charging circuit have electric capacity to be reset, respond this input signal, produce the output of a short pulse erasure signal.
Wherein above-mentioned control signal generation circuit comprises one first inverter, one second inverter, one the 3rd inverter, one first trigger and a CMOS transistor, first inverter wherein, second inverter, and the 3rd inverter is connected serially to the clock end of first trigger in regular turn, again by the input of the output feed-in CMOS transistor of first trigger, CMOS transistor is exported this first control signal, in addition, first trigger is that the positive edge with function of reset triggers D flip-flop, wherein its reset signal is provided by the output of first inverter, and its input signal is a power supply input signal.
Above-mentioned capacitor pulse detection comprises one the 4th inverter, one the 5th inverter and a positive edge with signal output apparatus and triggers second D flip-flop, connect the in regular turn clock end of this second D flip-flop of back feed-in of the 4th inverter and the 5th inverter, the input of this second D flip-flop is by this first input signal feed-in, and the input signal of short pulse has been eliminated in the output output of this this second D flip-flop.
The short pulse width that desire of the present invention is filtered is the size decision by the long L ratio of the wide W/ channel of the channel of p transistor npn npn, the heal p transistor npn npn of the little W/L ratio of then should selecting to heal big of the short pulse width of desire filtration.
Description of drawings
Preferred embodiment of the present invention will be done more detailed elaboration below in conjunction with the accompanying drawings.
The output of Fig. 1 a demonstration tradition goes into to be lined with as a buffer, there is no filter function.
Fig. 1 b shows that tradition output goes into pad when adding the low-pass filtering function, two glitches very close to the time, the late comer still may pass through, and causes the filter function mistake.
Fig. 2 shows the functional block diagram of eliminating circuit according to the short pulse of the present invention's design.
Fig. 3 shows the short pulse elimination circuit diagram according to the present invention's design.
Fig. 4 shows the oscillogram of eliminating each end points that circuit draws in response to input signal according to the short pulse of the present invention design.
The reference numeral explanation
| 100 conversion of signals testing circuits | 102 first CMOS transistors |
| 105 first delay circuits | 106 exclusive or |
| 150 control signal generation circuit | 151 first inverters |
| 152 second inverters | 153 second delay circuits |
| 154 the 3rd inverters | The d type flip flop of 155 tool edge-triggered and function of reset |
| 162 | 200 reset and charging circuit |
| 201pMOS | 202nMOS |
| 204 | 250 capacitor pulses detect and signal output apparatus |
| 251 the 4th inverters | 252 the 5th inverters |
| D type flip flop is triggered in 255 sidelines | High impulse H1, H2, H3 |
| Low pulse L1, L2 | 401,402,403,404 is the R1 signal pulse |
| 501,502,503,504 signal pulses for d type flip flop output | 701,702,703,704,705 for electric capacity is put, charging signals |
| 601,602,603,604 is the signal pulse of second CMOS transistor output | 905 output signal respective pulses |
| 804,805 pulses for the PU end |
Embodiment
In view of as described in background of invention, go into dig pass from output and send next signal to, be not sufficient to guarantee to be enough to filter the noise of high frequency with simple low pass circuit, because as long as two and/or above high-frequency noise signal are enough approaching, with regard to be enough to make originally desire the noise that filters since capacitor discharge not as good as the noise pulse that causes the back to be imported be able to by.Circuit provided by the present invention can solve the above problems.
Circuit of the present invention can be represented with the function square of Fig. 2, comprise: a conversion of signals testing circuit 100, a control signal generation circuit 150, are reset and are connected in regular turn with signal output apparatus 250 with charging circuit 200 and capacitor pulse detection.Wherein conversion of signals testing circuit 100 has an input receiving inputted signal IN, and an output 110, and when input signal IN changed, output 110 outputs detected pulse signal.Control signal generation circuit 150 responses detect pulse signal and produce two control signal CP and CK0.Reset with charging circuit 200 according to CP and CK0 signal and to electric capacity 204 quick charges or the discharge of Fig. 3.Capacitor pulse detects with signal output apparatus 250 response input signal IN and according to electric capacity 204 terminal voltages whether surpass predetermined current potential, if then respond input signal IN and export the signal OUT that a short pulse is eliminated.
Being when input signal IN changes according to circuit signal transition detection circuitry 100 of the present invention as shown in Figure 4, is that 1 detection pulse signal X01 is to control signal generation circuit 150 with regard to output level.Otherwise when input signal does not change, will output level be that 0 detection pulse signal X01 is to control signal generation circuit 150.
Please refer to Fig. 3, conversion of signals testing circuit 100 comprises: one first CMOS transistor, 102 inputs receive a pending input signal IN, the first input end of output while feed-in first delay circuit 105 and an exclusive or logic gate XOR 106.First delay circuit 105 can be made up of even number of inverters, in order to second input that the CMOS transistor 102 outputs delay t1 time of doing is imported XOR 106 again.Therefore, as shown in Figure 4 so long as input signal IN has any change, by electronegative potential (this and after with current potential 0 expression) to high potential (this and after represent with current potential 1), or, all will make the pulse of XOR output one t1 time width on output item X01 in the moment that changes by current potential 1 to 0.Note that the time t1 that first delay circuit 105 postpones gets final product with the variation that can detect signal or noise, generally is no more than 1-2ns.Because t1 is oversize will cause last pulse because of time-delay with carry out XOR when prepulse, and lead to errors.
Control signal generation circuit 150 comprises the d type flip flop 155 and one second CMOS transistor 162 of one first inverter 151, one second delay circuit 152, one second inverter, 153 1 3rd inverters 154, a tool edge-triggered and function of reset.Wherein, the output R1 of first inverter 151 is except importing second delay circuit 152 producing the t2 time delay, simultaneously also as the reset signal R1 of d type flip flop 155.Second delayer 152 is in order to prevent trigger 155 (race) phenomenon of competing.
153 of second inverters except output CK0 the 3rd inverter 154, also with a signal CK0 as the discharge control switch of resetting with charging circuit 200.The signal output signal CK1 of the 3rd inverter 154 inputs to the clock end CK of d type flip flop 155.Therefore, d type flip flop 155 clock control signals fall behind the t2 time at least than reset signal R1.The input D of d type flip flop 155 then connects the signal of a Vdd, and the signal CP0 of output Q is the input of feed-in second CMOS transistor 162 then.
Reset and charging circuit 200, comprise a pMOS 201, repeatedly connect a nMOS 202 and electric capacity 204.Wherein electric capacity 204 is in parallel with nMOS 202.PMOS 201 is by the output CP control switch of control signal generation circuit 150.And nMOS 202 is by second inverter, the 153 output CK0 controls of control signal generation circuit 150.
Capacitor pulse detects with signal output apparatus 250 to be made up of the 4th inverter 251, the 5th inverter 252 and sideline triggering d type flip flop 255.Connect the in regular turn clock end CK of this second D flip-flop 255 of back feed-in of the 4th inverter 251 and the 5th inverter 252, the input D of D flip-flop 255 receives an input signal IN, and the input signal OUT of short pulse has been eliminated in the output of the output of D flip-flop 255.
Therefore, please refer to Fig. 4, when input signal IN has change, for example, the T0 time is when importing a pulse H1, output signal INX2 after first CMOS transistor, 102 output signal INX1 and the time-delay will make XOR gate 106, in the pulse 401 and 402 pulses of two correspondences of X01 output, correspond respectively to the left border 301 and the right border 302 of H1 pulse.Signal CK1 postpones the t2 time again at second delay circuit 152.Therefore, the positive edge of tool function of reset trigger d type flip flop 155 will respective pulses 401 and the inversion signal R1 of 402 pulses and reset and when CK1 rectifies edge and rises, just make the CP0 of d type flip flop 155 export 1.Pulse 501 and 502 left border as shown in Figure 4.
Signal CP is pulse 501 and 502 signals after second CMOS transistor 162 is anti-phase 601 and 602.Circuit is as shown in Figure 3 worked as CP=1 as can be known, and during CK0=1, pMOS 201 closes, and electric capacity 204 will and discharge electric charge by nMOS 202 guiding ground connection.And when CP=0 and CK0=0, pMOS 201 opens and nMOS 202 closes, therefore will be to electric capacity 204 chargings.CP=1 and CK0=0, pMOS 201 and nMOS 202 close, and, keep previous state that is.Therefore, the terminal voltage PU0 of electric capacity 204, as shown in Figure 4, and in pulse 601, electric capacity 204 first sudden discharges 701, pulse 601 is charged after finishing, as the charged state 702 of Fig. 4, very fast again discharge when pulse 602 occurs.If pulse 601 and 602 time intervals of pulse hour, PU0 will be less than the start voltage V that promotes the 4th inverter 251
TH, therefore, capacitor pulse detects with signal output apparatus 250 outputs and keeps original state.
When the L1 width that follows the H1 input closely still falls short of, when H1 right border 302 and H2 left border 303 width are still less than the setting width as shown, its result will make X01 produce pulse 402, CP0 produces pulse 502, the charged state of electric capacity 204, as PU signal 703 because the L1 time too shortly fail charging and surpass VTH, so be discharged to 0 again very soon.
When the H2 width that follows the L1 input closely enough long (when surpassing default value), as shown in Figure 4, electric capacity 204 begins to enter charged state and just finishes after new pulse 604 occurs after pulse 603 finishes.Therefore, PU0 will surmount V between charge period
TH, and the PU end that capacitor pulse is detected with signal output apparatus 250 produces pulse 804, and make trigger 255 produce a clock, and when pulse 804 positive edge rise, export 0 or 1 signal identical with input signal IN.
Note that except input high impulse H1, H2 can make electric capacity 204 produce outside the charging signals 702,704, low pulse L1, L2 also can make electric capacity 204 produce charging signals 703,705.Circuit of the present invention is except the little high impulse of filter width, and the low pulse that width is little also can be regarded as noise and ignore.Therefore, if the wide inadequately PU end that just can not make of the charging signals 705 of the low pulse correspondence of L2 produces pulse, otherwise, when the low pulse duration of L2 is enough, will produce pulse 805, and end is because of the 804 outputs changes that produced, for example positive edge of output signal 905 respective pulses 804 and the positive edge of pulse 805 among Fig. 4.
Please note the channel width W of pMOS 201 and the speed that length L (W/L ratio) has determined charging.W/L is than higher, and expression can be written into the big electric current of healing, and charging can be faster.The size of electric capacity 204 need make PU0 voltage V at least
PU0＞V
THElectric capacity 204 sizes heal big chargeable electric charge just more greatly.The W/L of adjustment pMOS 201 when capacitance size can set the pulse size that desire is filtered.In addition.According to circuit design of the present invention, be the electric capacity of 0.05pF with the size of electric capacity 204, electric capacity can satisfy typical 1ns discharge demand at 0.5ns time discharge off when the W/L ratio of nMOS 202 was 4 μ m/0.22 μ m.
The preferred embodiment that the above only is not is in order to limit claim of the present invention; All other do not break away from the equivalence finished under the disclosed spirit and changes or modify, and all should be included in the application's the scope of claim.
Claims (8)
1. a short pulse is eliminated circuit, comprises at least:
One conversion of signals testing circuit when producing digital translation in order to detect an input signal, promptly produces one and detects pulse signal;
One control signal generation circuit, receive this detection pulse signal after, produce one first control signal, and one second control signal; And
One resets and charging circuit, comprise one first transistor npn npn, one second transistor npn npn and an electric capacity, wherein first type is opposite electrical transistor with second type, this second transistor npn npn and this electric capacity ground connection in parallel, this first transistor npn npn repeatedly is connected on this second transistor npn npn, and respectively by the charging and the replacement of this first control signal and this second control signal control capacitance; And
One capacitor pulse detects and signal output apparatus, be connected in the output of this replacement and charging circuit, recharge, and the charging interval is when surpassing a set point when this replacement and charging circuit have electric capacity to be reset, respond this input signal, produce the output of a short pulse erasure signal.
2. short pulse as claimed in claim 1 is eliminated circuit, wherein above-mentioned conversion of signals testing circuit comprises one first CMOS transistor, one first delayer and an XOR gate, import this input signal by this first CMOS transistor, one input of this first CMOS transistor output this first delayer of feed-in and this XOR gate, this first delayer is exported then another input of this XOR gate of feed-in.
3. short pulse as claimed in claim 1 is eliminated circuit, wherein above-mentioned conversion of signals testing circuit, this detection pulse signal of this generation when this input signal has the conversion of signals of 1-＞0 or 0-＞1.
4. short pulse as claimed in claim 1 is eliminated circuit, wherein above-mentioned control signal generation circuit comprises one first inverter, one second inverter, one the 3rd inverter, one first trigger and one second CMOS transistor, this first inverter wherein, this second inverter, and the 3rd inverter is connected serially to the clock end of this first trigger in regular turn, again by the input of this second CMOS transistor of output feed-in of this first trigger, this first control signal of the output of this second CMOS transistor, this first trigger is that the positive edge with function of reset triggers D flip-flop in addition, its reset signal is provided by the output of first inverter, and its input signal is a power supply input signal.
5. short pulse as claimed in claim 4 is eliminated circuit, also comprises one second delayer and is series between this first inverter and this second inverter, in order to prevent this trigger phenomenon of competing.
6. short pulse as claimed in claim 4 is eliminated circuit, and this first control signal of the output of the second wherein above-mentioned CMOS transistor, this second control signal are by this second inverter output.
7. short pulse as claimed in claim 1 is eliminated circuit, wherein above-mentioned capacitor pulse detection comprises one the 5th inverter, a hex inverter and a positive edge with signal output apparatus and triggers second D flip-flop, connect the in regular turn clock end of this second D flip-flop of back feed-in of the 5th inverter and this hex inverter, the input of this second D flip-flop is by this first input signal feed-in, and this output is exported this short pulse erasure signal.
8. short pulse as claimed in claim 1 is eliminated circuit, the short pulse width that wherein above-mentioned desire is filtered is the size decision by the long L ratio of the wide W/ channel of the channel of first transistor npn npn, heal first transistor npn npn of the W/L ratio that little then selection heals big of the short pulse width that desire is filtered.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410007445 CN1291548C (en) | 2004-03-04 | 2004-03-04 | Short pulse canel circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410007445 CN1291548C (en) | 2004-03-04 | 2004-03-04 | Short pulse canel circuit |
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| Publication Number | Publication Date |
|---|---|
| CN1560996A true CN1560996A (en) | 2005-01-05 |
| CN1291548C CN1291548C (en) | 2006-12-20 |
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| CN 200410007445 Expired - Lifetime CN1291548C (en) | 2004-03-04 | 2004-03-04 | Short pulse canel circuit |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103378823A (en) * | 2012-04-16 | 2013-10-30 | 円星科技股份有限公司 | Frequency generation method and system using pulse wave identification |
| CN104113328A (en) * | 2013-04-22 | 2014-10-22 | 上海华虹宏力半导体制造有限公司 | Phase comparator for phase locked loops |
| CN104283569A (en) * | 2013-07-04 | 2015-01-14 | 奇景光电股份有限公司 | Signal decoding circuit |
| CN104467754A (en) * | 2014-12-23 | 2015-03-25 | 安徽大学 | MOSFET driver with short pulse suppressing function |
| CN106936411A (en) * | 2015-12-30 | 2017-07-07 | 格科微电子（上海）有限公司 | The digital trigger of anti-noise jamming |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101441460B (en) * | 2008-12-30 | 2011-01-26 | 奇瑞汽车股份有限公司 | Control method for controlling circuit for controlling device switch |
-
2004
- 2004-03-04 CN CN 200410007445 patent/CN1291548C/en not_active Expired - Lifetime
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103378823A (en) * | 2012-04-16 | 2013-10-30 | 円星科技股份有限公司 | Frequency generation method and system using pulse wave identification |
| CN103378823B (en) * | 2012-04-16 | 2016-08-03 | 円星科技股份有限公司 | Frequency generation method and system using pulse wave identification |
| CN104113328A (en) * | 2013-04-22 | 2014-10-22 | 上海华虹宏力半导体制造有限公司 | Phase comparator for phase locked loops |
| CN104113328B (en) * | 2013-04-22 | 2017-02-15 | 上海华虹宏力半导体制造有限公司 | Phase comparator for phase locked loops |
| CN104283569A (en) * | 2013-07-04 | 2015-01-14 | 奇景光电股份有限公司 | Signal decoding circuit |
| CN104467754A (en) * | 2014-12-23 | 2015-03-25 | 安徽大学 | MOSFET driver with short pulse suppressing function |
| CN106936411A (en) * | 2015-12-30 | 2017-07-07 | 格科微电子（上海）有限公司 | The digital trigger of anti-noise jamming |
| CN106936411B (en) * | 2015-12-30 | 2021-07-27 | 格科微电子（上海）有限公司 | Digital trigger with noise interference resistance |
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| CN1291548C (en) | 2006-12-20 |
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Granted publication date: 20061220 |