CN101572261A - 芯片封装结构 - Google Patents

芯片封装结构 Download PDF

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CN101572261A
CN101572261A CNA2008103013493A CN200810301349A CN101572261A CN 101572261 A CN101572261 A CN 101572261A CN A2008103013493 A CNA2008103013493 A CN A2008103013493A CN 200810301349 A CN200810301349 A CN 200810301349A CN 101572261 A CN101572261 A CN 101572261A
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chip
circuit board
substrate
packaging structure
electrically connected
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吴英政
周得钧
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Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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Priority to CNA2008103013493A priority Critical patent/CN101572261A/zh
Priority to US12/192,083 priority patent/US20090267206A1/en
Publication of CN101572261A publication Critical patent/CN101572261A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H05K3/323—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Combinations Of Printed Boards (AREA)
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Abstract

一种芯片封装结构，其包括多个封装单元及一个电路板，每个封装单元包括一个基板、一个芯片及异方向性导电层。基板具有一个面向电路板的第一表面和一个背向电路板的第二表面。电路板上具有多个焊点。在第一表面和第二表面上具有多个焊垫，芯片通过异方向性导电层电连接于基板的第一表面上。芯片的面积小于基板的面积。每个封装单元的基板的第一表面通过焊球与相邻的封装单元的基板的第二表面的焊垫纵向电连接，最接近电路板的封装单元的基板的第一表面通过焊球与电路板的焊点电连接。上述芯片封装结构，将多个芯片封装单元纵向堆叠于电路板上，提高集成度的同时不会导致电路板面积增大，有利于电子装置的小型化。

Description

芯片封装结构
技术领域
本发明涉及一种芯片封装技术，尤其是涉及一种芯片封装结构。
背景技术
请参阅图1，为现有芯片封装结构10，该芯片封装结构10包括基板11、芯片12、多条导线13，粘着层14，封胶体15。所述芯片12具有多个电极接点121，所述基板11上有至少两个不连续的粘着层14，基板11与电极接点121之间以导线13电性连接。所述基板11位于所述不连续的粘着层14上，所述封胶体15将所述基板11与所述导线13密封起来。然而该芯片封装结构10比较复杂，整个封装结构比较厚，且目前采用的集成方式是将多个该芯片封装结构10在集成到电路板上，导致电路板面积增大，这样不利于电子装置的小型化。
发明内容
有鉴于此，有必要提供一种可以实现小型化的芯片封装结构。
一种芯片封装结构，其包括多个封装单元及一个电路板，所述每个封装单元包括一个基板、一个芯片及异方向性导电层。所述基板具有一个面向所述电路板的第一表面和一个背向所述电路板的第二表面。所述电路板上具有多个焊点。在所述第一表面和第二表面上具有多个焊垫，所述芯片通过异方向性导电层电连接于所述基板的第一表面上。所述芯片的面积小于所述基板的面积。所述每个封装单元的基板的第一表面通过焊球与相邻的所述封装单元的基板的第二表面的焊垫纵向电连接，最接近所述电路板的封装单元的基板的第一表面通过焊球与所述电路板的焊点电连接。
上述芯片封装结构，通过采用异方性导电层直接将芯片电性连接于基板上，结构简单，且将多个芯片封装单元纵向堆叠于电路板上，提高集成度的同时不会导致电路板面积增大，有利于电子装置的小型化。
附图说明
图1为现有芯片封装结构的示意图。
图2为本发明提供的芯片封装结构的示意图。
具体实施方式
如图2所示，其为本发明提供的一种芯片封装结构100的示意图。该芯片封装结构100包括多个封装单元110及一个电路板120。
所述电路板120上具有多个焊点121，所述每个封装单元110包括一个基板111、一个芯片112及异方向性导电层113，该异方向性导电层113可以为异方向性导电胶或者异方向性导电膜。
所述基板111具有一个面向所述电路板120的第一表面115和一个背向所述电路板120的第二表面116，所述基板111的第一表面115和第二表面116上均具有多个焊垫114，所述基板111可为印刷电路板，可挠性电路板，陶瓷电路板等。
所述芯片112有导电凸块117，所述基板111是通过该导电凸块117与芯片112进行电连接。所述芯片112也可以直接通过异方向性导电层113电连接于所述基板111的第一表面115上，这样有利于提高整个芯片封装结构100的传输速率。所述每个封装单元110的基板111的第一表面115通过焊球101与相邻的所述封装单元110的基板111的第二表面116的焊垫114纵向电连接。所述芯片112的面积小于所述基板111的面积，这样有利于焊接且不占额外空间，最接近所述电路板120的封装单元110的基板111的第一表面115通过焊球101与所述电路板120的焊点121电连接。其中，所述焊球101可以为无铅焊球或者铅锡焊球。
上述芯片封装结构，通过采用异方性导电层直接将芯片电性连接于基板上，结构简单，且将多个芯片封装单元纵向堆叠于电路板上，提高集成度的同时不会导致电路板面积增大，有利于电子装置的小型化。
可以理解的是，对于本领域的普通技术人员来说，可以根据本发明的技术构思做出其它各种相应的改变与变形，而所有这些改变与变形都应属于本发明权利要求的保护范围。

Claims (7)

1.一种芯片封装结构，其包括多个封装单元及一个电路板，所述每个封装单元包括一个基板及一个芯片，所述电路板上具有多个焊点，其特征在于：所述每个封装单元还包括异方向性导电层，所述基板具有一个面向所述电路板的第一表面和一个背向所述电路板的第二表面，所述基板的第一表面和第二表面具有多个焊垫，所述芯片通过异方向性导电层电连接于所述基板的第一表面上，所述芯片的面积小于所述基板的面积，所述每个封装单元的基板的第一表面通过焊球与相邻的所述封装单元的基板的第二表面的焊垫纵向电连接，最接近所述电路板的封装单元的基板的第一表面通过焊球与所述电路板的焊点电连接。
2.如权利要求1所述的芯片封装结构，其特征在于：所述异方向性导电层为异方性导电胶。
3.如权利要求1所述的芯片封装结构，其特征在于：所述异方向性导电层为异方性导电膜。
4.如权利要求1所述的芯片封装结构，其特征在于：所述焊球为无铅焊球。
5.如权利要求1所述的芯片封装结构，其特征在于：所述焊球为铅锡焊球。
6.如权利要求1所述的芯片封装结构，其特征在于：所述芯片具有导电凸块，所述基板以所述导电凸块与芯片进行电连接。
7.如权利要求1所述的芯片封装结构，其特征在于：所述基板的材料可为印刷电路板、可挠性电路板及陶瓷电路板。
CNA2008103013493A 2008-04-28 2008-04-28 芯片封装结构 Pending CN101572261A (zh)

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US12/192,083 US20090267206A1 (en) 2008-04-28 2008-08-14 Stacked semiconductor package

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102064162A (zh) * 2010-11-09 2011-05-18 日月光半导体制造股份有限公司 堆叠式封装结构、其封装结构及封装结构的制造方法
CN113707621A (zh) * 2021-10-29 2021-11-26 甬矽电子(宁波)股份有限公司 半导体封装结构和半导体封装结构的制备方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170056391A (ko) * 2015-11-13 2017-05-23 삼성전기주식회사 프론트 엔드 모듈

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000208698A (ja) * 1999-01-18 2000-07-28 Toshiba Corp 半導体装置
TWI237354B (en) * 2002-01-31 2005-08-01 Advanced Semiconductor Eng Stacked package structure
KR100669830B1 (ko) * 2004-11-16 2007-04-16 삼성전자주식회사 이방성 도전막을 이용한 적층 패키지
KR100738653B1 (ko) * 2005-09-02 2007-07-11 한국과학기술원 이미지 센서 모듈용 웨이퍼 레벨 칩 사이즈 패키지 및 이의제조방법
JP2008166440A (ja) * 2006-12-27 2008-07-17 Spansion Llc 半導体装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102064162A (zh) * 2010-11-09 2011-05-18 日月光半导体制造股份有限公司 堆叠式封装结构、其封装结构及封装结构的制造方法
CN102064162B (zh) * 2010-11-09 2013-01-02 日月光半导体制造股份有限公司 堆叠式封装结构、其封装结构及封装结构的制造方法
CN113707621A (zh) * 2021-10-29 2021-11-26 甬矽电子(宁波)股份有限公司 半导体封装结构和半导体封装结构的制备方法

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