CN101520725B - 具有数字功率调节的微处理器 - Google Patents
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Abstract
本发明提供了一个基于数字的机制,用于调整处理器中的功耗。该处理器包含一个或者多个功能单元和数字调节器,该数字调节器监控该处理器的功能单元的活动状态,以估计处理器的功耗。数字调节器的一个实施例包含一个或者多个选通单元、监控电路(320)、以及调节电路(330)。每一个选通单元控制传送到该处理器的一个功能单元的功率的传送,并且提供指示它的相关功能单元的活动状态的信号。该监控电路从所述信号中确定估计的功耗水平,并将估计的功耗和阈值功率水平相比较。如果估计的功耗超过该阈值功率水平,则该调节电路调整该处理器中的指令流。
Description
本申请是申请日为2000年11月21日,申请号为00818992.7,发明名称为“具有数字功率调节的微处理器”的中国专利申请的分案申请。
技术领域
本发明涉及微处理器,而且尤其涉及用于控制在微处理器中的功耗的机制。
背景技术
现代的处理器包含广大的执行资源以支持多条指令的并行处理。处理器一般包含一个或多个整数、浮点、转移和存储器执行单元以分别实现整数、浮点、转移和加载/存储指令。此外,整数和浮点单元一般包含寄存器堆以相对接近于该处理器核心保持数据。向处理器提供广大的执行资源的一个缺点是要求有大量的功率来运行它们。取决于执行单元的大小和它们实现的功能,不同的执行单元可以消耗或多或少的功率,但是把这么多逻辑封装到一个相对小的处理芯片上的实际结果是将产生重要功率耗散问题的可能性。
几乎没有程序需要一个处理器的执行资源的全部范围持续很长的时间间隔。运行一个程序耗散的功率取决于它的组件指令的属性和它们被并行执行的可能性。程序一般包含各种指令类型,但是很少有足够多的正确类型的指令可以用来使得处理器的全部执行资源忙碌相当长的时间周期。为此,大多数处理器使用时钟选通机制,以便当执行资源不被使用时切断传送到该执行资源的时钟,由此减小功率。此外,当指令进入和退出由一个执行资源的不同组件服务的流水线阶段时,该组件能够被开和关。因此,普通的程序可以耗散相对可管理的功率水平。
某些程序确实将处理器的许多执行资源激活相对长的时间间隔,因此耗散比普通程序多很多的功率。除非提供了一个机制来限制处理器的功耗,否则处理器通常被设计以处理消耗最高功率的程序。这可能需要以低于它的最高性能水平为所有程序运行该处理器,而与运行普通程序所要求的功率无关。
功率调节是一个已经提出用来处理由高性能处理器产生的功耗问题的策略。当一个处理器的功耗过高时,功率调节降低该处理器的性能。这可以通过临时减小该处理器执行指令的速率直到功耗降低到安全水平为止来进行。功率调节允许处理器被设计成用于普通程序运行所用的功率水平。当运行一个资源消耗较多的程序时,处理器减小它的指令执行速率以保持它的功耗在一个已确定的限度内。
提出的功率调节机制依赖模拟参数来监控处理器耗散的功率。例如,一个热量调节机制监控处理器芯片的温度,并且当温度超过阈值时减小处理器的执行速度。已经提出其它的调节方案来监控由处理器消耗的电流或者在开关调节器中的脉冲宽度调制器的占空比。
这些功率调节机制具有许多缺点。它们将附加的模拟电路引入到一个主要是数字的环境,即处理器中。它们易于随处理器的环境(温度、电压、组成)中的变化而改变。它们可以在处理器的功率水平中产生低频率的变化。它们不直接限制由该处理器消耗的功率,而且它们不是确定性的。这就是说,不能在一个时钟接一个时钟的基础上预测它们的行为。
本发明解决了可用功率调节机制的这些及其它不足。
发明内容
本发明提供了一种数字调节器来控制微处理器的功耗。
根据本发明,一种处理器包含一个或多个功能单元和数字调节器。该数字调节器监控处理器的功能单元的活动状态以估计该处理器的功耗。
根据本发明的第一方面,提供一种处理器,包含:
形成指令执行流水线的功能单元;
选通电路,控制到该功能单元的功率传送,并且提供一个指示传送给该功能单元的功率水平的信号;
一个监控电路,把指示的功率水平与一个阈值功率水平进行比较;以及
一个调节电路,如果指示的功率水平超过阈值功率水平,则调整所述处理器中的指令流。
根据本发明的第二方面,提供了一种控制在一个处理器中的功率消耗的方法,包含:
收集来自于在该处理器中的选通电路的功率信号,该功率信号指示当前传送到与选通电路相关联的多个功能单元的功率水平;
根据收集的功率信号调整估计的功率消耗水平;
将该估计的功率消耗水平与一个阈值功率消耗水平相比较;以及
当该估计的功率消耗水平超过阈值功率消耗水平时,调整处理器的一个指令执行速率。
根据本发明的第三方面,提供了一种处理器,包含:
形成指令执行流水线的一个或多个功能单元;以及
一个数字调节器,监控该一个或多个功能单元的活动状态以估计用于该处理器的一个功率消耗水平,其中该数字调节器包含:
一个或多个选通单元,其中每一个选通单元控制到一个相关功能单元的功率传送,并且指示用于该相关功能单元的一个活动状态;一个监控电路,从指示的一个或多个功能单元的活动状态中确定处理器功率消耗水平的估计,其中所述估计将与预定的阈值进行比较;以及
一个调节电路,在所述估计超过所述预定阈值时,调整所述处理器中的指令流。
对于本发明的一个实施例,该数字调节器包含一个或多个选通单元、一个监控电路、和一个调节电路。每一个选通单元控制传送到该处理器一个功能单元的功率传送,并且提供一个信号来指示它的相关功能单元的活动状态。该监控电路从信号中确定该处理器的一个估计的功率消耗水平,并且将估计的功率消耗与一个阈值功率水平相比较。如果该估计的功率消耗水平超过该阈值功率水平,则调节电路调整在处理器中的指令流。
附图说明
参考以下附图可以理解本发明,其中类似的单元用类似的数字指示。提供这些附图以说明本发明中的选定实施例并且不用于限制本发明的范围。
图1是可以在其上实现本发明的一个计算机系统的一个实施例的框图。
图2是根据本发明,实现了一个数字功率调节器的一个处理器的一个实施例的框图。
图3是由图2中的处理器实现的数字功率调节器的一个实施例的框图。
图4是一个表示图3中的调节电路的一个实施例的示意图。
图5是一个流程图,表示了一种根据本发明、用于调整处理器的功耗的方法。
图6A和6B是表示根据本发明实现数字调节器的多个执行核心处理器的实施例的框图。
具体实施方式
下面的讨论阐述了许多具体的细节以便提供对本发明的彻底理解。然而,本领域普通技术人员受益于这个公开,将会理解:可以实践本发明而不需要这些具体细节。此外,各种众所周知的方法、过程、组件和电路没有被详细描述,以便把注意力集中在本发明的特征上。
本发明提供了一种机制,用于通过监控一个处理器的功能单元响应于一个指令序列的活动来控制该处理器的功率耗散。例如哪些功能单元由当前在进行中的指令激活的活动,可以由指示相应功能单元是否被打开或者关闭的二进制信号表示。处理器消耗的功率的估计值是通过对与当前“打开”的每一个功能单元相关联的功率加权求和来提供的。用于一个功能单元的功率加权表示当该功能单元被激活时它消耗的功率量。如果估计的功率超过阈值水平,则一个调节机制调整通过该处理器的指令流以减少该功能单元的活动。
用于每一个功能单元的功率加权可以通过一个校准过程来确定。例如,作为设计过程的一部分,该数字调节器可以被校准一次,或者它可以自我校准。在后面的情况中,该数字调节器可以使用当前的监控电路和一个校准算法定期地调整用于每一功能单元的功率加权。
对于该发明的一个实施例,一个选通单元与每一功能单元相关联,以响应于当前在进行中的指令,控制到该功能单元的功率传送。一个流水线控制电路向每一个选通单元指示它的相关功能单元的开/关状态。来自每一个选通单元的一个信号向一个监控电路指示它的相关功能单元的开/关状态。监控电路依据所指示的状态,在该处理器的当前功耗的估计中包含或者忽略相应的功率加权。作为选择,当功能单元是“开”时,每一个选通单元信号可以把它的相关功能单元的功率加权传送到该监控电路。本发明的其它实施例可以使用其它机制用于指示在该估计的功率中要被考虑的功率加权。
该监控电路计算用于活动的功能单元的功率加权的总和,并且把它们和一个阈值进行比较,以逐时钟地提供该处理器的功耗的估计值。对于该数字调节器的一个实施例来说,在多个时钟周期上累加这些估计值以提供一个累加功率值,其平滑了在该处理器的功耗中逐时钟的变化。依据累加功率值,一个调节电路调整指令被处理的速率。例如,该调节电路可以注入“气泡”到该处理器的指令执行流水线中以降低性能,或者它可以减小该处理器的时钟操作的频率。
所公开的机制因此依赖于在该处理器的逻辑中的数字事件(活动状态)来估计功耗,并且直接通过指令被处理的速率来调整这些事件的速率。这提供了一个用于控制处理器的功耗的快速、直接、和确定性的机制,而且它这样做时不会把模拟电路引入到处理器中。
图1是在其中可以实现本发明的一个计算机系统100的一个实施例的一个框图。计算机系统100包含一个或多个处理器110、一个主存储器140、一个非易失性存储器150、各种外围设备160、和系统逻辑170。系统逻辑170控制在一个或多个处理器110、主存储器140、非易失性存储器150和外围设备160当中的数据传输。提供了计算机系统100来说明本发明的各种特征。显示的特定配置不是实现本发明所必需的。
处理器110包含多个功能单元124,这些功能单元124形成一个指令执行流水线120。指令从主存储器140和非易失性存储器150提供到处理器110。一个数字调节器130响应于处理的指令监控在各种功能单元124中的功耗,并且相应地调整通过流水线120的指令流动。
当一个指令沿着流水线120向下进行时,它引导各种功能单元124执行一个或多个操作,这些操作合起来实现该指令。例如,一个浮点乘法累加指令(FMAC)可以导致在指示的资源中发生下列操作:一个浮点寄存器堆读出三个操作数;一个FMAC执行单元将两个操作数相乘,并且添加乘积到第三个操作;一个例外单元检查该乘积并且为错误进行求和;以及如果没有检测到错误的话,则一个收回单元把该结果写到浮点寄存器堆中。取决于特定的处理器实现,这些资源或者它们的组件可以被组合到一个或多个功能单元中,当该指令沿着流水线向下进行时打开和关闭这些功能单元。当每一个功能单元由指令激活时,它消耗一定量的功率。
对于本发明的一个实施例,由一个功能单元124消耗的功率由一个相关的功率加权表示。当一个功能单元由一条指令激活时,数字调节器130检测它的活动状态,并且添加它的相关功率加权到该处理器总功耗的估计值中。数字调节器130在一个选定的间隔上实现这些操作,产生由当前正在执行的指令序列消耗的功率的一个估计值,并且如果估计的功耗超过一个指定的阈值水平的话,则调整通过流水线120的指令流。
图2更详细地表示了处理器110的一个实施例。对于处理器110的公开实施例来说,流水线120被分别表示为取出(FET)、扩展(EXP)、登记(REG)、执行(EXE)、检测(DET)、以及收回(RET)阶段,而且指示对应于每一个阶段的执行资源。本发明不需要把处理器110划分成一个特定流水线阶段集合。例如,一个公开的阶段可以被再分成两个或更多阶段,以解决定时发布或者便于更高的处理器时钟频率。作为选择,两个或更多阶段可以组合成单个阶段。其它实施例可以包含用于无序处理指令的硬件。公开的流水线仅仅提供了在实现本发明的一个处理器中可以如何划分操作的一个示例。
流水线120的前端包含取出单元210和发布单元220,其提供指令到在流水线120的后端中的执行单元用于执行。取出单元210直接从存储器140中或者通过一个局部高速缓存(没有显示)获取指令,并且把取出的指令提供到发布单元220。发布单元220将该指令解码,并且把它们发布到在流水线120后端中的执行资源。
在这个讨论中,一般地使用术语“指令”来指代指令、宏指令、指令束或者许多用于对处理器操作编码的其它机制中的任一种。例如,该解码操作可以将一个宏指令转换成一个或多个微操作(μops)、把一个指令束分解成一个或多个指令节、或者获取一个与一个指令相关联的微码序列。
流水线120的后端包含寄存器单元230、执行单元250、例外单元260和收回单元270。寄存器单元230包含一个寄存器重命名单元和各种寄存器堆(没有显示),以分别标识在指令中指定的寄存器以及从标识的寄存器中访问数据。执行单元250包含一个或多个转移执行单元(BRU)252、整数执行单元(IEU)254、加载/存储单元(LSU)256、以及浮点执行单元(FPU)258,以处理转移、整数、加载/存储、和浮点指令。例外单元260检查由执行单元250产生的结果,并且如果遇到异常条件,则调整控制流。如果没有检测到异常条件,则收回单元270用该结果更新处理器110的体系结构状态。
由不同的指令激活的功能单元对应于被指示用于流水线120的执行资源的不同组合和子集。数字调节器130监控这些功能单元的活动状态,并且相应地调整指令通过流水线120处理的速率。例如,一个功能单元可以包含一个浮点寄存器(在寄存器单元230中),而且FPU 258可以具有在两个或更多功能单元中的组件。通常,一个功能单元包含被一起激活和去激活的各种执行资源(寄存器堆、执行单元、跟踪逻辑)。本发明不取决于在图2中显示的功能单元和执行资源之间的详细映射。
图3是一个表示数字调节器130的一个实施例以及它与流水线120的功能单元124相互作用的框图。数字调节器130的公开实施例包含选通单元310(1)-310(n)(一般称为选通单元130)、一个监控电路320、和一个调节电路330。每一个选通单元310与在流水线120中的一个功能单元124相关联,以控制到该功能单元的功率传送。例如,依据功能单元124的服务是否为实现当前在该功能单元在其中进行操作的流水线阶段中的一条指令所必需,选通单元310可以是将时钟信号与功能单元124耦合或者去耦合的时钟选通电路。还在图3中显示了一个流水线控制电路350,其向选通单元310指示对于当前执行的指令,哪些功能单元是活动的。
对于数字调节器130的公开实施例,每一个选通单元130提供一个信号到监控电路320,以指示功率是否正被传送给功能单元124。例如,信号可以是功能单元124的活动状态,当功能单元124被“打开”时,认定该信号。当该信号被认定时,即当选通单元130提供功率到功能单元124时,用于该功能单元的功率加权被添加到用于处理器110的估计的功耗中。当该信号没有被认定时,即当选通单元130切断到功能单元124的功率时,相关的功率加权没有被加到估计的功耗中。一个典型的处理器可以包含10-20个选通单元310以控制到10-20个功能单元124的功率传送。
监控电路320从选通单元130收集信号,并且从收集的信号中确定用于处理器110的当前估计的功耗水平。对于数字调节器130的公开实施例,监控电路320包含加权单元314(1)-314(n)(一般称为加权单元314)、加法器324、饱和电路326、以及累加器328。对于本发明的一个实施例,每一个加权单元314通过一个相应的选通单元310与功能单元124中的一个相关联。当来自它的选通单元310的活动状态信号被认定了时,加权单元314提供一个功率水平到加法器324。当该活动状态信号没有被认定时,加权单元314输出零。
加法器324计算由加权单元134指示的功率加权总和,并且从该总和中减去阈值水平。加法器324的输出通过饱和电路326转发到累加器328。包含饱和电路326以在由加法器324转发的值溢出时防止绕回。累加器328提供该转发的值到调节电路330,还提供一份副本回到加法器324以依据处理器的后续活动状态进行更新。
以选定的间隔,累加器328的内容(“累加的功率”)被提供到调节电路330。如果累加的功率是正,例如在指定间隔内累加功耗估计值超过阈值功率水平,则调节电路330的一个实施例减少通过流水线120的指令流动。调节电路330发信号通知取出单元210,以注入“气泡”到被提供给流水线120后端的指令流中。实际上,当为指定间隔估计的功耗水平超过阈值水平时,调节电路330调整处理器时钟的占空比。
表1:说明了用于其中指定间隔是128个时钟周期的情况的一组占空比调整。
累加的功率 | 占空比 |
X<0 | 128/128 |
0<=X<1 | 127/128 |
1<=X<2 | 126/128 |
2<=X<3 | 125/128 |
3<=X<4 | 124/128 |
... | ... |
125<=X<126 | 2/128 |
126<=X<127 | 1/128 |
127<=X | 0/128 |
对于由表1说明的实施例,功率加权可以是8-16位的、与当功能单元被激活时由它消耗的功率成比例的定点数。X的上8位可以用来调整该处理器时钟的占空比。这些位变化更慢一些,以衰减由调节电路330指示的指令流变化。对于上述示例,其中采样间隔是128个时钟周期,数字调节器130提供了128个级别的调节。这些级别提供了精细调整的调节控制,其与所估计的功耗超过阈值功耗的量成比例。较佳地,调节电路350在采样间隔内分布由估计的功耗指示的开/关阶段。该分布可以是均匀的、可以是随机的、或者它可以取决于某些其它模式。在下面将更详细地讨论一种这样的分布。
图4是调节电路330的一个实施例的示意表示。调节电路330的公开实施例包含存储器设备410、控制单元420、和计数器430。还显示了在其中存储累加的功率的累加器338的一个寄存器440。存储器设备410可以是,例如,一个只读存储器(ROM),响应于来自计数器420的计时指示和来自累加器328的累加的功率水平,通过控制单元420访问该存储器设备的表项。
对于调节电路330的公开实施例,计数器430是一个对128求模的计数器。计数器430的输出在连续的时钟周期上从0-127递增在控制单元420中的列索引,并且当到达127时回到0。类似地,累加器328的输出依据累加功率的当前值调整在控制单元420中的行索引。对于该公开的实施例,当分别X<=0,72,和124时,行索引是0,71,和123。控制单元420使用这些索引从存储器设备410中读出相应的表项。表项的值指示气泡是否应当被注入到处理器110的指令执行流水线中。例如,当输出是0时,气泡被注入,而当输出是1时,没有气泡被注入。
对于存储器设备410的一个实施例,每一行都用不同数量的1和0进行填充,0的数目与映射到该行的X值成比例。例如,行0可以包含全部是1,以便当累加的功率水平(X)不超过零时,即当运行的功率估计值不超过阈值水平时,没有气泡被注入到该指令执行流水线中。在功率谱的另一端,行127可以不包含1,以便只要累加的功率水平超过一个规定量就在每一个时钟周期上注入气泡到该指令执行流水线中。对于公开的示例,这个量由饱和电路328确定为127,即X=>127。在行0和行127之间的行可以用与X值成比例的0填充。例如,行67包含分布在它的不同列中的68个0,行111包含分布在它的各列中的112个0,而且行17包含分布在它的各列中的18个0。对于本发明的一个实施例,0可以以一种随机方式分布在它们指定行的各列中。
数字调节器130的公开实施例包含一个反馈回路。调节量取决于功能单元的活动状态,而活动状态反过来受调节量的影响。累加器328执行在时间上的积分,其引入一个90度的滞后相移到这个反馈回路中。为了稳定性目的,在该反馈回路内最小化其它延迟,即相移是重要的。用于该数字反馈回路的稳定性标准将很可能取决于在一个间隔期间要多么显著地调整该处理器的功耗,该间隔对应于穿越该指令执行流水线需要的时钟周期数目(流水线间隔)。例如,功率加权应被选得在流水线间隔期间确保相对小的功耗变化。
数字调节器130的响应时间由它的反馈回路控制。因为数字调节器响应于在该逻辑中的离散信号而不是由处理器组件的集体行为确定的宏观现象(温度、电流)进行操作,所以它的响应时间在微秒数量级。基于热量的调节机制的响应时间在秒数量级。数字调节器130不能控制持续时间比这个响应时间还要短的功耗中的峰值。为了最小化由例如注入气泡表示的性能损失,数字调节器130和由该功率传送系统允许的响应一样慢。这意味着该功率传送系统应当能在比响应时间还要短的间隔,处理在该处理器的功耗中、高于该阈值水平的峰值。对于这些峰值,能量可以从该处理器的电源电容器提供。
数字调节器130对处理器的功耗上的控制程度越大,它将会越有效。在数字调节器130实现了覆盖该处理器功能单元大部分的选通机制的地方,数字调节器130最有效。大范围的选通控制意味着:当超过阈值水平时,数字调节器130能够快速和显著地调整功耗的水平。类似地,在功能单元上提供更精细的控制增加了数字调节器130的效率。例如,把处理器的执行资源分成更多数量的功能单元124,并且提供附加的选通单元来控制这些功能单元,向调节器130提供了对处理器功耗更大的控制。
图5是一个流程图,表示一种根据本发明、用于调节处理器中的功率的方法500。方法500首先在510确定在该处理器中哪些功能单元是活动的。例如,可以由来自时钟选通电路的信号来指示功能单元的状态(活动/不活动),其中该时钟选通电路提供功率到功能单元。例如,如果该选通电路提供功率到该功能单元(活动状态),则它可以认定该信号,而且如果它当前没有提供功率到该功能单元(不活动状态),则它可以取消该信号。
一旦在510已经确定了活动的功能单元,就在520为该处理器估计功率水平。这可以通过将功率加权与由每一选通单元提供的信号相关联、并且向该估计的功率水平递增与每一个认定的信号相关联的功率加权来完成。与取消的信号相关联的加权功率不对当前估计的功率水平有所贡献。
在530把当前估计的功率水平与阈值功率水平相比较。阈值功率水平表示,例如,在其以上处理器不应被操作一段延长时间的一个功率水平。对于一个实施例,从当前估计的功率水平中减去该阈值,并且把结果加到处理器的相对功率水平的连续估计值(runningestimate),即累加的功率中。如果累加的功率是正的(EPL>阈值),则在540调整该指令吞吐量。如果累加的功率是负的(EPL<阈值),则不调整该指令吞吐量。
可以通过许多机制减小处理器的指令吞吐量。对于方法500的一个实施例,可以把气泡注入到指令执行流水线中,以减少处理器的功能单元是活动的时钟周期部分。例如,可以通过仅仅在选定的处理器时钟周期上触发该发布单元以发布指令,来引入气泡。对于本发明的另一个实施例,可以减小处理器时钟操作的频率。
本发明的一个优点是依据在该流水线的功能单元中的活动水平调整处理器流水线的执行资源。不同于基于热量或者电流估计功耗的技术,由该数字调节器监控的功能单元活动是在该处理器内各个流水线的一个特征。在分配活动和功耗到特定单元中的结果特异性在在单个处理器芯片上实现了多个执行核心的处理器中尤其有用。这里,“执行核心”涉及与一个完整处理器相关联的执行资源,以便多执行核心的处理器有效地在单个芯片上实现多处理器。只要总功耗不超过阈值水平,本发明的数字调节器允许正处理能耗大的代码段的执行核心有效地从另一个(或多个)执行核心借用功率。做为选择,它允许每一个执行核心依据在它的指令执行流水线中的活动来被调节。
图6A是一个在其中实现了本发明的多执行核心处理器610的一个实施例的块级框图。处理器610包含执行核心620(a)-620(n)(一般称为(一个或多个)执行核心630)。每一执行核心620都包含形成执行流水线640的功能单元630。共享的数字调节器650监控和调整在所有流水线640的功能单元630中的活动。只要没有超过总功率阈值,处理器110的这个实施例允许每一个执行核心620从剩余的执行核心借用功率。
图6B是一个在其中实现了本发明的多执行核心处理器660的另一个实施例的块级框图。处理器660包含执行核心620(a)-620(n)(一般称为(一个或多个)执行核心630),其中每一个都包含形成执行流水线640的功能单元630。每一个执行核心630还包含数字调节器650,以监控和调整在它的功能单元630中的活动。处理器110的这个实施例允许每一个执行核心620由它的相关数字调节器630独立地进行调节。
因此,这里提供了依据处理器的功能单元的活动状态控制在处理器中的功耗的数字调节器。在指令执行期间监控活动状态,并且依据从活动状态中估计的功耗水平调整该执行速率。可以通过响应于估计的功耗把“气泡”或者NOP注入到该指令执行流中来控制功耗。
对于本发明的一个实施例,把功率加权分配给每一个功能单元,并且通过对每一个活动的功能单元的功率加权求和来估计处理器的功耗。当估计的功耗超过阈值时,数字调节器减小处理器执行指令的速率。可以通过在处理器设计或者测试阶段期间的校准过程来确定各种功能单元的功率加权。数字调节器还可以包含电路来实现自校准过程。
已经提供了公开的实施例来说明本发明的各种特征。在处理器设计技术领域的技术人员,受益于这个公开,将会意识到:对公开实施例的变化和修改依然属于所附权利要求的精神和范围之内。
Claims (9)
1.一种处理器,包含:
形成指令执行流水线的多个功能单元,其中包括至少一个执行单元;
数字调节器,所述数字调节器包括:
至少一个时钟选通电路,用于根据正由所述执行单元执行的第一数目的指令使至少一个时钟信号与至少一个执行单元耦合或去耦合;
监控电路,从所述至少一个时钟选通电路收集包括指示功率是否正被传送给所述执行单元的信号的信号,并且从所收集的信号来确定估计的功耗水平;
数字调节电路,用于如果所述估计的功耗水平超过阈值功率水平,则减少通过所述流水线的指令吞吐量。
2.如权利要求1所述的处理器,其中,减少通过所述流水线的指令吞吐量是通过减小取出指令并将指令提供给所述流水线的速率来完成的。
3.如权利要求2所述的处理器,还包括指令取出电路和发布单元,所述指令取出电路从高速缓存中取出指令并且将所取出的指令提供给所述发布单元,以将所述指令派发给所述至少一个执行单元。
4.如权利要求2所述的处理器,还包括至少一个寄存器,用于存储使所述数字调节电路降低指令被提供给所述至少一个执行单元的速率的信息。
5.如权利要求1所述的处理器,其中,所述处理器包括在单个处理器芯片上的多个执行核心,每个执行核心具有流水线,以及其中,所述数字调节器是共享的数字调节器,用来调整在所述执行核心的所有流水线的功能单元中的活动。
6.如权利要求1所述的处理器,其中,所述处理器包括在单个处理器芯片上的多个执行核心,每个执行核心具有数字调节器,其中包括具有所述数字调节器的执行核心。
7.如权利要求1所述的处理器,其中,所述监控电路基于与所述执行单元相关联并且表示所述执行单元在被激活时消耗的功率量的功率加权来确定所述估计的功耗水平。
8.如权利要求1所述的处理器,其中,所述数字调节电路通过向所述处理器的指令执行流水线中注入气泡,来减少通过所述流水线的指令吞吐量。
9.如权利要求1所述的处理器,其中,所述数字调节器提供128个级别的调节。
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HK1046561B (zh) | 2005-06-03 |
WO2001048584A1 (en) | 2001-07-05 |
JP2012198922A (ja) | 2012-10-18 |
JP5073903B2 (ja) | 2012-11-14 |
CN101520725A (zh) | 2009-09-02 |
CN1434934A (zh) | 2003-08-06 |
JP2014112399A (ja) | 2014-06-19 |
AU1626601A (en) | 2001-07-09 |
TW512261B (en) | 2002-12-01 |
HK1046561A1 (en) | 2003-01-17 |
KR20020062986A (ko) | 2002-07-31 |
EP1259870B1 (en) | 2010-03-10 |
JP2003523563A (ja) | 2003-08-05 |
CN100492252C (zh) | 2009-05-27 |
ATE460698T1 (de) | 2010-03-15 |
GB2373896C (en) | 2013-02-13 |
US6564328B1 (en) | 2003-05-13 |
DE60043996D1 (de) | 2010-04-22 |
JP5650689B2 (ja) | 2015-01-07 |
EP1259870A1 (en) | 2002-11-27 |
JP6042830B2 (ja) | 2016-12-14 |
KR100511110B1 (ko) | 2005-08-31 |
GB0214785D0 (en) | 2002-08-07 |
GB2373896A (en) | 2002-10-02 |
GB2373896B (en) | 2004-11-03 |
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