CN101505974A - 用来制作双波纹结构的光掩模及其形成方法 - Google Patents

用来制作双波纹结构的光掩模及其形成方法 Download PDF

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Publication number
CN101505974A
CN101505974A CNA2006800416059A CN200680041605A CN101505974A CN 101505974 A CN101505974 A CN 101505974A CN A2006800416059 A CNA2006800416059 A CN A2006800416059A CN 200680041605 A CN200680041605 A CN 200680041605A CN 101505974 A CN101505974 A CN 101505974A
Authority
CN
China
Prior art keywords
layer
substrate
absorber layer
metal
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2006800416059A
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English (en)
Chinese (zh)
Inventor
S·S·麦唐纳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tekscend Photomasks Inc
Original Assignee
DuPont Photomasks Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by DuPont Photomasks Inc filed Critical DuPont Photomasks Inc
Publication of CN101505974A publication Critical patent/CN101505974A/zh
Pending legal-status Critical Current

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/68—Organic materials, e.g. photoresists
    • H10P14/683—Organic materials, e.g. photoresists carbon-based polymeric organic materials, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/091—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts by printing or stamping

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
CNA2006800416059A 2005-09-07 2006-09-06 用来制作双波纹结构的光掩模及其形成方法 Pending CN101505974A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US71462705P 2005-09-07 2005-09-07
US60/714,627 2005-09-07

Publications (1)

Publication Number Publication Date
CN101505974A true CN101505974A (zh) 2009-08-12

Family

ID=37836413

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2006800416059A Pending CN101505974A (zh) 2005-09-07 2006-09-06 用来制作双波纹结构的光掩模及其形成方法

Country Status (3)

Country Link
JP (1) JP2009523312A (https=)
CN (1) CN101505974A (https=)
WO (1) WO2007030527A2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102650822A (zh) * 2011-02-24 2012-08-29 中芯国际集成电路制造(上海)有限公司 双重图形化的纳米压印模具及其形成方法

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4684984B2 (ja) * 2005-12-07 2011-05-18 キヤノン株式会社 半導体装置の製造方法と物品の製造方法
DE102006030267B4 (de) * 2006-06-30 2009-04-16 Advanced Micro Devices, Inc., Sunnyvale Nano-Einprägetechnik mit erhöhter Flexibilität in Bezug auf die Justierung und die Formung von Strukturelementen
FR2942739B1 (fr) * 2009-03-03 2011-05-13 Commissariat Energie Atomique Procede de fabrication d'un moule pour la lithographie par nano-impression
FR2942738B1 (fr) 2009-03-03 2016-04-15 Commissariat Energie Atomique Procede de fabrication d'un moule pour la lithographie par nano-impression
KR101711646B1 (ko) 2009-12-11 2017-03-03 엘지디스플레이 주식회사 임프린트용 몰드의 제조방법 및 임프린트용 몰드를 이용한 패턴 형성방법
JP5349404B2 (ja) * 2010-05-28 2013-11-20 株式会社東芝 パターン形成方法
US9034233B2 (en) 2010-11-30 2015-05-19 Infineon Technologies Ag Method of processing a substrate
JP5681552B2 (ja) * 2011-04-15 2015-03-11 株式会社フジクラ インプリントモールドの製造方法及びインプリントモールド
JP6066793B2 (ja) * 2013-03-25 2017-01-25 京セラクリスタルデバイス株式会社 圧電素子ウエハ形成方法
KR102614850B1 (ko) * 2016-10-05 2023-12-18 삼성전자주식회사 반도체 소자 제조방법
KR102710915B1 (ko) * 2016-10-25 2024-09-26 엘지디스플레이 주식회사 임프린트 몰드 및 이의 제조방법
JP7547265B2 (ja) 2021-03-23 2024-09-09 キオクシア株式会社 設計パターン生成方法、テンプレート、テンプレートの製造方法、及び半導体装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3415335B2 (ja) * 1995-08-11 2003-06-09 大日本印刷株式会社 多段エッチング型基板の製造方法
US7037639B2 (en) * 2002-05-01 2006-05-02 Molecular Imprints, Inc. Methods of manufacturing a lithography template
US6852454B2 (en) * 2002-06-18 2005-02-08 Freescale Semiconductor, Inc. Multi-tiered lithographic template and method of formation and use
JP3821069B2 (ja) * 2002-08-01 2006-09-13 株式会社日立製作所 転写パターンによる構造体の形成方法
US7083880B2 (en) * 2002-08-15 2006-08-01 Freescale Semiconductor, Inc. Lithographic template and method of formation and use
US20040224261A1 (en) * 2003-05-08 2004-11-11 Resnick Douglas J. Unitary dual damascene process using imprint lithography
TW200507175A (en) * 2003-06-20 2005-02-16 Matsushita Electric Industrial Co Ltd Pattern forming method, and manufacturing method for semiconductor device
ATE451717T1 (de) * 2003-09-29 2009-12-15 Ibm Herstellungsverfahren

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102650822A (zh) * 2011-02-24 2012-08-29 中芯国际集成电路制造(上海)有限公司 双重图形化的纳米压印模具及其形成方法
CN102650822B (zh) * 2011-02-24 2015-03-11 中芯国际集成电路制造(上海)有限公司 双重图形化的纳米压印模具及其形成方法

Also Published As

Publication number Publication date
WO2007030527A3 (en) 2009-04-30
JP2009523312A (ja) 2009-06-18
WO2007030527A2 (en) 2007-03-15

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Application publication date: 20090812