CN101452892B - 鳍场效应晶体管器件结构的制造方法 - Google Patents
鳍场效应晶体管器件结构的制造方法 Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
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Abstract
本发明提供一种鳍场效应晶体管器件结构的制造方法,包括:提供绝缘体上硅衬底;在该绝缘体上硅衬底上形成具有各自的帽层的第一和第二半导体鳍;在该第一鳍上形成第一高k电介质层和第一金属层;在该第二鳍上形成第二高k电介质层和第二金属层,该第二金属层的最终组分不同于该第一金属层的最终组分;掺杂部分该第一和第二鳍;以及然后除去该第一和第二半导体鳍之间的部分该第一和第二高k电介质层和部分该第一和第二金属层。
Description
技术领域
本发明涉及制造半导体器件的方法,更特别地,涉及制造鳍场效应晶体管(FinFET)器件结构的方法。
背景技术
鳍场效应晶体管器件是众所周知的。为继续缩小晶体管的尺寸,例如减小到32nm甚至更小,鳍场效应晶体管器件是平面晶体管的替代技术之一。
一般来说,鳍场效应晶体管器件是形成于衬底例如绝缘体上硅(SOI)衬底上的非平面的双栅极晶体管。在鳍场效应晶体管器件中,导电沟道(channel)被形成器件的体(body)的薄半导体(例如硅)“鳍”围绕。鳍的尺寸本质上决定器件的有效沟道长度。
通过减少多晶硅耗尽(depletion)和栅极泄漏,包括金属导体和高k电介质的栅极进一步有助于缩小尺寸。
为有助于满足鳍场效应晶体管器件的不同需求,有时期望有在同一SOI衬底上形成的具有不同特性例如不同的阈值电压(Vt)的多个鳍场效应晶体管器件。
形成于同一半导体或SOI衬底上的包括多个具有金属导体和高k绝缘体栅极的FinFET器件的FinFET器件结构是已知的,例如参见美国专利No.7105390 B2,Justin K.Brask等人申请于2003年12月30日,授权于2006年9月12日,题为“NON PLANAR TRANSISTOR WITH METAL GATEELECTRODES”;美国专利No.7187046 B2,Chung-Chen Wu等人申请于2004年4月26日,授权于2007年3月6日,题为“METHOD OF FORMING ANN CHANNEL AND P CHANNEL FINFET DEVICE ON THE SAMESEMICONDUCTOR SUB STRATE。
虽然已知的鳍场效应晶体管器件及其制造方法是有帮助的,但本发明人认为可实现在同一衬底上制造鳍场效应晶体管器件的方法的进一步改良(例如成本、灵活性)。
发明内容
根据本发明,这里教导制造具有多个FinFET器件(例如n型和p型)的FinFET器件结构的方法,该多个FinFET器件形成于同一SOI衬底上,栅极中具有不同的金属导体和/或不同的高k绝缘体。
本发明的首要目的是提供一种在同一SOI衬底上制造具有不同电特性的多个鳍场效应晶体管器件的方法。
本发明的另一目的是提供一种在同一SOI衬底上制造包括具有不同组元(化学上和/或空间上)的栅极的NMOS鳍场效应晶体管和PMOS鳍场效应晶体管的方法。
根据本发明一优选实施例,制造鳍场效应晶体管器件结构的方法包括:
提供绝缘体上半导体(SOI)衬底,具有基层(例如半导体层)、在基层上的绝缘层和在绝缘层上的半导体层;
在SOI衬底上形成帽层(例如硅氮化物);
在绝缘层上形成第一和第二半导体鳍,第一帽层在第一鳍上,第二帽层在第二鳍上;
提供跨第一和第二帽层以及第一和第二鳍的第一高k电介质层;
在第一高k电介质层上提供第一金属层;
在第一金属层上提供第一半导体层;
从第二帽层、第二鳍且从与第二鳍相邻的区域除去第一半导体层、第一金属层和第一高k电介质层;
在第二帽层、第二鳍和部分第一金属层上提供第二高k电介质层;
在第二高k电介质层上提供第二金属层,该第二金属层具有与该第一金属层不同的组分;
在第二帽层之上的区域中的第二金属层上且在与第二鳍相邻的区域中提供第二半导体层;
从第二帽层之上的区域中的第二金属层,从毗邻区域且从与第二鳍相邻的区域除去第二半导体层;
从第一帽层之上的区域且从第一半导体层之上的毗邻区域(adjoiningregion)除去第二金属层和第二高k电介质层;
从包括第一和第二帽层的顶表面的平面以上的区域除去第一金属层、第一高k电介质层、第一半导体层、第二金属层、第二高k电介质层和第二半导体层;
形成第一和第二栅极;
在第一和第二鳍的与第一和第二栅极相邻的部分内形成各自的源极和漏极区域;以及然后
从第一和第二鳍之间的中间区域除去部分第一和第二半导体层、第一和第二高k电介质层以及第一和第二金属层。
结合附图参照具体实施方式,本发明的上述和其他目的将变得明显。
附图说明
图1-6、7A、7B、8A、9A、9B、9C,图8B、10A、10B是根据本发明的方法的优选实施例的各种侧截面图和平面示意图。
图11是流程图,示出根据本发明的方法的优选实施例的各步骤。
具体实施方式
根据本发明的方法的优选实施例示意性示于(不是按比例的)图1-10的顺序阶段中。根据优选实施例的步骤流程示于图11中。本发明人认为,考虑到本说明以及附图,实施根据本发明方法的优选实施例的每个步骤是在本领域的普通技能以内。因此,这里提供各步骤的具体细节到仅使普通技术人员实践本发明的程度。关于例如沉积、图案化、蚀刻、注入、掺杂、退火和/或平坦化和技术的进一步细节可见于例如VLSI Technology,by S.M.Sze,2nd Edition,Lib.Congress #TK7874.V566 1988 621.381’73.87-22803中。还参见Wu等人的专利’046 B2,通过引用在此并入其全部内容。另外,可参考在此通过引用并入其全部内容的以下美国专利:6657252 B2,Fried等人申请于2002年3月19日,授权于2003年12月2日,题为“FINFET CMOS WITHNVRAM CAPABILITY”;6992354 B2,Nowak等人申请于2003年6月25日,授权于2006年1月31日,题为“FINFET HAVING SUPPRESSEDPARASITIC DEVICE CHARACTERISTICS”。
现在参照附图,特别是图1。也参照图11所示的步骤。在第一步中,提供绝缘体上半导体(SOI)衬底10、20、30。SOI衬底包括半导体衬底10、绝缘层(BOX,二氧化硅)20、半导体材料(例如硅)30。然后,在下一步中,形成帽层40(例如硅氮化物(SiN)或其它合适的材料,通过例如化学气相沉积(CVD)形成)。帽层40覆盖例如SOI衬底10、20、30。
现在继续图2所示的下面的步骤,形成具有第一和第二SiN帽41、42的第一和第二半导体鳍31、32(通过已知技术,第一鳍31可以被“体”或“阱”掺杂以用于NFET,第二鳍32可以被“体”或“阱”掺杂以用于PFET)。然而,在该步骤掺杂鳍31、32是可选的,是设计选择事项。鳍31、32和帽41、42可以由任何合适的传统光刻和接着的已知的反应离子蚀刻(RIE)工艺来形成。替代地,已知的间隔物成像转移(spacer imaging transfer)技术可用于形成鳍和帽。例如参见Wu等人、Fried等人或Nowak等人的专利以了解背景技术。
鳍31、32每个(和帽41、42每个)具有宽度(W),其是约(10%)均匀的且选自5nm-300nm,更优选地10nm-100nm,最优选地20nm-50nm范围。优选地,鳍31、32的宽度(W)大致相同。
另外,鳍31、32每个具有高度(H),其是约(±10%)均匀的。优选地,鳍31、32的高度(H)大致相同,但替代地,可以根据特定应用而是不同的。每个高度(H)选自5nm到200nm的范围,更优选地10nm到100nm,最优选地15nm到40nm。
SiN帽41、42每个具有大致均匀的厚度(T)。优选地,帽41、42的厚度(T)大致相同,且选自20nm到50nm的厚度范围。本领域技术人员将理解,鳍31、32,帽41、42和层10、20具有沿指向图2的平面内的方向延伸的长度。
现在我们转到如参照图3所说明的后续步骤。如图所示,提供(例如沉积)跨第一和第二帽层41、42且跨第一和第二鳍31、32的第一高k电介质层50。
用于层50的高k材料的示例包括金属氧化物例如铪氧化物、铪硅氧化物、铪硅氮氧化物、镧氧化物、镧铝氧化物、锆氧化物、锆硅氧化物、锆硅氮氧化物、钽氧化物、钛氧化物、钡锶钛氧化物、钡钛氧化物、锶钛氧化物、钇氧化物、铝氧化物、铅钪钽氧化物、铅锌铌酸盐、以及这些材料的任意组合。这些高k电介质层或膜50通过CVD(化学气相沉积)、ALD(原子层沉积)或其它已知技术提供。层50具有选自约15埃到约30埃范围的大致均匀的最终厚度。
如图3所示,沉积层50之后,在第一高k电介质层50上沉积第一金属层60。
用于层60的金属材料的示例包括金属(例如钨、钛、钽、钌、铝、铂、银、金)、导电金属性化合物材料(例如钽氮化物、钛氮化物、钨硅化物、钨氮化物、钛氮化物、钽氮化物、钌氧化物、钴硅化物、镍硅化物)、碳纳米管、导电碳、或这些材料的任意合适组合。金属材料通过例如PVD(物理气相沉积)、CVD、ALD、或其它已知的合适方法沉积。优选地,层60具有选自50埃到100埃范围的大致均匀的最终厚度。
接着,如图4所示,通过任意常规技术例如CVD(化学气相沉积)实现多晶硅层70的沉积。然后,通过例如已知的化学机械抛光(CMP)平坦化多晶硅层70,除去多晶硅层70的一部分(示意性示出的P1),从而暴露第一金属栅极层60的顶表面。
在图5中,从第二帽层42、第二鳍32和与第二鳍32相邻的区域90除去第一半导体层70、第一金属层60和第一高k电介质层50。在第一金属层60和多晶硅层70(与鳍31相邻)上提供(例如沉积)的掩模80允许通过例如常规的反应离子蚀刻(RIE)除去覆盖第二鳍和在相邻区域90内的多晶硅层70。然后,通过蚀刻层50、60从第二鳍32和第二帽层42除去部分第一金属层60和部分第一高k电介质层50。所得中间结构示于图5中。
然后,通过标准蚀刻技术除去掩模80。
在图6中,在第二帽层42、第二鳍32、第一多晶硅层70和部分第一金属层60上提供第二高k电介质层500。可使用常规沉积技术。
接着,在位于第二帽层42上的第二金属层600上和与第二鳍32相邻的区域90中提供(例如沉积)第二半导体层700(图7A)。例如,通过沉积提供第二多晶硅层700。然后,通过CMP和/或其它常规去除技术从区域71、72除去部分多晶硅层700。然后,通过常规蚀刻除去第一鳍31上(即,从区域73、74)暴露的第二高k电介质层500和第二金属层600。这些步骤之后的中间结构示于图7A(横截面图)和7B(平面图)中。
在图8A和8B中,通过常规栅极图案化和蚀刻例如干蚀刻(RIE)和其他常规蚀刻去除包括第一和第二帽层41、42的顶表面S的平面P之上的层50、60、70、500、600、700,形成第一和第二栅极。可选地,在栅极图案化之前,除去第一鳍31顶部/上暴露的第一高k和第一金属层50、60以及第二鳍32顶部/上暴露的第二高k和第二金属层500、600。形成第一栅极(50、60、31、41、70)和第二栅极(500、600、32、46、700)之后的结构示于图8A和8B的视图中。另见例如授予Nowak等人的美国专利No.6992354 B2和文章Choi的文章“A Spacer Patterning Technology forNanoscale CMOS”,0018-9383102 IEEE,了解本发明可采用的栅极形成方法和技术。
在图9B、9A和9C中,通过常规离子注入或等离子体掺杂为第一和第二栅极形成合适的N和/或P源/漏极区域31A、31B。进行合适的常规退火以活化掺杂剂。栅极多晶硅之下的硅鳍被多晶硅栅极和SiN帽覆盖,且未被掺杂。见例如美国专利No.6992354 B2(通过引用并入于此)了解本发明可采用的常规源/漏极形成技术细节。掺杂是用于N和P器件,或者替代地,两种器件都是N掺杂或P掺杂。
接着,在图10A和10B中,进行图案化(掩模化,接着蚀刻)以除去第一FinFET和第二FinFET之间的部分高k和金属层50、60、500、600以及多晶硅层70、700,以得到图10A(横截面图)和10B(平面图)所示的最终结构。最终结构包括中空的中间区域75,其中可制造到FinFET的后续连接(未示出)。一般地,如图10B所示,区域75优选具有“类正方形”的顶部截面。
Claims (12)
1.一种制造鳍场效应晶体管器件结构的方法,包括:
提供绝缘体上半导体衬底,包括基层、在该基层上的绝缘层和在该绝缘层上的半导体层;
在绝缘体上半导体衬底上形成帽层;
在所述绝缘层上形成第一和第二半导体鳍,第一帽层在该第一鳍上,第二帽层在该第二鳍上;
提供跨该第一和第二帽层以及该第一和第二鳍的第一高k电介质层;
在该第一高k电介质层上提供第一金属层;
在该第一金属层上提供第一半导体层;
从该第二帽层、该第二鳍且从与该第二鳍相邻的区域除去该第一半导体层、该第一金属层和该第一高k电介质层;
在该第二帽层、该第二鳍和部分该第一金属层上提供第二高k电介质层;
在该第二高k电介质层上提供第二金属层,该第二金属层具有与该第一金属层不同的组分;
在该第二帽层之上的区域中的第二金属层上且在与该第二鳍相邻的区域中提供第二半导体层;
从该第二帽层之上的区域中的该第二金属层,从毗邻区域且从与该第二鳍相邻的区域除去该第二半导体层;
从该第一帽层之上的区域且从该第一半导体层之上的毗邻区域除去该第二金属层和该第二高k电介质层;
从包括该第一和第二帽层的顶表面的平面以上的区域除去该第一金属层、该第一高k电介质层、该第一半导体层、该第二金属层、该第二高k电介质层和该第二半导体层;
形成第一和第二栅极;
在该第一和第二鳍的与该第一和第二栅极相邻的部分内形成各自的源极和漏极区域;以及然后
从该第一和第二鳍之间的中间区域除去部分该第一和第二半导体层、该第一和第二高k电介质层以及该第一和第二金属层。
2.如权利要求1所述的方法,还包括形成该第一和第二鳍,使得每个鳍具有在20nm到50nm范围内的相等均匀性的单一宽度。
3.如权利要求1所述的方法,还包括形成该第一和第二鳍,使得每个鳍具有在15nm到40nm范围内的相等的最大高度。
4.如权利要求1所述的方法,其中该第一金属层具有与该第二金属层的化学组分不同的化学组分。
5.如权利要求1所述的方法,其中该第一高k电介质具有与该第二高k电介质的化学组分不同的化学组分。
6.如权利要求1所述的方法,其中该第一金属层具有与该第二金属层不同的最终尺寸。
7.如权利要求1所述的方法,其中该第一鳍和该第二鳍的每个具有选自从5nm到300nm宽度范围的相等且均一的宽度W。
8.如权利要求1所述的方法,其中该第一金属层具有与该第二金属层的化学组分不同的化学组分。
9.如权利要求1所述的方法,其中该第一帽层和该第二帽层具有选自20nm到50nm范围的相等的厚度T。
10.如权利要求1所述的方法,其中该第一半导体鳍和该第二半导体鳍具有选自15nm到40nm范围的相等的高度H。
11.如权利要求1所述的方法,其中该第一半导体鳍和该第二半导体鳍具有选自10nm到100nm范围的相等的宽度W。
12.如权利要求1所述的方法,其中该第一金属层和该第二金属层具有选自50埃到100埃范围的实质上不同的最终厚度。
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