CN107104139B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN107104139B
CN107104139B CN201611158235.9A CN201611158235A CN107104139B CN 107104139 B CN107104139 B CN 107104139B CN 201611158235 A CN201611158235 A CN 201611158235A CN 107104139 B CN107104139 B CN 107104139B
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CN107104139A (zh
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张哲诚
林志翰
曾鸿辉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体器件包括半导体衬底以及至少一个栅极堆叠件。栅极堆叠件位于半导体衬底上，并且栅极堆叠件包括至少一个功函数导体和填充导体。在功函数导体中具有凹槽。填充导体包括插塞部和盖部。插塞部位于功函数导体的凹槽中。盖部覆盖功函数导体。本发明还提供一种制造半导体器件的方法。

Description

半导体器件及其制造方法
相关申请的交叉参考
本申请要求于2016年2月19日提交的美国临时申请第62/297,750号的优先权，其内容结合于此作为参考。
技术领域
本发明涉及半导体领域，并且更具体地，涉及半导体器件及其制造方法。
背景技术
随着半导体工业已经为更高的器件密度、更高性能以及更低成本而努力，已经涉及包括的同时遇到的制造和设计的问题。这些问题的一种解决办法是发展鳍式场效应晶体管(FinFET)。典型的FinFET包括通过在衬底中蚀刻隔开的凹槽形成的薄的垂直的“鳍”。在鳍内限定源极、漏极以及沟道区。晶体管的栅极围绕鳍的沟道区围裹。这种结构使栅极能够在三个方向沟道中诱导电流流动。因此，FinFET器件具有增高电流流动并且减少短沟道效应的优点。
随着集成电路材料和高k金属栅极(HKMG)工艺已经取得的技术进步并且已经应用到FinFET，FinFET和其它金属氧化物半导体场效应晶体管(MOSFET)的尺寸已经逐渐减小。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各个部件没有按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意增加或减少。
图1至图16是根据本发明的一些实施例的各个阶段的制造半导体器件的方法的截面图。
发明内容
根据本发明的一个方面，提供一种半导体器件，包括：半导体衬底；以及位于半导体衬底上的至少一个栅极堆叠件，栅极堆叠件包括：至少一个功函数导体，在功函数导体中具有凹槽；以及填充导体，填充导体包括插塞部和盖部，插塞部位于功函数导体的凹槽中，盖部覆盖功函数导体。
根据本发明的另一方面，提供一种半导体器件，包括：半导体衬底；位于半导体衬底上的至少一个N型栅极堆叠件，在N型栅极堆叠件中包括填充导体，填充导体具有头部和尾部，尾部位于头部和半导体衬底之间；以及位于半导体衬底上的至少一个P型栅极堆叠件，在P型栅极堆叠件中包括填充导体，填充导体具有头部和尾部，尾部位于头部和半导体衬底之间，其中，N型栅极堆叠件和P型栅极堆叠件的填充导体的头部具有相同的宽度。
根据本方面的另一方面，提供一种制造半导体器件的方法，方法包括：在半导体衬底上形成至少两个栅极间隔件；在栅极间隔件之间形成至少一个功函数导体，在功函数导体中具有凹槽；使功函数导体在栅极间隔件之间凹陷以暴露栅极间隔件的侧壁的至少一部分；以及在凹槽以及栅极间隔件的侧壁的暴露部分之间的空间中形成填充导体。
具体实施方式
以下公开内容提供了许多不同实施例或实例，用于实现主题提供的不同特征。下面描述组件和布置的具体实例以简化本发明。当然，这些仅是实例并且不意欲限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括形成在第一部件和第二部件之间的附加部件，使得第一部件和第二部件不直接接触的实施例。此外，本发明可以在各个实例中重复参考标号和/或字符。这种重复是为了简化和清楚的目的，并且其本身并不表示所讨论的实施例和/或配置之间的关系。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语，以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，空间关系术语旨在包括在使用或操作过程中器件的不同方位。装置可以以其他方式定位(旋转90度或在其他方位)，并且在本文中使用的空间关系描述符可以同样地作相应地解释。
可以提升本发明的一个或多个实施例的器件的实例是半导体器件。例如，这样的器件是鳍式场效应晶体管(FinFET)器件。以下公开内容将继续以FinFET实例来说明本发明的各个实施例。然而，应该理解，除了权利要求中特别声明，本申请不应限制于特定类型的器件。
图1至图16是根据本发明的一些实施例的处于各个阶段处的制造半导体器件的方法的截面图。参考图1。提供了衬底110。在一些实施例中，衬底110包括硅。可选地，衬底110可以包括锗、硅锗、砷化镓或其他合适的半导体材料。同样可选地，衬底110可以包括外延层。例如，衬底110可以具有位于块状半导体上面的外延层。此外，衬底110可以应变以用于性能增强。例如，外延层可以包括那些与块状半导体的材料不同的半导体材料，半导体材料诸如位于块状硅上面的硅锗层或位于块状硅锗上面的硅层。可以通过选择性外延生长(SEG)形成这样的应变的衬底。此外，衬底110可以包括绝缘体上半导体(SOI)结构。进一步可选的，衬底110可以包括埋介电层，埋介电层诸如通过注氧隔离(SIMOX)技术、晶圆接合、SEG或其它合适方法形成的埋氧化物(BOX)层，埋氧化物(BOX)层诸如通过注氧隔离(SIMOX)技术、晶圆接合、SEG或其它合适方法形成。
半导体鳍112和114形成在衬底110上。在一些实施例中，半导体鳍112、114包括硅。例如，可以通过使用光刻技术图案化和蚀刻衬底110来形成半导体鳍112和114。在一些实施例中，光刻胶材料层(未示出)顺序沉积在衬底110上方。根据所需图案(这里为半导体鳍112和114)光照(曝光)并显影光刻胶材料层，从而去除部分的光刻胶材料层。剩余的光刻胶材料保护下面的材料免于随后的工艺步骤(诸如蚀刻)的损害。需要注意的是，诸如氧化物掩模或氮化硅掩模的其他掩模也可以用在蚀刻工艺中。
形成了隔离介电质105作为浅沟槽隔离(STI)以填充半导体鳍112和114之间的沟槽。隔离介电质105可以包括诸如氧化硅的任何合适的介电材料。形成隔离介电质105的方法可以包括：在衬底110上沉积隔离介电质105以覆盖半导体鳍112和114，可选的实施平坦化工艺以去除在沟槽外侧的过量的隔离介电质105，并且然后在隔离介电质105上实施蚀刻工艺直至暴露半导体鳍112和114的上部。
栅极介电质122和124分别形成在半导体鳍112和114以及衬底110上。栅极介电质122和124可以通过热氧化、化学汽相沉积、溅射或本领域已知的和用于形成栅极介电质的其他方法来形成。根据栅极介电质的形成工艺，位于半导体鳍112的顶部上的栅极介电质122的厚度可以不同于位于半导体鳍112的侧壁(未示出)上的栅极介电质122的厚度。相似的，位于半导体鳍114的顶部上的栅极介电质124的厚度可以不同于位于半导体鳍114的侧壁(未示出)上的栅极介电质124的厚度。可以图案化栅极介电质122和124以分别围裹半导体鳍112和114的中央部分，同时分别暴露部分的半导体鳍112和114。例如，至少一个栅极介电质122和124中可以包括高k介电材料，高k介电材料诸如金属氧化物、金属氮化物、金属硅盐酸、过渡金属氧化物、过渡金属氮化物、过渡金属硅盐酸、金属的氮氧化物、金属铝酸、硅酸锆、铝酸锆，或它们的组合。在一些实施例中，至少一个栅极结构122和124可以包括氧化铪(HfO2)、氧化铪硅(HfSiO)、氮氧化铪硅(HfSiON)、氧化铪钽(HfTaO)、氧化铪钛(HfTiO)、氧化铪锆(HfZrO)、氧化镧(LaO)、氧化锆(ZrO)、氧化钛(TiO)、氧化钽(Ta2O5)、氧化钇(Y2O3)、氧化锶钛(SrTiO3、STO)、氧化钡钛(BaTiO3、BTO)、氧化钡锆(BaZrO)、氧化铪镧(HfLaO)、氧化镧硅(LaSiO)、氧化铝硅(AlSiO)、氧化铝(Al2O3)、氮化硅(Si3N4)、氮氧化硅(SiON)以及它们的组合。至少一个栅极介电质122和124可以具有多层结构，多层结构诸如一层的氧化硅(即，界面层)和另一层高k材料。至少一个栅极介电质122和124可以使用化学汽相沉积(CVD)、物理汽相沉积(PVD)、原子层沉积(ALD)、热氧化、臭氧氧化、其他合适的工艺，或它们的组合形成。
伪栅极层132和134分别形成在栅极介电质122和124上。至少一个伪栅极层132和134可以通过CVD、溅射沉积或通过用于沉积导体材料的其它合适的技术形成。可以图案化伪栅极层132和134以分别围裹半导体鳍112和114的中央部分的同时分别暴露部分的半导体鳍112和114。在一些实施例中，可以通过相同的工艺图案化栅极介电质122和在栅极介电层122上的伪栅极层132。相似的，可以通过相同的工艺图案化栅极介电质124和伪栅极层134。至少一个伪栅极层132和134可以包括多晶硅(poly-Si)或多晶硅锗(poly-SiGe)。
参考图2。一对栅极间隔件142形成在衬底110上并且一对栅极间隔件142沿着伪栅极结构132形成，同时一对栅极间隔件144形成在衬底110上并且一对栅极间隔件144沿着伪栅极结构134形成。在一些实施例中，栅极间隔件142和144可以包括氧化硅、氮化硅、氮氧化硅或其他合适的材料。栅极间隔件142和144可以包括单层或多层结构。为了形成栅极间隔件142和144，可以通过CVD、PVD、ALD或其他合适的技术在衬底110上形成毯层。然后，在毯层上实施各向异性蚀刻以分别在伪栅极结构132和134的相对侧上形成栅极间隔件142和144。在一些实施例中，栅极间隔件142和144用于偏移随后形成的掺杂区域，掺杂区域诸如源极/漏极区域。栅极间隔件142和144可以进一步用于设计或改变源极/漏极区域(结)轮廓。
参考图3。通过伪栅极结构132和134以及栅极间隔件142和144两者暴露部分的半导体鳍112和114，去除(或凹陷)部分的半导体鳍112和114以在衬底110中形成凹槽112r和114r。可以去除任何合适量的材料。保留的半导体鳍112具有多个源极/漏极部分112s和位于源极/漏极部分112s之间的沟道部112c。保留的半导体鳍114具有多个源极/漏极部分114s和位于源极/漏极部分114s之间的沟道部114c。源极/漏极部分112s和114s嵌入在衬底110中并且部分的源极/漏极部分112s和114s通过凹槽112r和114r暴露。沟道部112c和114c分别位于伪栅极结构132和134下方。
去除部分的半导体鳍112和114可以包括在图2的结构上方形成光刻胶层或覆盖层(例如，氧化物覆盖层)，然后对光刻胶层或覆盖层图案化以得到使半导体鳍112和114的一部分暴露的开口，接着蚀刻半导体鳍112和114的暴露部分。在一些实施例中，可以使用干法蚀刻工艺来蚀刻半导体鳍114。可选地，该蚀刻工艺可以是湿法蚀刻工艺，或干法和湿法蚀刻工艺的组合。去除可包括光刻工艺来促进蚀刻工艺。该光刻工艺可包括光刻胶涂覆(例如，旋转涂覆)、软烘烤、掩模对准、曝光、曝光后烘烤、显影光刻胶、漂洗、干燥(例如，硬烘烤)、其他合适的工艺，或它们的组合。可选地，通过其他方法实现或替换光刻工艺，其他方法诸如无掩模光刻、电子束写入以及离子束写入。在另外一些其他的实施例中，光刻工艺可以实施纳米压印技术。在一些实施例中，可用HF或其他合适的溶液来实施预清洗过程以清洗凹槽112r和114r。
参考图4。多个外延结构152和154分别形成在半导体鳍112和114的凹槽112r和114r中并且多个外延结构152和154分别形成在源极/漏极区域112s和114s上。可以使用一个或多个外延或外延的(epi)工艺来形成该外延结构152和154，使得可以在半导体鳍112和114的源极/漏极区域112s和114s上以晶体状态形成Si部件、SiGe部件和/或其他合适的部件。在一些实施例中，外延结构152和154的晶格常数不同于半导体鳍112和114的晶格常数，使得半导体鳍112和114的沟道可以通过外延结构152和154应力或应变以提高半导体器件实现载流子迁移以及提高器件的性能。外延工艺包括CVD沉积技术(例如，汽相外延(VPE)和/或超高真空CVD(UHV-CVD))、分子束外延，和/或其他合适的工艺。该外延工艺可使用气体和/或液体前体，该气体和/或液体前体与半导体鳍112和114(例如，硅)的嵌入部分122s和114s的组成部分相互作用。因此，可获得应变的沟道以提高载流子迁移率同时加强器件性能。外延结构152和154可以是原位掺杂的。掺杂的物质包括p型掺杂物(诸如硼或BF2)；n型掺杂物(例如磷或砷)；和/或包含它们的组合在内的其他合适的掺杂物。如果外延结构152和154不是原位掺杂的，那么将实施第二注入工艺(即，结注入工艺)以掺杂该外延结构152和154。可以实施一个或多个退火工艺以激活外延结构152和154。退火工艺包括快速热退火(RTA)和/或激光退火工艺。
然后，层间介电(ILD)层160形成在栅极间隔件142和144的外侧以及衬底110上。ILD层160可以由氧化硅、氮化硅、氮氧化硅、碳化硅、低介电常数介电材料或它们的组合制成。ILD层160包括单层或多层。ILD层160通过诸如CVD的合适的技术形成。可以应用化学机械平坦化(CMP)工艺以去除过量的ILD层160并且将伪栅极结构132和134的顶面暴露于随后的伪栅极去除工艺。
参考图5。去除伪栅极结构132和134(参考图4)以形成具有栅极间隔件142作为侧壁的开口162和具有栅极间隔件144作为侧壁的开口164。在一些实施例中，也去除栅极介电质122和124。可选的，在一些实施例中，如图5中示出的，去除伪栅极结构132和134的同时也保留栅极介电质122和124。可以通过干法蚀刻、湿法蚀刻或干法蚀刻和湿法蚀刻的组合去除伪栅极结构132和134(以及栅极介电层122和124)。例如，湿法蚀刻工艺可以包括暴露含氢氧化物溶液(如，氢氧化铵)、去离子水，和/或其他合适的蚀刻剂溶液。
参考图6。P型功函数材料172可以形成在图5中示出的结构上。P型功函数材料172可以提供用于P型半导体器件的P型栅极堆叠件的所需的功函数值。P型功函数材料172可以通过合适的工艺形成，合适的工艺诸如ALD、CVD、PVD、远程等离子CVD(RPCVD)、等离子体增强CVD(PECVD)、金属有机物CVD(MOCVD)、溅射、电镀、其它合适的工艺，和/或其组合物。在一些实施例中，P型功函数材料172可以由TiN、Co、WN或TaC制成。
可以形成介电材料240(例如，旋涂玻璃)，介电材料240覆盖部分的P型功函数材料172并且介电材料240填充开口164。可以在介电材料240上方限定光刻胶245。可以提供介电材料240和/或光刻胶245用于P型功函数材料172，该P型功函数材料172用于P型半导体器件。例如，可以通过旋涂工艺、光刻工艺以及蚀刻工艺限定介电材料240和光刻胶245。
参考图7。可以去除图6的未通过介电材料240和光刻胶245覆盖的部分的P型功函数材料172，限定了一个P型功函数导体层172p。在限定了P型功函数导体层172p后，可以通过湿法蚀刻工艺、干法蚀刻工艺，和/或其组合方法去除图6的介电材料240和光刻胶245，暴露P型功函数导体层172p。
参考图8。N型功函数材料174可以形成在图7中示出的结构上。N型功函数材料174可以提供用于N型半导体器件的N型栅极堆叠件的所需的功函数值。N型功函数材料174可以通过合适的工艺形成，合适的工艺诸如ALD、CVD、PVD、远程等离子CVD(RPCVD)、等离子体增强CVD(PECVD)、金属有机物CVD(MOCVD)、溅射、电镀、其它合适的工艺，和/或其组合物。在一些实施例中，N型功函数材料174可以由Ti、Al或TiAl制成。
参考图9。可以采用CMP工艺去除开口162和164外侧的过量的部分的P型功函数导体层172p和N型功函数材料174，以提供一个对于P型功函数导体层172p、N型功函数导体层174n和174p的基本上为平面的顶面。保留的N型功函数导体层174n位于开口162中。保留的P型功函数导体层172p和N型功函数导体层174p位于开口164中。
参考图10。掩模180形成在图9中示出的结构上。具体来说，功函数导体在开口162中，功函数导体包括N型功函数导体层174n，在N型功函数导体层174n中具有凹槽R1。具体来说，功函数导体在开口164中，功函数导体包括N型功函数导体层174p和N型功函数导体层172p，在N型功函数导体层174p中具有凹槽R2。掩模180可以作为填充层，并且掩模180至少形成在凹槽R1和R2的下部。使得填充层可以保护下面的功函数导体免于随后对功函数导体的上部实施的蚀刻工艺的损害。在一些实施例中，掩模180过量填充凹槽R1和R2。在一些实施例中，掩模180可以是硬掩模，掩模180包括氮化硅、氮氧化硅、碳化硅，和/或其它合适的材料。可以使用诸如CVD或者PVD的方法形成掩模180。
参考图11。去除部分的掩模180以至少暴露在开口162和164中的功函数导体的顶面，以对于在开口162和164中的功函数导体随后实施的蚀刻工艺有益。换句话说，在凹槽R1和R2中凹陷的掩模180用作填充层，以在开口162和164中暴露部分的功函数导体。特别是，在去除掩模180的覆盖部分之后，暴露在开口162中的N型功函数导体层174n的顶面。相似地，在去除掩模180的覆盖部分之后，暴露N型功函数导体层174n和P型功函数导体层172p的顶面。在一些实施例中，在移除工艺后，去除掩模180的上部以至少暴露功函数导体的顶面，并且保留在凹槽R1和R2中掩模180的下部以保护下面的功函数导体。去除掩模180的上部的实例方法可以是回蚀工艺。
参考图12。凹陷在开口162和164中的功函数导体，以至少暴露栅极间隔件142和144的部分的侧壁1422和1442。特别地，每个栅极间隔件142具有侧壁1422，并且栅极间隔件142的侧壁1422是相对的同时在侧壁间隔件1422之间限定开口162。在开口162中的和在栅极间隔件142的侧壁1422之间凹陷N型功函数导体层174n，使得暴露侧壁1422的上部。相似地，每个栅极间隔件144具有侧壁1442，并且栅极间隔件144的侧壁1442是相对的同时在侧壁间隔件1422之间限定开口164。在开口164中的和在栅极间隔件144的侧壁1442之间凹陷N型功函数导体层174p和P型功函数导体层172p，使得暴露侧壁1442的上部。在凹陷工艺后，可以塑形在开口162中的N型功函数导体层174n的顶面，使得凹槽R1具有锥形开口R12和与锥形开口R12互相连通的底部凹槽R14。底部凹槽R14位于锥形开口R12和半导体鳍112之间。锥形开口R12朝向底部凹槽R14逐渐变细。换句话说，锥形开口R12具有的宽度大于底部凹槽R14具有的宽度，并且锥形开口R12的宽度在空间上是不同的。相似的，在凹陷工艺后，可以塑形在开口164中的N型功函数导体层174p和P型功函数导体层172p的顶面，使得凹槽R2具有锥形开口R22和与锥形开口R22互相连通的底部凹槽R24。底部凹槽R24位于锥形开口R22和半导体鳍114之间。锥形开口R22朝向底部凹槽R24逐渐变细。换句话说，锥形开口R22具有的宽度大于底部凹槽R24具有的宽度，并且锥形开口R22的宽度空间上是不同的。凹陷功函数导体的实例方法可以包括湿法蚀刻工艺，该湿法蚀刻工艺选择性去除部分的未通过掩模180保护的功函数导体(例如，功函数金属退出工艺)。
参考图13。去除在凹槽R1和R2中的掩模180(参考图12)以暴露凹槽R1和R2。换句话说，在去除工艺后，暴露位于掩模180下方和在开口162中的部分的功函数导体(即，N型功函数导体层174n的底部)。相似的，在去除后，也暴露位于掩模180下方和在开口164中的部分的功函数导体(即，N型功函数导体层174p的底部)。在凹槽R1和R2中去除掩模180的实例方法是湿法蚀刻，湿法蚀刻能够选择性去除氮化硅，并且该湿法蚀刻采用热(约145℃至180℃)磷酸(H3PO4)溶液。
参考图14。在凹槽R1中和栅极间隔件142的侧壁1422的暴露部分之间的空间形成的填充导体190。在一些实施例中，形成的填充导体190包括填充导体190过量填充凹槽R1，使得填充导体190到达栅极间隔件142的侧壁1422的暴露部分，并且因此，填充导体190具有插塞部192(或尾部)和与插塞部192互相连接的盖部194(或头部)。插塞部192位于开口162中的功函数导体的凹槽R1中。盖部194覆盖开口162中的功函数导体。特别地，插塞部192占有N型功函数导体层174n的凹槽R1。盖部194覆盖插塞部192和N型功函数导体层174n，并且盖部194可以与栅极间隔件142的侧壁1422接触。这样N型功函数导体层174n和填充导体190可以协同作为用于N型半导体器件的N型栅极堆叠件G1。在N型栅极堆叠件G1中，由于盖部194覆盖N型功函数导体层174n，可以增加N型栅极堆叠件G1的接触面积，其可以有益于在N型栅极堆叠件G1(尤其是盖部194)上形成接触。
相似地，在凹槽R2中和栅极间隔件144的侧壁1442的暴露部分之间的空间形成的填充导体200。在一些实施例中，形成的填充导体200包括填充导体200过量填充凹槽R2，使得填充导体200到达栅极间隔件144的侧壁1442的暴露部分，并且因此，填充导体200具有插塞部202(或尾部)和与插塞部192互相连接的盖部204(或头部)。插塞部202位于开口164中的功函数导体的凹槽R2中。盖部204覆盖开口164中的功函数导体。特别地，插塞部202占有N型和P型功函数导体层174p和172p的凹槽R2。盖部204覆盖插塞部202和N型和P型功函数导体层174p和172p，并且盖部204可以与栅极间隔件144的侧壁1442接触。这样N型和P型功函数导体层174p和172p和填充导体200可以协同作为用于P型半导体器件的P型栅极堆叠件G2。在P型栅极堆叠件G2中，由于盖部204覆盖N型和P型功函数导体层174p和172p，可以增加P型栅极堆叠件G2的接触面积，其可以有益于在P型栅极堆叠件G2(尤其是盖部204)上形成接触。
在一些实施例中，由于N型栅极堆叠件G1的填充导体190的盖部194过量填充凹槽R1以到达相对侧壁1422，在相对侧壁1422之间的盖部194具有相等距离的宽度。相似地，由于P型栅极堆叠件G2的盖部204过量填充凹槽R2以到达相对侧壁1442，在相对侧壁1442之间的盖部204具有相等距离的宽度。在一些实施例中，在相对侧壁1422之间的距离和在相对侧壁1442之间的距离可以是相同的，使得N型栅极堆叠件G1和P型栅极堆叠件G2的盖部194和204具有基本上相同的宽度，即使N型栅极堆叠件G1和P型栅极堆叠件G2的功函数导体是不同的，其可以有利于盖部194和204以推挤下部的功函数导体。换句话说，即使N型栅极堆叠件G1的功函数导体包括N型功函数层174n同时P型栅极堆叠件G2的功函数导体包括N型和P型功函数导体层174p和172p两者，具有基本上相同的宽度的盖部194和204可以分别提供优化力以推挤下部的功函数导体。
在一些实施例中，由于N型栅极堆叠件G1的功函数导体包括N型功函数层174n同时P型栅极堆叠件G2的功函数导体包括N型和P型功函数导体层174p和172p两者，N型和P型栅极堆叠件G1和G2的功函数导体具有不同的形状，并且因此，凹槽R1和R2具有不同的宽度。同样的，N型和P型栅极堆叠件G1和G2的填充导体190和200的插塞部192和202具有不同的宽度。
在一些实施例中，由于盖部194和204分别通过过量填充凹槽R1和R2形成，并且插塞部192和202分别位于凹槽R1和R2中，盖部194和204的宽度大于插塞部192和202的宽度，其可以有益于增加N型和P型栅极堆叠件G1和G2的接触面积。不同的方式中，分别在开口162和164中的盖部194和204的宽度不小于功函数导体的宽度，使得可以增加N型和P型栅极堆叠件G1和G2的接触面积。特别地，盖部194的宽度不小于N型栅极堆叠件G1的N型功函数层174n的宽度，并且盖部204的宽度小于P型栅极堆叠件G2的P型功函数层172p的宽度。
在一些实施例中，由于盖部194和204分别通过过量填充凹槽R1和R2形成以使盖部194和204到达侧壁1422和1442，在开口162中的功函数导体不位于盖部194的至少一个侧壁上，并且在开口164中的功函数导体也不位于盖部204的至少一个侧壁上。换句话说，栅极间隔件142位于N型栅极堆叠件G1的至少一个侧壁上，并且N型栅极堆叠件G1的功函数导体(包括N型功函数导体层174n)不位于盖部194和栅极间隔件142之间。相似地，栅极间隔件144位于P型栅极堆叠件G2的至少一个侧壁上，并且P型栅极堆叠件G2的功函数导体(包括N型和P型功函数导体层174p和172p)不位于盖部204和栅极间隔件144之间。
在一些实施例中，又不插塞部192和202分别占用凹槽R1和R2，插塞部192和202可以具有与凹槽R1和R2的N型功函数导体层174n和174p相同的形状。特别地，插塞部192可以包括锥形插塞1922和与锥形插塞1922互相连接的底部插塞1924。锥形插塞1922位于盖部194与底部插塞1924之间。锥形插塞1922占用锥形开口R12，并且底部插塞1924占用底部凹槽R14。因此，锥形插塞1922从盖部194至底部插塞1924逐渐变细。换句话说，锥形插塞1922具有的宽度大于底部插塞1924具有的宽度，并且锥形插塞1922的宽度在空间上是不同的。相似地，插塞部202可以包括锥形插塞2022和与锥形插塞2022互相连接的底部插塞2024。锥形插塞2022位于盖部204与底部插塞2024之间。锥形插塞2022占用锥形开口R22，并且底部插塞2024占用底部凹槽R24。因此，锥形插塞2022从盖部204至底部插塞2024逐渐变细。换句话说，锥形插塞2022具有的宽度大于底部插塞2024具有的宽度，并且锥形插塞2022的宽度在空间上是不同的。
在一些实施例中，锥形插塞1922和栅极间隔件142的侧壁1422限定的角度α1在从约0°至约90°的范围内。在一些实施例中，通过锥形插塞1922和栅极间隔件142的侧壁1422限定的角度α1可以在从约25°到约88°的范围内或在从约43°至约82°范围内或在从约67°到约79°范围内。相似地，锥形插塞2022和栅极间隔件144的侧壁1442限定的角度α2在从约0°至约90°的范围内。在一些实施例中，通过锥形插塞2022和栅极间隔件144的侧壁1442限定的角度α2的范围可以在从约25°到约88°的范围内或在从约43°至约82°范围内或在从约67°到约79°范围内。在一些实施例中，锥形插塞1922和底部凹槽R14的侧壁限定的角度β1在从约90°至约180°的范围内。在一些实施例中，通过锥形插塞1922和底部凹槽R14的侧壁限定的角度β1的范围可以在从约102°到约163°的范围内或在从约115°至约154°范围内或在从约120°到约146°范围内。相似地，锥形插塞2022和底部凹槽R24的侧壁限定的角度β2在从约90°至约180°的范围内。在一些实施例中，通过锥形插塞2022和底部凹槽R24的侧壁限定的角度β2的范围可以在从约102°到约163°的范围内或在从约115°至约154°范围内或在从约120°到约146°范围内。
在一些实施例中，形成填充导体190和200的实例方法可以包括诸如CVD、PVD、ALD或其它合适工艺的沉积工艺。在沉积工艺后，可以采用CMP工艺以移除过量的填充导体190和200，即过量填充到开口162和164外侧的填充导体190和200。在一些实施例中，填充导体190和200由相同的工艺制成并且填充导体190和200由基本上相同的材料制成。例如，填充导体190和200可以包括钨(W)、铝(Al)、铜(Cu)或其它合适的材料。
参考图15。在栅极间隔件142的侧壁1422的暴露部分之间的空间中凹陷部分的填充导体190，并且也在栅极间隔件144的侧壁1442的暴露部分之间的空间中凹陷部分的填充导体200。更具体地，去除盖部194和204的上部，并且在N型和P型栅极堆叠件G1和G2中分别保留盖部194和204的下部。填充导体190和200的凹陷部分的实例方法可以包括蚀刻工艺。例如，凹陷包括与填充导体190和200反应的蚀刻剂，在凹槽中位于填充导体190、200之间和位于栅极间隔件142、144之间的蚀刻剂具有高选择性。
参考图16。介电盖210和220分别形成在凹陷的填充导体190和200上。换句话说，介电盖210和220分别封住凹陷的填充导体190和200。介电盖210和N型栅极堆叠件G1的功函数导体包括N型功函数导体层174n，介电盖210和N型功函数导体层174n在空间上通过填充导体190间隔开。特别地，填充导体190的盖部194空间上将N型功函数导体层174n与介电盖210分隔开。相似地，介电盖220和P型栅极堆叠件G2的功函数导体包括N型和P型功函数导体层174p和172p，介电盖210和N型和P型功函数导体层174p和172p在空间上通过填充导体200间隔开。特别地，盖部204空间上将N型和P型功函数导体层174p和172p与介电盖220分隔开。在一些实施例中，盖部194的宽度不小于介电盖210的宽度，以有益于盖部194在空间上将位于上方的介电盖210与位于下方的N型功函数导体层174n分隔开。相似地，盖部204的宽度不小于介电盖220的宽度，以有益于盖部204在空间上将上方的介电盖220与下方的N型和P型功函数导体层174p和172p分隔开。
形成介电盖210和220的实例方法可以包括诸如ALD、CVD、PVD或其它合适工艺的沉积工艺。在沉积工艺后，可以采用CMP工艺以移除过量的介电盖210和220，即过量填充到开口162和164外侧的介电盖210和220。介电盖210和220可以由氧化硅、氮化硅、氮氧化硅、碳化硅、低介电常数介电材料或其它合适的材料制成。
在一些实施例中，由于填充导体包括盖部，盖部覆盖功函数导体，可以增加盖部与栅极堆叠件的接触面积。还有，在一些实施例中，由于N型和P型栅极堆叠件的填充导体的盖部(或头部)具有基本上相同的宽度，盖部可以提供优化力以推挤下部的N型和P型栅极堆叠件的功函数导体。
在一些实施例中，半导体器件包括半导体衬底以及至少一个栅极堆叠件。栅极堆叠件位于半导体衬底上，并且栅极堆叠件包括至少一个功函数导体和填充导体。在功函数导体中具有凹槽。填充导体包括插塞部和盖部。插塞部位于功函数导体的凹槽中。盖部覆盖功函数导体。
在一些实施例中，半导体器件包括半导体衬底、至少一个N型栅极堆叠件以及至少一个P型栅极堆叠件。N型栅极堆叠件位于半导体衬底上。在N型栅极堆叠件中包括填充导体。填充导体具有头部和尾部。尾部位于头部和半导体衬底之间。P型栅极堆叠件位于半导体衬底上。在P型栅极堆叠件中包括填充导体。填充导体具有头部和尾部。尾部位于头部和半导体衬底之间。N型栅极堆叠件和P型栅极堆叠件的填充导体的头部具有基本上相同的宽度。
在一些实施例中，制造半导体器件的方法包括在半导体衬底上形成至少两个栅极间隔件，在栅极间隔件之间形成至少一个功函数导体，在功函数导体中具有凹槽，在栅极间隔件之间凹陷功函数导体以暴露栅极间隔件的至少部分的侧壁，以及在凹槽中和在栅极间隔件的侧壁的暴露部分之间的空间中形成填充导体。
根据本发明的一个方面，提供一种半导体器件，包括：半导体衬底；以及位于半导体衬底上的至少一个栅极堆叠件，栅极堆叠件包括：至少一个功函数导体，在功函数导体中具有凹槽；以及填充导体，填充导体包括插塞部和盖部，插塞部位于功函数导体的凹槽中，盖部覆盖功函数导体。
根据本发明的一个实施例，填充导体包括钨。
根据本发明的一个实施例，盖部的宽度大于插塞部的宽度。
根据本发明的一个实施例，盖部的宽度不小于功函数导体的宽度。
根据本发明的一个实施例，半导体器件还包括：覆盖填充导体的介电盖，其中，介电盖和功函数导体被填充导体在空间上分隔开。
根据本发明的一个实施例，盖部的宽度不小于介电盖的宽度。
根据本发明的一个实施例，插塞部包括锥形插塞和底部插塞，锥形插塞位于盖部和底部插塞之间并且从盖部至底部插塞逐渐变细。
根据本发明的一个实施例，功函数导体的凹槽包括锥形开口和底部凹槽，锥形开口位于盖部和底部凹槽之间并且朝向底部凹槽逐渐变细。
根据本发明的一个实施例，功函数导体不在盖部的至少一个侧壁上。
根据本发明的一个实施例，半导体器件还包括：位于栅极堆叠件的至少一个侧壁上的至少一个栅极间隔件，其中，功函数导体不在盖部和栅极间隔件之间。
根据本发明的另一方面，提供一种半导体器件，包括：半导体衬底；位于半导体衬底上的至少一个N型栅极堆叠件，在N型栅极堆叠件中包括填充导体，填充导体具有头部和尾部，尾部位于头部和半导体衬底之间；以及位于半导体衬底上的至少一个P型栅极堆叠件，在P型栅极堆叠件中包括填充导体，填充导体具有头部和尾部，尾部位于头部和半导体衬底之间，其中，N型栅极堆叠件和P型栅极堆叠件的填充导体的头部具有相同的宽度。
根据本发明的一个实施例，在N型栅极堆叠件中包括至少一个N型功函数导体，并且N型功函数导体被N型栅极堆叠件的填充导体的头部覆盖。
根据本发明的一个实施例，在P型栅极堆叠件中包括至少一个P型功函数导体，并且P型功函数导体被P型栅极堆叠件的填充导体的头部覆盖。
根据本发明的一个实施例，N型栅极堆叠件和P型栅极堆叠件的填充导体的尾部具有不同的宽度。
根据本发明的一个实施例，N型栅极堆叠件和P型栅极堆叠件的填充导体由相同的材料制成。
根据本方面的另一方面，提供一种制造半导体器件的方法，方法包括：在半导体衬底上形成至少两个栅极间隔件；在栅极间隔件之间形成至少一个功函数导体，在功函数导体中具有凹槽；使功函数导体在栅极间隔件之间凹陷以暴露栅极间隔件的侧壁的至少一部分；以及在凹槽以及栅极间隔件的侧壁的暴露部分之间的空间中形成填充导体。
根据本发明的一个实施例，形成填充导体包括：用填充导体过量填充凹槽使得填充导体到达栅极间隔件的侧壁的暴露部分。
根据本发明的一个实施例，方法还包括：使栅极间隔件的侧壁的暴露部分之间的空间中的填充导体的一部分凹陷；以及在凹陷的填充导体上形成介电盖。
根据本发明的一个实施例，方法还包括：在凹槽的下部中形成填充层，其中，在形成填充层后实施凹陷；以及在凹陷后去除填充层。
根据本发明的一个实施例，形成填充层包括：用填充层过量填充凹槽；以及在凹槽中使填充层凹陷。
以上论述了若干实施例的部件，使得本领域的技术人员可以更好地理解本发明的各个方面。本领域技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他的处理和结构以用于达到与本发明所介绍实施例相同的目的和/或实现相同优点。本领域技术人员也应该意识到，这些等效结构并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (20)

1.一种半导体器件，包括：
半导体衬底；以及
位于所述半导体衬底上的至少一个栅极堆叠件，所述栅极堆叠件包括：
至少一个功函数导体，在所述功函数导体中具有凹槽；以及
填充导体，所述填充导体包括插塞部和盖部，所述插塞部位于所述功函数导体的所述凹槽中，所述盖部覆盖所述功函数导体；
覆盖所述盖部的介电盖，所述盖部的侧壁和所述介电盖的侧壁共平面；
位于所述栅极堆叠件的至少一个侧壁上的至少一个栅极间隔件，
其中，所述盖部的侧壁和所述介电盖的侧壁以及所述功函数导体的外侧壁均与所述栅极间隔件直接接触，
所述栅极间隔件在对应于所述功函数导体处具有的厚度，与所述栅极间隔件在对应于所述盖部处具有的厚度相同。
2.根据权利要求1所述的半导体器件，其中，所述填充导体包括钨。
3.根据权利要求1所述的半导体器件，其中，所述盖部的宽度大于所述插塞部的宽度。
4.根据权利要求1所述的半导体器件，其中，所述盖部的宽度不小于所述功函数导体的宽度。
5.根据权利要求1所述的半导体器件，其中，所述介电盖和所述功函数导体被所述填充导体在空间上分隔开，所述栅极间隔件的顶面和所述介电盖的顶面共平面。
6.根据权利要求5所述的半导体器件，其中，所述盖部的宽度不小于所述介电盖的宽度。
7.根据权利要求1所述的半导体器件，其中，所述插塞部包括锥形插塞和底部插塞，所述锥形插塞位于所述盖部和所述底部插塞之间并且从所述盖部至所述底部插塞逐渐变细。
8.根据权利要求1所述的半导体器件，其中，所述功函数导体的所述凹槽包括锥形开口和底部凹槽，所述锥形开口位于所述盖部和所述底部凹槽之间并且朝向所述底部凹槽逐渐变细。
9.根据权利要求1所述的半导体器件，其中，所述功函数导体不在所述盖部的至少一个侧壁上。
10.根据权利要求1所述的半导体器件，其中，所述功函数导体不在所述盖部和所述栅极间隔件之间。
11.一种半导体器件，包括：
半导体衬底；
位于所述半导体衬底上的至少一个N型栅极堆叠件，在所述N型栅极堆叠件中包括填充导体，所述填充导体具有头部和尾部，所述尾部位于所述头部和所述半导体衬底之间；以及
位于所述半导体衬底上的至少一个P型栅极堆叠件，在所述P型栅极堆叠件中包括填充导体，所述填充导体具有头部和尾部，所述尾部位于所述头部和所述半导体衬底之间，其中，所述N型栅极堆叠件和所述P型栅极堆叠件的所述填充导体的所述头部具有相同的宽度；
其中，对于所述N型栅极堆叠件和所述P型栅极堆叠件中的至少一个，还包括：
覆盖头部的介电盖，所述头部的侧壁和所述介电盖的侧壁共平面；
位于栅极堆叠件的至少一个侧壁上的至少一个栅极间隔件，
其中，所述头部的侧壁和所述介电盖的侧壁以及围绕所述尾部的功函数导体的外侧壁均与所述栅极间隔件接触，
所述栅极间隔件在对应于所述功函数导体处具有的厚度，与所述栅极间隔件在对应于所述头部处具有的厚度相同。
12.根据权利要求11所述的半导体器件，其中，在所述N型栅极堆叠件中包括至少一个N型功函数导体，并且所述N型功函数导体被所述N型栅极堆叠件的所述填充导体的所述头部覆盖。
13.根据权利要求11所述的半导体器件，其中，在所述P型栅极堆叠件中包括至少一个P型功函数导体，并且所述P型功函数导体被所述P型栅极堆叠件的所述填充导体的所述头部覆盖。
14.根据权利要求11所述的半导体器件，其中，所述N型栅极堆叠件和所述P型栅极堆叠件的所述填充导体的所述尾部具有不同的宽度。
15.根据权利要求11所述的半导体器件，其中，所述N型栅极堆叠件和所述P型栅极堆叠件的所述填充导体由相同的材料制成。
16.一种制造半导体器件的方法，所述方法包括：
在半导体衬底上形成至少两个栅极间隔件；
在所述栅极间隔件之间形成至少一个功函数导体，在所述功函数导体中具有凹槽；
使所述功函数导体在所述栅极间隔件之间凹陷以暴露所述栅极间隔件的侧壁的至少一部分；以及
在所述凹槽以及所述栅极间隔件的所述侧壁的所述暴露部分之间的空间中形成填充导体，所述填充导体包括插塞部和盖部；
形成覆盖所述盖部的介电盖，所述盖部的侧壁和所述介电盖的侧壁共平面；
其中，所述盖部的侧壁和所述介电盖的侧壁以及所述功函数导体的外侧壁均与所述栅极间隔件直接接触，
所述栅极间隔件在对应于所述功函数导体处具有的厚度，与所述栅极间隔件在对应于所述盖部处具有的厚度相同。
17.根据权利要求16所述的方法，其中，形成所述填充导体包括：
用所述填充导体过量填充所述凹槽使得所述填充导体到达所述栅极间隔件的所述侧壁的所述暴露部分。
18.根据权利要求16所述的方法，形成所述介电盖包括：
使所述栅极间隔件的所述侧壁的所述暴露部分之间的空间中的所述填充导体的一部分凹陷；以及
在所述凹陷的填充导体上形成所述介电盖。
19.根据权利要求16所述的方法，还包括：
在所述凹槽的下部中形成填充层，其中，在形成所述填充层后实施所述凹陷；以及
在所述凹陷后去除所述填充层。
20.根据权利要求19所述的方法，其中，形成所述填充层包括：
用所述填充层过量填充所述凹槽；以及
在所述凹槽中使所述填充层凹陷。
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