CN101425457B - 高介电常数栅极介电材料的形成方法与半导体元件 - Google Patents

高介电常数栅极介电材料的形成方法与半导体元件 Download PDF

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CN101425457B
CN101425457B CN2008101738421A CN200810173842A CN101425457B CN 101425457 B CN101425457 B CN 101425457B CN 2008101738421 A CN2008101738421 A CN 2008101738421A CN 200810173842 A CN200810173842 A CN 200810173842A CN 101425457 B CN101425457 B CN 101425457B
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dielectric constant
high dielectric
dielectric material
formation method
constant grid
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CN101425457A (zh
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欧阳晖
尚·路克·艾佛拉特
萝拉·宁斯
莉塔·沃斯
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Inter-University Microelectronics Center
Katholieke Universiteit Leuven
Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种高介电常数栅极介电材料的形成方法与半导体元件，该方法包括下列步骤：提供一半导体基材；清洗该基材；对该基材进行一热处理，其中该热处理在一无氧化环境中进行，导致形成一薄界面层；以及沉积一高介电常数材料于薄界面层之上。本发明的方法能产生均匀且薄的、具有适当的末端的界面层，使其能够相容于后续高介电常数(high-k)材料的沉积，并能改善界面层的粗糙度与品质。同时，本发明的结构能增进在半导体元件中的电荷载流子迁移率。

Description

高介电常数栅极介电材料的形成方法与半导体元件 
技术领域
本发明涉及集成电路的制备方法，且尤其涉及一种沉积高介电常数材料于基材上的方法，借此提供一适合高介电常数材料沉积的界面层，还涉及制备栅极介电结构时沉积高介电常数材料的方法。 
背景技术
目前需要缩小(降低)半导体元件的尺寸，以增加半导体芯片之上的元件密度，使得半导体元件操作得更快且消耗较少的功率。 
二氧化硅最常作为半导体元件的栅极介电材料。然而，将二氧化硅应用作为栅极介电材料时，随着二氧化硅厚度的下降，伴随对氧化过程的严格限制。使用这些介电材料时，是需要控制整个晶片的次埃(sub-angstrom)均匀度与厚度的。 
再者，当介电层厚度降低的同时，量子穿隧效应(quantum tunneling effects)倾向增加，造成不想要的电流流经栅极与沟道之间。 
近来关于降低元件的尺寸，许多研究已经致力于开发另一种介电常数材料，其形成的厚度大于二氧化硅，且仍然具有相同的场效表现。这些材料通常称为高介电常数(high-k)材料，因为其介电常数值高于二氧化硅的介电常数值(3.9)。 
此种高介电常数(high-k)材料的相对性能通常表示为等效氧化层厚度(Equivalent oxide thickness，EOT)，因为此种替代材料层可以更厚，但其仍然提供与相对较薄的二氧化硅层同样的电性效果。 
然而，使用较高介电常数材料的缺点在于，其容易提供较差品质的界面。较差品质的界面容易损害最终栅极电极微结构的电性表现，在上述例子中，高介电常数材料直接沉积于硅基材之上。 
因此，公知技术WO2005/013349中提及介电材料(例如二氧化硅或类似的材料)可提供一缓冲层(或界面或桥梁)介于半导体晶片和高介电常数材料之间，当使用高介电常数材料时，用以改善其电性表现。 
不幸地，很难发展超薄的界面层(例如厚度低于10埃)，且又具有均匀性。 
缺乏均匀性可能会损害最终元件的电性特性。 
为了整合高介电常数材料到目前CMOS制造工艺系统中，良好品质(平坦、平滑、均匀且展现连续界面氧化物成长)的界面层将有利于半导体基材和高介电常数材料的界面。 
此处的挑战在于，将半导体晶片基材(特别是二氧化硅晶片基材)和高介电常数材料之间的界面层品质最佳化，因该处的品质将决定最终晶体管的性能表现与可靠度(reliablity)。 
发明内容
本发明的目的之一就是提供一种改善且替代的方法，其能解决公知技术的缺点。 
本发明的另一目的就是提供一种方法，其特别能产生一种均匀超薄的界面层，此界面层适合沉积具有高介电常数的材料(例如高介电常数(high-k)材料)。 
再者，本发明的目的在于改善介于半导体基材(或晶片)和介电层之间的界面，特别是沉积一高介电常数材料于基材之上。 
本发明提供一种高介电常数栅极介电材料的形成方法，包括下列步骤：提供一半导体基材；清洗该基材；对该基材进行一热处理，其中该热处理于一无氧化环境中进行，导致形成一薄界面层；以及沉积一高介电常数材料于薄界面层之上。 
优选地，上述清洗基材包括一最终的氢氟酸处理。 
优选地，在本发明的方法中，热处理的温度约高于700℃，较佳约高于1000℃，更佳约高于1050℃。 
优选地，在本发明的方法中，其中该无氧化环境包括一钝气，更佳包括氦气及/或氩气。 
优选地，在本发明的方法中，还包括加入部分氢气到无氧化环境中。 
优选地，在本发明的方法中，其中该部分氢气的体积约少于10％，较佳约介于1％～10％。 
优选地，该无氧化环境中不包括氮气。 
优选地，在本发明的方法中，其中热处理的时间约少于2分钟，较佳约少于1分钟，更佳约少于40秒。 
优选地，依照本发明的方法，其中在热处理之后，形成一薄化学氧化层。 
优选地，上述的薄化学氧化层的形成借助施加一湿式臭氧(O3)/最终去离子水(DIW)处理或一UV增强式氧化物成长法(UV-enhanced oxide growthmethod)。 
优选地，依照本发明的方法中，其中高介电常数材料为任何一种介电常数值(k)高于二氧化硅的介电材料。 
优选地，上述的高介电常数材料借助原子层沉积法(Atomic LayerDeposition)沉积而得。 
优选地，在本发明的方法中，其中沉积该高介电常数材料之后，接着进行一沉积后退火处理。 
优选地，上述的薄界面层的厚度较佳约少于0.6nm。 
依照本发明所述的方法，可用于形成高介电常数栅极介电材料。 
优选地，上述的半导体元件，其包括一高介电常数栅极介电材料，其中高介电常数栅极介电材料包括一约少于0.6nm的薄界面层。 
依照本发明的方法，能产生均匀且薄的、具有适当的末端(例如OH键)的界面层，使其能够相容于后续高介电常数(high-k)材料的沉积。 
再者，实行本发明的方法，能改善界面层的粗糙度与品质。 
同时，在本发明的结构下，能增进在半导体元件中的电荷载流子迁移率。 
为让本发明的上述和其它目的、特征、和优点能更明显易懂，下文特举出优选实施例，并配合附图，作详细说明如下： 
附图说明
图1为一系列流程图，用以说明依照本发明的方法制备表面的流程。 
图2为利用角度解析X-光光电子光谱仪(AR-XPS)测量的厚度图，用以显示本发明的界面层与用不同方法沉积的高介电常数(high-k)材料HfO2层的厚度。 
图3显示HfO2覆盖率相对于氧化物厚度。 
图4借助光学测厚仪测量依序形成的氧化层厚度。
图5借助原子力显微镜确认表面粗糙度。 
图6显示利用不同表面处理而得的电容对应电压图。 
图7显示形成薄界面层可能的机制。 
具体实施方式
本发明基于意外发现一实行本发明的方法，包括在含有钝气的无氧化环境中进行热处理，以形成一薄界面层。 
本发明所谓的“无氧化环境”是指没有氧气的环境。此环境较佳包括一钝气环境或钝气混合物，以及视需要地包括其它添加剂。 
特别是，添加氢气在包含钝气环境或钝气混合物的无氧环境中，可增加上述薄界面层的表面平滑度。 
在本发明中，热处理的步骤进行于清洗基材之后，以及未沉积高介电常数材料之前。 
本发明所谓的“高介电常数”是指任何介电材料，其具有一介电常数值k(相对于真空下)高于3.9(此为二氧化硅的介电常数)，且较佳高于8.0。 
在包含钝气的无氧化环境中施加热处理，会形成一薄界面层。 
上述的界面层可能包括氧化硅和次氧化物(SiOx，0<x≦2)。 
本发明新颖之处在于形成一均匀(平滑或平整)薄的(厚度小于10埃)界面层，其具有合理的缝隙(leakage)且能增强电荷载流子(charge carrier)的迁移率，然而使用公知技术却会得到低品质的界面层(粗糙(既不平整，不平滑，也不均匀)且没有连续的界面氧化层成长)，造成较高的缝隙(leakage)与较高的界面陷阱密度(interface trap density，Dit)，且最终结果造成半导体元件较差的性能表现。 
已知当裸硅基材上暴露于含有氧气的环境中时，自身氧化层(nativeoxide)会成长于裸硅基材上。 
此种自身氧化层本质上是SiO和SiO2的异质混合物。 
此种自身氧化层的品质与厚度在整个基材表面上是不一致的，因此，在硅基材表面上的这些自身氧化薄膜会阻碍对超薄栅极氧化薄膜厚度的准确控制。 
因此，除了清洁其它物质以外，主要用于清洁基材上的自身氧化物，以 避免污染以及为了产生优异的电性表现。 
清洁基材经常包括最终的氢氟酸(HF)疏水处理，用以抑制氧自由基(redical)和硅结合。 
上述的最终氢氟酸疏水处理，也称为IMEC-foob，是先使用臭氧和去离子水(O3/DIW)的氧化步骤，接着使用一氧化物移除步骤(使用HF/HCl)。最后，用去离子水(去离子水掺盐酸)润洗，再进行含有异丙醇和氮气的马南哥尼干燥法(Marangoni drying)。 
此最终氢氟酸处理(IMEC-foob)造成表面无氧化物。 
但是，经由最终氢氟酸(IMEC-foob)的清洁所产生的无氧化物的表面，其无法提供适合后续沉积高介电常数(high-k)材料所需要的末端OH键。 
因此，本发明建议基材经过清洁步骤后，接着在无氧化环境中进行一热处理。 
上述的热处理会形成一均匀薄氧化物及/或次氧化物的界面层，其位于栅极介电层与半导体基材之间。 
上述薄界面氧化物/次氧化物层，又称为钝气中薄界面层，借助在无氧化环境中施加一热处理而得。 
图1为一流程图，用以说明依照本发明的方法在半导体制备过程中的各阶段步骤。 
上述方法中包括在半导体主体中形成隔离结构，例如浅沟隔离结构(Shallow Trench Isolation，STI)。 
开始制备栅极的步骤，首先进行一最终氢氟酸疏水处理以清洁半导体主体的上表面，此清洗步骤进行于无氧化环境中进行热处理步骤之前。 
在一包括钝气的无氧化环境中，进行上述热处理步骤以产生高品质薄界面层于半导体主体之上。 
接着，视需要地形成一化学氧化物，借助湿式O3/最终去离子水(DIW)清洁处理(也称为IMEC-clean)或UV增强氧化物成长法，造成表面具有一薄化学氧化层。 
当界面层形成之后，高介电常数(high-k)栅极介电层沉积于界面层之上。此高介电常数(high-k)栅极介电层可包括一层或多层高介电常数(high-k)介电材料。
视需要地对高介电常数(high-k)介电材料进行一沉积后退火处理。 
一导电金属栅极接触(或栅极电极)形成于高介电常数(high-k)栅极介电层之上，因而形成栅极结构或栅极堆叠。 
此栅极电极可包括一层或多层导电材料。 
再者，多晶硅覆盖层(capping layer)沉积于栅极接触之上。 
栅极接触、高介电常数(high-k)栅极介电层与界面层接着一起被图案化形成一栅极结构。 
借助离子注入、扩散掺杂适当的n或p杂质，以形成半导体主体的源极/漏极区域并进行内连线工艺。 
当形成浅沟隔离结构时，借助干式蚀刻于基材中形成沟槽，再填充介电材料以提供电性的绝缘。 
此栅极介电材料可以是一高介电常数(high-k)材料，例如氧化铪，氧化铝或氧化锆。 
栅极电极(或栅极接触)可由半导体材料构成，例如多晶硅、硅化锗、锗、金属硅化物或择自于下述群组的金属材料：金属、金属氮化物、金属碳氮化物以及上述的组合(例如钛(Ti)、钽(Ta)、钨(W)、钌(Ru)、氮(碳)化钛(Ti(C)N)、氮(碳)化钽(Ta(C)N)、氮(碳)化钨(W(C)N)。 
栅极结构分隔两侧的源极与漏极，其中源极与漏极接触沟道区域(channel region)的相对两侧。 
侧壁间隔物(sidewall spacer)形成栅极结构侧壁，侧壁间隔物通常与源极和漏极的边界对齐。这些侧壁间隔物可由例如氧化硅、氮化硅及/或碳化硅所组成。 
依照本发明的一个优选实施例，形成高介电常数(high-k)栅极介电材料的方法，包括以下步骤：提供一半导体基材，清洗该基材，在无氧化环境中进行一热处理，以及接着沉积一高介电常数(high-k)材料。 
依照本发明的方法，在无氧化环境中进行一热处理，尚包括钝气混合物，造成一薄界面层的形成。 
再者，此均匀薄界面层，由施加热处理而得，其具有适合的表面末端，因此能使表面适合高介电常数(high-k)材料的沉积，且减少EOT。 
上述的均匀薄界面层，提供改良的界面特性，此界面层介于硅结构与高 介电常数(high-k)材料之间，借助下述沉积步骤而得。 
在包含钝气混合物的无氧化环境中进行的热处理，较佳进行在一快速热处理(rapid thermal process，RTP)腔体中。 
上述热处理进行于约高于700℃的温度，较佳约高于1000℃，更佳约高于1050℃。 
上述热处理的期间较佳约少于2分钟，更佳约少于1分钟，又更佳约少于40秒。 
依照本发明的方法，热处理可以进行于炉管中(例如LPCVD低压化学气相沉积反应炉)，或使用瞬间退火(spike anneal)。当在LPCVD反应炉中进行热处理时，需要较长期间(至少10分钟至几小时)，而瞬间退火一般约在1050℃中进行1秒钟。 
进行热处理期间，一包括氧化硅与次氧化物(SiOx，0<x≦2)均匀薄的层被揭开(unraveled)于基材表面上。 
进行热处理期间，上述的无氧化环境的钝气较佳为氦气(He)及/或氩气(Ar)。 
氮气不适合加入无氧化环境中，当其并入于界面且增加界面状态密度时，会导致沟道迁移率的降低，影响此元件的电性特性。 
优选地，加入部分氢气到包括钝气的无氧化环境中。 
优选地部分氢气的体积约少于10％，较佳介于1～10％之间。 
无氧化环境的压力较佳介于10到20托耳(torr)。 
依照本发明的方法，会获得薄界面层的厚度约少于0.6nm。 
再者，依照本发明的方法获得的高品质界面层，其平整(或平滑或均匀)且呈现连续的界面氧化物成长。 
在本发明的方法中，形成上述的薄界面层，接着后续沉积一高介电常数(high-k)材料。 
上述的高介电常数(high-k)材料的沉积可使用本领域普通技术人员所知的沉积技术，较佳为原子层沉积法(Atomic Layer Deposition，ALD)、金属有机气相沉积法(Metal-Organic Chemical Vapor Deposition，MOCVD)、分子束外延法(Molecular Beam Epitaxy，MBE)、化学气相沉积法(Chemical VaporDeposition，CVD)或物理气相沉积法(Physical Vapor Deposition，PVD)。
高介电常数(high-k)材料的例子包括，但不限于二元的金属氧化物，包括ZrO2、HfO2、La2O3、Y2O3、TiO2，以及其硅化盐类和铝酸盐类；金属氧氮化物包括AlON、ZrON、HfON、LaON、YON等，以及其硅酸盐和铝酸盐类例如ZrSiON、HfSiON、LaSiON、YSiON；钙钛矿型的氧化物，包括钛酸盐系统的材料，例如钛酸钡、钛酸锶、碳酸钡锶((BaSr)TiO3，BST)。 
优选地，高介电常数(high-k)材料的沉积视需要地伴随一沉积后退火处理以进一步降低界面陷阱密度(interface trap density，Dit)。 
在一实施例中，在无氧化环境中的热处理之后，立即进行高介电常数(high-k)材料的沉积步骤。 
在另一实施例中，在无氧化环境中的热处理之后，视需要地进行化学氧化成长步骤。 
化学成长氧化物是将裸露的半导体表面和较佳为薄界面层与液体及/或气体化学物接触以氧化其表面。 
依照本发明，化学氧化物的形成较佳借助进行湿式例如臭氧(O3)/最终的去离子水(DIW)(IMEC-clean)的清洁处理或UV增强式氧化物成长法，两种方法可择一选择。 
上述的湿式臭氧(O3)/最终去离子水(DIW)清洁，也称为IMEC-cleam，是先使用臭氧和去离子水(O3/DIW)，接着使用一氧化物移除步骤(使用HF/HCl)。最后，用臭氧化的去离子(臭氧/去离子水掺盐酸)润洗，再进行含有异丙醇和氮气的马南哥尼干燥法(Marangoni drying)。 
上述的湿式臭氧(O3)/最终去离子水(DIW)清洁(IMEC-clean)，会使表面留下一非常干净且薄化学氧化物层。 
上述的UV增强式氧化物成长法是在空气中进行UV照射以成长一薄氧化层。氩气连续地注入基材之上，以降低空气中的氧化物成长的速度。 
利用上述的UV增强式氧化物成长法而得的化学氧化层，其厚度薄于用湿式臭氧(O3)/最终去离子水(DIW)清洁(IMEC-clean)而得的氧化层。 
借助进行湿式臭氧(O3)/最终去离子水(DIW)清洁(IMEC-clean)或UV增强式氧化物成长法而得的化学氧化物层，可提供除了施加热处理所造成的效果之外，另外能使表面具有后续沉积高介电常数(high-k)材料所需要的合适的末端(例如OH键)。
因此，总氧化层来自于两种贡献，其一来自于无氧化环境中进行热处理而得的界面层，另一来自于进行湿式臭氧(O3)/最终去离子水(DIW)清洁(IMEC-clean)或UV增强式氧化物成长法而得的化学氧化层。 
只进行化学氧化物沉积，而未进行一热处理，会得到有缝隙(leakage)、较差品质的化学氧化物(对照下列讨论的图3与图6)，其不适合后续沉积高介电常数(high-k)材料，因此得到低品质的半导体元件。 
接着，视需要地进行化学氧化物形成步骤之后，进行ALD高介电常数(high-k)材料的沉积步骤。 
上述的半导体基材较佳为硅基材或包含硅晶片或硅层的绝缘层上覆硅基材(silicon-on-insulator，SOI)，例如多晶硅、外延硅或非晶硅，具有或不具有导电的掺杂物。 
上述的半导体基材可以为任何半导体基材，只要此基材能抵抗本发明所需要的高温。 
此基材可能包括各种绝缘区域，例如浅沟隔离区域(Shallow TrenchIsolation，STI)、局部氧化区(Local Oxidation of Silicon，LOCOS)或其它类似的隔离区域，其形成于基材或上述的表面上。 
图2显示依照本发明的不同表面处理步骤，由AR-XPS测量到的界面层与沉积高介电常数(high-k)介电材料HfO2的厚度。 
在图2中的界面层(interfacial layer，IL)，是借助于无氧化环境中的热处理而得的，或借助化学氧化物成长法搭配或不搭配前者之热处理而得的。 
图2中标出热处理法不同的条件，包括无氧化环境的成份与温度。 
上述化学氧化层借助进行湿式臭氧(O3)/最终去离子水(DIW)清洁(IMEC-clean)或UV增强式氧化物成长法(图2中标示为UV/Air/Ar)而得。 
图2显示界面层与高介电常数(high-k)的HfO2材料层两者只进行热处理步骤，两者的厚度具有非常好的结果。 
例如H2/He/1050℃热处理与He/1050℃热处理形成超薄的界面层，其厚度分别为0.4nm和0.5nm。 
再者，如图2所示，H2/He/1050℃热处理帮助限制后续的化学氧化物成长。 
因此，依照本发明的方法可用于达到EOT缩小化。
借助进行热处理搭配UV增强式氧化物成长法所形成的界面层，其总氧化物的厚度也少于只利用UV增强式氧化物成长法所得的厚度。 
但是，如图3所示，相较于热处理搭配UV增强式氧化物成长法，进行UV增强式氧化物成长法得到较低的HfO2覆盖率(coverage)。可能的解释在于，UV增强式氧化物方法无法在表面上显示足够的、合适的活化功能基末端(例如OH键)，因此对于后续高介电常数(high-k)材料沉积步骤时，表面为粗糙且低品质成核层(nucleation)，因此，造成后续元件的电性特性出问题。 
的确，图3显示依照本发明的方法，其HfO2覆盖率对应氧化物的厚度关系图。 
借助进行热处理，与视需要地进行化学氧化物形成法(UV增强式氧化物成长法或湿式臭氧(O3)/最终去离子水(DIW)清洁(IMEC-clean))。 
形成上述界面层后，进行例如5次ALD HfO2单层沉积的循环。 
一般的ALD技术与HfO2的ALD对界面层表面条件特别敏感，因此，进行HfO2的ALD时，依据界面层的粗糙度、界面层表面的活性功能基末端(例如OH键)与界面层的连续性/均匀性(例如无岛状类似物)对界面层的品质进行评估。 
据此，具有较多OH功能基末端且较平滑(较低粗糙度)的界面层表面，较有利于HfO2的ALD沉积。 
如图3所示，借助热处理形成界面层(不论搭配或不搭配进行UV增强式氧化物成长法)提供较佳的HfO2覆盖率，因此为较佳品质、平滑的界面层。 
上述的HfO2覆盖率也高于利用臭氧(O3)/最终去离子水(DIW)化学氧化物成长法(不论搭配或不搭配热处理形成界面层)而得的HfO2覆盖率，且特别能改善只进行UV增强式氧化物成长法获得的较差的覆盖率。 
图4显示依照本发明的不同表面处理步骤而依序成长(step-by-step)的氧化层厚度(借助光学测厚仪(Ellipsometry)测量)。 
每一次进行清洁步骤(IMFOOB)后，在无氧化环境中进行热处理或一化学氧化物成长(湿式臭氧(O3)/最终去离子水(DIW)清洁(IMEC-clean)或UV/Air/Ar)，或上述的组合。 
由热处理所形成的界面层，图4中指出不同的实验条件，包括无氧化环境的组成和温度。
化学氧化物由UV增强式氧化物成长法或由湿式臭氧(O3)/最终去离子水(DIW)清洁(IMEC-clean)而得。 
图4测出的总氧化层厚度，包括在无氧化环境中进行热处理而得的界面层，与由UV增强式氧化物成长法或由湿式臭氧(O3)/最终去离子水(DIW)清洁(IMEC-clean)而得的化学氧化物层。 
在此须注意的是，由光学测厚仪所测的氧化层厚度，其准确度不如由AR-XPS所测。 
事实上，由光学测厚仪所测的厚度会厚于由AR-XPS所测的厚度。 
但是，图4所显示的趋势符合图2的结果。 
图5显示借助原子力显微镜(Atomic Force Microscope，AFM)测得的表面粗糙度。 
图5所测量为进行热处理而得的界面层及/或进行氧化物成长法而得的化学氧化物。 
由热处理形成的界面层，图5中指出不同的实验条件，包括无氧化环境的组成和温度。 
化学氧化物由UV增强式氧化物成长法或由湿式臭氧(O3)/最终去离子水(DIW)清洁(IMEC-clean)而得。 
如图5所示，只由UV增强式氧化物成长法或只由湿式臭氧(O3)/最终去离子水(DIW)清洁(IMEC-clean)而得的化学氧化层，不进行热(预)处理形成界面层，会得到相对较粗糙的氧化层表面。例如，由湿式臭氧(O3)/最终去离子水(DIW)清洁(IMEC-clean)而得的化学氧化层，其Rms＝0.18nm，而由UV增强式氧化物成长法而得的化学氧化层，其Rms＝0.14nm，其中每一次Rms测量的范围为1×1μm。 
相反地，进行H2/He/1050℃热处理形成界面层有助于平滑界面层的表面，且当化学氧化层沉积于其上时，对于1×1μm的范围，Rms值达到0.08～0.09nm。 
再者，低温处理(例如700℃)将会降低表面平滑度的表现(对于1×1μm的范围，Rms＝0.146nm)。 
如图6所示，只进行热处理，或只有化学氧化物成长，或结合热处理与化学氧化物成长(UV增强式氧化物标示为UV/Air/Ar/1s)所得的元件的电容 对应电压曲线图。 
电容(MOS)为一种P型基材，其具有TaN/TiN金属栅极电极。 
进行H2/He/1050℃的热处理及/或进行UV增强式氧化物成长法，接着借助40次ALD单层HfO2沉积循环。 
由图6得知，只进行UV增强式氧化物成长法会得到非常多缝隙(leakage)，且薄氧化层。 
此种多缝隙(leakage)可由形成第一界面层所抑制，不论搭配或不搭配UV增强式氧化物成长法。 
图7显示形成薄界面层可能的机制。包括HF-last疏水性处理的清洁步骤，会留下氢原子末端的表面(Si-H键，如图7a)，此会抑制氧原子自由基与硅上层结合。有水的存在时(润洗过程中)，溶氧及/或OH-自由基可能攻击内层的Si-Si键，而不破坏Si-H键，留下SiOx次氧化物于(无氧化物)表面之下。当进行热处理期间，包含氧化硅与次氧化物(SiOx，0<x≦2)的薄层被揭开(unraveled)于硅表面上(图7b)。此薄层是连续的(没有岛状物形成)，均匀且疏水性，是一种适合介于基材和借助ALD沉积高介电常数(high-k)材料(例如Hf氧化物)之间的界面层。 
因此，依照本发明的方法，产生一均匀超薄界面层，其位于高介电常数材料(high-k)底下。 
依照本发明的方法，能产生均匀且薄的、具有适当的末端(例如OH键)的界面层，使其能够相容于后续高介电常数(high-k)材料的沉积。 
再者，实行本发明的方法，能改善界面层的粗糙度与品质。 
同时，在本发明的结构下，能增进在半导体元件中的电荷载流子迁移率。 
虽然本发明已以数个优选实施例揭示如上，然而其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视所附的权利要求书所界定的范围为准。

Claims (22)

1.一种高介电常数栅极介电材料的形成方法，包括下列步骤：
提供一半导体基材；
清洗该基材；
对该基材进行一热处理，其中该热处理于一无氧化环境中进行，导致形成一薄界面层；以及
沉积一高介电常数材料于该薄界面层之上。
2.如权利要求1所述的高介电常数栅极介电材料的形成方法，其中清洗该基材包括一最终的氢氟酸处理。
3.如权利要求1或2所述的高介电常数栅极介电材料的形成方法，其中该热处理的温度高于700℃。
4.如权利要求1或2所述的高介电常数栅极介电材料的形成方法，其中该热处理的温度高于1000℃。
5.如权利要求1或2所述的高介电常数栅极介电材料的形成方法，其中该热处理的温度高于1050℃。
6.如权利要求1所述的高介电常数栅极介电材料的形成方法，其中该无氧化环境包括一钝气。
7.如权利要求1所述的高介电常数栅极介电材料的形成方法，其中该无氧化环境包括氦气及/或氩气。
8.如权利要求1所述的高介电常数栅极介电材料的形成方法，其中还包括加入部分氢气到该无氧化环境中。
9.如权利要求8所述的高介电常数栅极介电材料的形成方法，其中该部分氢气的体积少于10％。
10.如权利要求8所述的高介电常数栅极介电材料的形成方法，其中该部分氢气的体积介于1％～10％。
11.如权利要求1所述的高介电常数栅极介电材料的形成方法，其中在该无氧化环境中不包括氮气。
12.如权利要求1所述的高介电常数栅极介电材料的形成方法，其中该热处理的时间少于2分钟。
13.如权利要求1所述的高介电常数栅极介电材料的形成方法，其中该热处理的时间少于1分钟。
14.如权利要求1所述的高介电常数栅极介电材料的形成方法，其中该热处理的时间少于40秒。
15.如权利要求1所述的高介电常数栅极介电材料的形成方法，其中在该热处理之后，形成一薄化学氧化层。
16.如权利要求15所述的高介电常数栅极介电材料的形成方法，其中该薄化学氧化层的形成借助施加一湿式臭氧(O3)/最终去离子水(DIW)处理或一UV增强式氧化物成长法。
17.如权利要求1所述的高介电常数栅极介电材料的形成方法，其中该高介电常数材料为任何一种介电常数值高于二氧化硅的介电材料。
18.如权利要求1所述的高介电常数栅极介电材料的形成方法，其中该高介电常数材料借助原子层沉积法沉积而得。
19.如权利要求1所述的高介电常数栅极介电材料的形成方法，其中沉积该高介电常数材料之后，接着进行一沉积后退火处理。
20.如权利要求1所述的高介电常数栅极介电材料的形成方法，其中该薄界面层的厚度少于0.6nm。
21.一种半导体元件，其包括依照权利要求1所述的方法所形成的高介电常数栅极介电材料。
22.一种半导体元件，其包括一高介电常数栅极介电材料，其中该高介电常数栅极介电材料包括一少于0.6nm的薄界面层。
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