CN101404274A - Lead frame, packaging structure and packaging method for packaging three-pin electronic component - Google Patents
Lead frame, packaging structure and packaging method for packaging three-pin electronic component Download PDFInfo
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- CN101404274A CN101404274A CNA2008101775134A CN200810177513A CN101404274A CN 101404274 A CN101404274 A CN 101404274A CN A2008101775134 A CNA2008101775134 A CN A2008101775134A CN 200810177513 A CN200810177513 A CN 200810177513A CN 101404274 A CN101404274 A CN 101404274A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12032—Schottky diode
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention discloses a lead frame and a packaging structure for packaging a three-pin electronic device and a packaging method thereof. The lead frame comprises a closed frame and three pins; a chip bearing board and ends of a second pin and a third pin are positioned inside an electronic device packaging area, and in the packaging area, the ratio of the area of the chip bearing board to the total area of the end parts of the second pin and the third pin is 4-6. The lead frame changes the area of the chip bearing boards in the prior art, and enlarges the area of the boards to an appropriate extent. A packaged and shaped product has a size same as that of a product produced by a conventional frame, but the power can be improved greatly, therefore, the lead frame solves the problems that the number of bonding rods of an internal lead is limited and the stress relief rate of the chip is different from that of the frame owing to the difference of the materials of the chip and the frame.
Description
Technical field
The present invention relates to have the electronic device encapsulation technical field of three pins, the microminiaturized three-pin electronic component encapsulation of particularly a kind of surface-adhered type lead frame, encapsulating structure and method for packing thereof.
Background technology
Development characteristic about electronic device is in recent years, on the one hand, the electronic device product has entered period of upgrading rapidly, its outstanding behaviours be by plug-in mounting to surface-assembled, by simulated to digitlization, by fixed to portable, by separate type to integrated transformation.Its objective is the miniaturization that makes the product size compactness, realizes discrete device, shorten the design cycle, and reduce the parasitic parameter etc. of interconnecting lead.On the other hand, energy-conservation is the industry trend of the times, and the market challenges that discrete device faced is that essential the continuation improved efficiency, and is easy to use and adopts advanced encapsulation.
The conduction of field effect transistor and voltage stabilizing circuit product and switching loss are continuing towards the littler form development of footprints and encapsulate also all in continuous reduction at present.These two kinds of variations are reflected in the semiconductor three-pin electronic component and make, and show that mainly packing forms develops to chip components such as SOT-23, SOT-89 from plug-in mountings such as TO-92, TO-126, TO-220.Wherein the SOT-23 encapsulation is with its thin thickness, overall volume is little, be easy to advantages such as assembling and receive increasing concern, for example in the mobile phone manufacturing, the mobile phone of a new generation advances towards frivolous and integrated multi-functional direction, requires supporting with it components and parts production firm constantly to release the miniaturization of suitable mobile phone enterprise demand, highly integrated, components and parts cheaply.In order to tackle this variation, the electronic device of miniaturization, integrated, high frequency, Gao Rong will be widely used, and along with the increase that mounts density, the use amount of chip device will be increased sharply.
Solved the miniaturization of semiconductor three-pin electronic component, integrated problem largely though chips such as SOT-23 are encapsulated in, improving device power how under the prerequisite of reduced volume does not in the industry cycle still have good solution so far.
In three-pin electronic component was made, device power depended on the area of chip itself to a great extent, and area is big more, the puncture voltage that chip bears is also big more, the power of device is also big more, and this is by the decision of the physical property of chip itself, is irreversible to a certain extent.
In the manufacture process of three-pin electronic component, normally produce lead frame earlier, the structure of conventional SOT-23 chip encapsulation usefulness lead frame 1a as shown in Figure 1, the termination of one of them pin 120a is for carrying central layer 11a, carrying central layer 11a is rectangle, in the middle of being positioned at, and two pin 121a are not connected with a year central layer 11a with 122a in addition.After having made lead frame, plate high-conductivity metal to carrying the position that central layer 11a and three pins be used to weld lead, as silver, silver coating shadow region as shown in Figure 2.Then chip 2a is bonded on year central layer 11a of lead frame 1a; Then with the end pressure welding of two lead 3a on chip 2a, an end pressure welding couples together with corresponding pin with the mode of the lead electrode with chip, as shown in Figure 2 on the pin 121a and 122a on the lead frame 1a; Use encapsulating material that chip and lead are sealed at last, packaging area is made the three-pin electronic component finished product shown in the frame of broken lines among Fig. 1,2.
Conventional SOT-23 chip encapsulation is generally 0.904 * 0.814mm with the central layer area that carries of lead frame
2, that is to say that conventional chip encapsulation must be less than above-mentioned size with the chip area of pasting on the lead frame, like this, the power of device gets off by carrying the central layer fixed size within the specific limits.Except carrying central layer size power-limiting, because year central layer area of conventional SOT-23 lead frame is less, need carry on the central layer the also device of pressure welding lead-in wire for some like this, glue that the silvered face of remainder is far from being enough behind the chip, so the quantity of pressure welding lead is restricted.Also have a problem to be at last, because the material of chip is different with the material of framework, both Stress Release speed also is different, area of chip is big more, both difference are also big more, be fatal after this difference reaches to a certain degree, it can cause chip to crack, even chip is come off from carrying central layer.
Summary of the invention
The technical problem to be solved in the present invention is, proposes a kind of three-pin electronic component encapsulating structure and lead frame is used in encapsulation, can effectively improve the power of three-pin electronic component.
Another technical problem that the present invention will solve is, proposes a kind of three-pin electronic component encapsulating structure and encapsulate to use lead frame, can effectively improve the quantity of pressure welding lead.
In addition, the another technical problem that the present invention will solve is, proposes a kind of three-pin electronic component method for packing, can effectively solve the problem of Stress Release in the quantity of the power that effectively improves three-pin electronic component, raising pressure welding lead.
In order to solve the problems of the technologies described above, the invention provides a kind of three-pin electronic component encapsulation lead frame, comprise closed frame and three pins, wherein the termination of first pin is for pasting the central layer that carries of chip, the end tail is connected with the upper side frame one of closed frame, second, the termination of three pins lay respectively at described year central layer left and right sides and with carry central layer and isolate, the end tail is connected with the lower frame one of closed frame respectively, described year central layer and second, the termination of three pins is positioned at the electron device package intra-zone, in described encapsulation region, the ratio of the area sum of the area of year central layer and the end portion of second pin and the 3rd pin is 4～6.
By above-mentioned structure, the area that make to carry central layer than the area that carries central layer of existing standard increase greatly (such as conventional SOT-23 chip component, its year central layer area and the termination of second pin and the 3rd pin area with ratio only be 0.7.), therefore area of chip bonding on it can be enlarged, thereby the power of chip can be effectively improved.
The encapsulation of above-mentioned three-pin electronic component is with in the lead frame, and described year central layer is rectangle, and the angle is provided with outstanding wing plate on two in rectangle, is positioned at and the top of carrying the second and the 3rd pin termination that central layer separates.It is in order to give the position of staying the pressure welding lead at described year on the central layer, also to have increased the area of year central layer simultaneously that wing plate is set.
Further, two inferior horns of described year central layer are oblique line or circular arc type chamfering, and corresponding to described chamfering, second and third pin has corresponding transition oblique line or arc section respectively.Because the width of the end tail spacing of the second and the 3rd pin and encapsulation region and highly be according to element require changeless, increase the area of the area of year central layer with regard to corresponding minimizing second of palpus and the 3rd pin termination, the termination width of the width of central layer with regard to corresponding second and third pin of minimizing of palpus carried in increase.When the width that carries central layer was increased to certain limit, the termination spacing that can make the second and the 3rd pin was greater than end tail spacing.In order to keep being connected of second and third pin termination and end tail, two inferior horns having taked rectangle is carried central layer change the practice of 45 degree oblique lines or circular arc type chamfering into by an angle of 90 degrees, and second and third pin termination and end tail are coupled together by corresponding transition oblique line or arc section.
Increased after the wing plate, having satisfied needs at the product requirement that carries solder taul on the central layer, and has increased the area of dissipation of year central layer, has further improved the dissipation power value of element.Wherein, described dissipation power value is meant that electronic device can bear and the maximum power that do not burn out.Foregoing power also is meant dissipation power.
In addition, the described closed frame that is made of first, second and third pin is an encapsulation unit, a plurality of encapsulation units are connected as a single entity by frame laterally and/or longitudinally, the lead frame group that formation can be rolled, launch, to be applicable to plating, to paste working continuously of production lines such as chip, solder taul, encapsulation, enhance productivity.
The present invention also provides a kind of three-pin electronic component method for packing, may further comprise the steps:
Step 3, paster.With year central layer metal face of weld of chip attach, on silvered face at lead frame;
Step 4, the welding lead.By lead chip and corresponding pin termination are coupled together;
Step 5, encapsulation.Use encapsulating material will carry termination (comprising chip and all leads) encapsulation of central layer and second and third pin.
In addition, for the problem of Stress Release, also comprise step 6 after step 5, that is: the product after the sealing is carried out front and back annealing and heat ageing, wherein, the condition of preceding annealing is: temperature is 250 ℃-150 ℃, and the duration is 1.5-2.5 hour; The condition of after annealing is: temperature is 200 ℃-100 ℃, and the duration is 6-18 hour; The condition of heat ageing is: temperature is 220 ℃-100 ℃, and the duration is 6-18 hour.
More specifically, in step 4, also comprise and chip respective electrode and the wing plate that carries central layer to be coupled together with lead according to the needs of chip.Weld metal layers in step 2 can be argent, and the lead material in step 4 can be metallic gold or copper, and the two can adopt hot ultrasonic bonding equipment to weld.
The present invention also provides a kind of three-pin electronic component encapsulating structure that is formed by the said method encapsulation.
By above-mentioned improved lead frame and encapsulating method, under the condition of the external dimensions that does not change whole lead frame, make the area that carries central layer of this three-pin electronic component increase 100%, improved the dissipation power of chip.Product size behind the encapsulated moulding is consistent with the product of conventional framework production like this, but power can improve a lot.In addition, the present invention breaks the normal procedure, change the design that conventional framework carries the central layer rectangle, on the basis of original rectangle, add wing plate, so when needed, just lead can be pressed onto on the wing plate, solve the restricted problem of lead pressure welding bar number smoothly, and,, solved different both the different problems of Stress Release speed that produce of material owing to the material of chip and framework by condition suitable front and back annealing and heat ageing.
Below in conjunction with the drawings and specific embodiments technical scheme of the present invention is described in detail.
Description of drawings
Fig. 1 is the structural representation that lead frame is used in the encapsulation of SOT-23 chip in the prior art;
Fig. 2 is a SOT-23 chip encapsulating structure schematic diagram in the prior art;
Fig. 3 is the structural representation of an embodiment of lead frame of the present invention;
Fig. 4 is the structural representation of an embodiment of three-pin electronic component encapsulating structure of the present invention;
Fig. 5 is the structural representation that is applicable to the three-pin electronic component encapsulation of continuous productive process with another embodiment of lead frame of the present invention;
Fig. 6 is the process chart of an embodiment of method for packing of the present invention;
The three-pin electronic component that Fig. 7 forms for the encapsulation through the method for the invention.
Fig. 8 is the lead frame schematic diagram of the present invention after silver-plated.
Embodiment
As shown in Figure 3, be the structural representation of an embodiment of lead frame provided by the invention.This lead frame comprises closed frame 1 and three pins 120,121,122, and wherein the termination of first pin 120 is for carrying central layer 11, and central layer 11 was a rectangle in described year, and the end tail of first pin extends to the top of frame 1, is connected with frame 1 one.The termination of second and third pin 121,122 lays respectively at the left and right sides of carrying central layer 11, separates with a year limit, central layer 11 left and right sides, and second and third pin 121,122 end tails extend to the bottom of frame 1, are connected with frame 1 one.
In addition, central layer 11 also comprised two wing plates 110,111 that protrude in described year central layer 11 in above-mentioned year, wherein, wing plate 110 is outstanding to be positioned at and to carry central layer 11 top of the termination of the second adjacent pin 121 side by side, and separate with the termination of pin 121, wing plate 111 is outstanding to be positioned at and to carry central layer 11 top of the 3rd adjacent pin 122 side by side, and separates with the termination of pin 122.It is in order to give the position of staying the pressure welding lead at described year on the central layer, can with lead chip respective electrode and the wing plate that carries central layer to be coupled together according to the needs of chip that wing plate is set.Also increased simultaneously the area of year central layer.For example, the area of described year central layer is 1.6 * 1=1.6mm
2, two termination areas are about 0.3 * 0.6 * 2=0.36mm
2, as not having wing plate, the area of year central layer is about 4.4 with the ratio of two termination area sums; If any wing plate, then carry central layer and be about 1 * 1.6+0.4 * 0.25 * 2=1.8mm
2, then the ratio of the two is about 5.
As shown in Figure 4, chip 2 is bonded on the silvered face that carries central layer 11 (silvered face is shadow region shown in Figure 4), chip 2 has three utmost points, wherein, first utmost point passes through lead 31 pressure weldings on the silvered face of wing plate 110, be connected with pin 120 with this, on the silvered face of the pin 122 of lead frame, the 3rd utmost point passes through lead 33 pressure weldings on the silvered face of the pin 121 of lead frame to second utmost point by lead 32 pressure weldings.
Owing to carrying outstanding two blocks of wing plates 110,111 on the central layer 11, then can be on wing plate 110 with lead 31 pressure weldings that are connected with pin 120, and the standard wire framework of existing conventional SOT-23 chip device can not carry this wire bonding on the central layer, because the silver-plated area that carries central layer big (referring to Fig. 2) inadequately.
As shown in Figure 5, structural representation for the lead frame C that is applicable to continuous productive process, carry central layer 11, three pins 120,121,122 are formed a lead frame unit A, a lead frame assembled unit of the transversely arranged formation of a plurality of unit A B, a plurality of unit B are vertically arranged the lead frame group C that formation can be rolled, launch.
As shown in Figure 6, be the flow chart of an embodiment of method for packing of the present invention.
At first, make lead frame,, go out lead frame as shown in Figure 3, can certainly directly go out lead frame group as shown in Figure 5 according to drawing;
Then, silver-plated at the cross cut end (of a beam) that carries central layer and pin of lead frame;
Again, three-pin electronic component chip 2 is sticked on carrying on the central layer 11 of lead frame;
Then, an electrode of chip is passed through lead 31 pressure weldings on wing plate 110, be connected with pin 120 with this, with other two electrodes respectively by lead 32 pressure weldings on the termination of the pin 122 of lead frame, by lead 33 pressure weldings on the termination of the pin 121 of lead frame;
Afterwards, use encapsulating material that three-pin electronic component chip and lead are encapsulated;
At last, the product after the encapsulation is carried out front and back annealing and heat ageing, wherein, the condition of preceding annealing is: temperature is 250 ℃-150 ℃, and the duration is 1.5-2.5 hour; The condition of after annealing is: temperature is 200 ℃-100 ℃, and the duration is 6-18 hour; The condition of heat ageing is: temperature is 220 ℃-100 ℃, and the duration is 6-18 hour.
The three-pin electronic component that encapsulates through said method as shown in Figure 7.Three-pin electronic component shown in Fig. 7 is identical with three-pin electronic component of the prior art on overall dimension, but owing to changed the area of year central layer, makes it by 0.904 original * 0.814mm
2Expand 1.6 * 1mm to
2, under the condition of the external dimensions that does not change electronic device, improved the dissipation power of chip.In addition, the present invention breaks the normal procedure, and changes the design that conventional framework carries the central layer rectangle, increases wing plate on the basis of original rectangle, just can chip respective electrode and wing plate be coupled together so when needed, solve the restricted problem of lead pressure welding bar number with lead.And,, solved different both the different problems of Stress Release speed that produce of material owing to the material of chip and framework by condition suitable front and back annealing and heat ageing.
Described in the present invention three-pin electronic component can be any components and parts with three pins, as transistor, integrated regulator element, Schottky diode or the like.
It should be noted last that: above embodiment is only unrestricted in order to explanation the present invention, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, the modification that the present invention is carried out or be equal to replacement under the premise without departing from the spirit and scope of the present invention all should be encompassed in the middle of the claim scope of the present invention.
Claims (10)
1. a three-pin electronic component encapsulates and uses lead frame, comprise closed frame and three pins, wherein the termination of first pin is for pasting the central layer that carries of chip, the end tail is connected with the upper side frame one of closed frame, second, the termination of three pins lay respectively at described year central layer left and right sides and with carry central layer and isolate, the end tail is connected with the lower frame one of closed frame respectively, described year central layer and second, the termination of three pins is positioned at the electron device package intra-zone, it is characterized in that, in described encapsulation region, the ratio of the area sum of the area of year central layer and the end portion of second pin and the 3rd pin is 4～6.
2. lead frame is used in three-pin electronic component encapsulation according to claim 1, it is characterized in that in described packaging area, the ratio of the area sum of the end portion of the area of described year central layer and second pin and the 3rd pin is 4.5～5.
3. lead frame is used in three-pin electronic component according to claim 1 encapsulation, it is characterized in that described year central layer is rectangle, and the angle is provided with outstanding wing plate on two in rectangle.
4. lead frame is used in three-pin electronic component encapsulation according to claim 3, it is characterized in that described wing plate is positioned at the top of the second and the 3rd pin termination that separates with year central layer.
5, three-pin electronic component encapsulation lead frame according to claim 1, it is characterized in that described year central layer is rectangle, two inferior horns of rectangle are oblique line or circular arc type chamfering, corresponding to described chamfering, second and third pin has corresponding transition oblique line or arc section respectively.
6. three-pin electronic component encapsulation lead frame according to claim 1, it is characterized in that, the described closed frame that is made of first, second and third pin is an encapsulation unit, a plurality of encapsulation units are connected as a single entity the lead frame group that formation can be rolled, launch by frame laterally and/or longitudinally.
7. the method for packing of a three-pin electronic component is characterized in that, may further comprise the steps:
Step 1: make lead frame, the shape and structure of lead frame as claim 1-6 arbitrary as described in lead frame;
Step 2: plating weld metal layers, the cross cut end (of a beam) coating metal layer that carries central layer and second and third pin in described lead-frame packages district.
Step 3: paster, with chip attach on the metal face of weld that carries central layer of lead frame;
Step 4: the welding lead couples together chip and corresponding pin termination by lead;
Step 5: encapsulation, use encapsulating material will comprise that the termination of carrying central layer and second and third pin of chip and all leads encapsulates.
8. three-pin electronic component method for packing according to claim 7 is characterized in that, also comprises step 6 after step 5, product after the encapsulation is carried out front and back annealing and heat ageing, wherein, the condition of preceding annealing is: temperature is 250 ℃-150 ℃, and the duration is 1.5-2.5 hour; The condition of after annealing is: temperature is 200 ℃-100 ℃, and the duration is 6-18 hour; The condition of heat ageing is: temperature is 220 ℃-100 ℃, and the duration is 6-18 hour.
9. three-pin electronic component method for packing according to claim 7 is characterized in that, in step 4, also comprises and can with lead chip respective electrode and the wing plate that carries central layer be coupled together according to the needs of chip.
One kind as claim 7-9 arbitrary as described in the three-pin electronic component encapsulating structure of method encapsulation.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101775134A CN101404274B (en) | 2008-11-13 | 2008-11-13 | Lead frame, packaging structure and packaging method for packaging three-pin electronic component |
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| CN2008101775134A CN101404274B (en) | 2008-11-13 | 2008-11-13 | Lead frame, packaging structure and packaging method for packaging three-pin electronic component |
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| CN101404274A true CN101404274A (en) | 2009-04-08 |
| CN101404274B CN101404274B (en) | 2010-08-18 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102347305A (en) * | 2011-10-24 | 2012-02-08 | 上海凯虹科技电子有限公司 | Array structure of lead frame |
| CN102610585A (en) * | 2011-12-19 | 2012-07-25 | 佛山市蓝箭电子有限公司 | Lead frame for silicon chip encapsulation, encapsulation method and formed electronic element |
| CN103589980A (en) * | 2013-11-27 | 2014-02-19 | 江苏环胜铜业有限公司 | Novel lead frame material stress releasing device |
| CN106601713A (en) * | 2016-12-21 | 2017-04-26 | 长电科技（宿迁）有限公司 | Frame structure with base island capable of wire bonding at flanges, and packaging structure for frame structure |
| CN109148406A (en) * | 2018-10-24 | 2019-01-04 | 扬州扬杰电子科技股份有限公司 | A kind of ultrathin type stamp-mounting-paper diode |
| CN109478521A (en) * | 2016-07-26 | 2019-03-15 | 三菱电机株式会社 | Semiconductor device |
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2008
- 2008-11-13 CN CN2008101775134A patent/CN101404274B/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102347305A (en) * | 2011-10-24 | 2012-02-08 | 上海凯虹科技电子有限公司 | Array structure of lead frame |
| CN102610585A (en) * | 2011-12-19 | 2012-07-25 | 佛山市蓝箭电子有限公司 | Lead frame for silicon chip encapsulation, encapsulation method and formed electronic element |
| CN103589980A (en) * | 2013-11-27 | 2014-02-19 | 江苏环胜铜业有限公司 | Novel lead frame material stress releasing device |
| CN109478521A (en) * | 2016-07-26 | 2019-03-15 | 三菱电机株式会社 | Semiconductor device |
| CN109478521B (en) * | 2016-07-26 | 2022-10-11 | 三菱电机株式会社 | Semiconductor device with a plurality of semiconductor chips |
| CN106601713A (en) * | 2016-12-21 | 2017-04-26 | 长电科技（宿迁）有限公司 | Frame structure with base island capable of wire bonding at flanges, and packaging structure for frame structure |
| CN109148406A (en) * | 2018-10-24 | 2019-01-04 | 扬州扬杰电子科技股份有限公司 | A kind of ultrathin type stamp-mounting-paper diode |
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| CN101404274B (en) | 2010-08-18 |
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