CN101371354A - 倒装附着且底填充堆叠的半导体装置 - Google Patents

倒装附着且底填充堆叠的半导体装置 Download PDF

Info

Publication number
CN101371354A
CN101371354A CNA2007800029648A CN200780002964A CN101371354A CN 101371354 A CN101371354 A CN 101371354A CN A2007800029648 A CNA2007800029648 A CN A2007800029648A CN 200780002964 A CN200780002964 A CN 200780002964A CN 101371354 A CN101371354 A CN 101371354A
Authority
CN
China
Prior art keywords
reflow
band spare
external component
band
base plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2007800029648A
Other languages
English (en)
Inventor
天谷正纯
渡边雅子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CN101371354A publication Critical patent/CN101371354A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11474—Multilayer masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/1148—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/8388—Hardening the adhesive by cooling, e.g. for thermoplastics or hot-melt adhesives
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10424—Frame holders
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0191—Using tape or non-metallic foil in a process, e.g. during filling of a hole with conductive paste
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/041—Solder preforms in the shape of solder balls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/043—Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Adhesive Tapes (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明揭示一种在半导体组合件中用作载体的带件，其具有一个或一个以上聚合材料(优选为热塑性材料)的底板(101)，所述底板具有第一(101a)和第二(101b)表面。聚合粘着膜(102、104)和不同材料(优选为惰性材料)的箔片(103、105)被附着到所述底板的所述第一和第二表面侧上；其因此为所述带件提供一厚度(120)。贯穿所述带件的所述厚度形成多个孔洞；所述孔洞优选为渐细状，且与所述第二带件表面形成介于约70°与80°之间的角度。具有约等于所述带件厚度的优选直径(302)的回焊金属元件(301)被固定在所述孔洞的每一者中。

Description

倒装附着且底填充堆叠的半导体装置
技术领域
本发明大体上涉及电子系统与半导体装置的领域；且更明确地说涉及制造倒装装配、底填充且堆叠的半导体装置。
背景技术
当利用焊接凸块连接将集成电路(IC)芯片装配在具有导线的绝缘衬底(例如印刷电路母板)上时，所述芯片与所述衬底分隔一间隙；所述焊接凸块互连延伸跨越所述间隙。所述IC芯片通常是半导体，例如，硅、锗化硅或砷化镓，所述衬底经常由基于陶瓷或聚合物的材料(例如FR-4)制成。因此，芯片与衬底的热膨胀系数(CTE)之间存在明显的差异；举例来说，在硅(约2.5ppm/℃)作为半导体材料且以塑料FR-4(约25ppm/℃)作为衬底材料的情况下，CTE的差异约为一数量级。由于此CTE差异的结果，当组合件在装置使用或可靠度测试期间受到温度循环作用时，在焊接互连上，尤其是在接点区域中，产生热机械应力。这些应力可能会使接点或凸块产生疲劳，从而导致裂痕以及组合件的最终失效。任何初期的微裂痕均会在机械冲击试验(例如落下试验)中恶化。
为了在不影响电连接的情况下分散所述机械应力并强化焊点，通常在半导体芯片与衬底之间的间隙中填入聚合材料，所述聚合材料囊封凸块且填充所述间隙中的任何空间。举例来说，在国际商务机械有限公司所开发的众所周知的“C-4”工艺中，使用聚合材料来填充硅芯片与陶瓷衬底之间的间隙中的任何空间。
通常，在焊接凸块已经历回焊工艺且形成用于IC芯片与衬底之间的电接触的金属接点之后涂敷囊封剂。粘性聚合热固先驱物(有时称为“底填充物”)被施配到衬底上邻近于芯片处，且通过毛细管力而被牵引到间隙中。接着，所述先驱物被加热、聚合、以及“固化”，以形成囊封剂；在固化工艺之后，囊封剂变硬而无法再次软化。
工业中众所周知，底填充物固化工艺所需要的温度循环本身可产生热机械应力，其对于芯片和/或焊接互连可能是不利的。当组合件从回焊温度冷却到环境温度时产生额外的应力。由这些工艺步骤所产生的应力可能会造成焊点分层、使芯片的钝化层产生裂痕，或将破裂传播到电路结构中。一般来说，对集成电路的分层式结构的破裂的敏感性随着各层厚度缩减以及低介电常数绝缘体的机械弱点提高而剧烈地提高；任何初期的微裂痕均会因机械冲击试验(例如落下试验)而扩大。
发明内容
申请人已认识到需要一种具成本效益的装配方法，其中可在没有底填充工艺的有害副作用的情况下实现底填充材料的应力分散益处，进而增强装置可靠度。一技术优点在于，所述方法是否提供装置修补或再加工的机会。所述方法应一致、低成本且灵活，足以应用于不同的半导体产品系列(尤其应用于堆叠半导体装置封装)以及各种不同的设计与工艺变化。另一技术优点在于，是否可在缩短生产循环时间和增加处理量的同时实现这些创新。
本发明的一个实施例是一种用作载体的带件，其由聚合材料(优选为热塑性材料)的一个或一个以上底板组成，所述底板具有第一和第二表面。聚合粘着膜和不同材料的箔片附着到所述底板的第一和第二表面侧上；其因此为所述带件提供一厚度。形成多个孔洞以贯穿所述带件的厚度；且在所述孔洞的每一者中放置具有约等于所述厚度的优选直径的回焊金属元件。
本发明的另一实施例是一种半导体封装，其由具有一轮廓和多个接触垫的半导体装置以及另外一具有多个终端垫的外部部件制成。此部件与所述装置隔开，且终端垫分别与装置接触垫对准。回焊元件将接触垫的每一者与其各自终端垫互连。热塑性材料填充所述装置与所述部件之间的空间；此材料粘着到所述装置、所述部件以及所述回焊元件。此外，所述材料具有实质上与所述装置的轮廓一致的轮廓，且填充所述空间而实质上没有任何空隙。
当所述装置是半导体芯片时，所述外部部件是适于所述芯片的倒装装配的衬底。当所述装置是囊封经装配半导体芯片的半导体封装或封装堆叠时，所述外部部件是适于所述封装的倒装附着的板。由于填充材料的热塑特性的缘故，当达到用以进行所述回焊元件的回焊的温度范围时，可对已完成的装置进行再加工。
本发明的另一实施例是一种用于装配半导体封装的方法，其中提供具有一轮廓与多个接触垫的半导体装置，另外还提供一如上文描述的带件；孔洞的位置且因此所述孔洞中的回焊金属元件的位置与接触垫的位置匹配。。从第一带件表面侧去除箔片，因而暴露所述第一带件侧上的聚合粘着膜。接着，放置所述带件的回焊元件，使其接触所述装置的接触垫，而所述第一带件侧上的第一聚合粘着膜将所述装置固定在适当位置。热能被供应到所述装置与所述带件，足以回焊所述回焊元件且液化所述热塑性底板。在冷却到环境温度之后，带件被附着到所述装置，实质上不会留下任何空隙。
所述方法的工艺步骤可通过提供一外部部件而继续，所述外部部件在与带件孔洞中的回焊元件的位置匹配的位置中具有多个接触垫。从所述第二表面侧去除所述箔片，因而暴露所述第二带件侧上的聚合粘着膜。接着，放置带件的回焊元件，使其接触外部部件的终端垫，而所述第二带件侧上的聚合粘着膜将外部部件固定在适当位置。热能被供应到所述装置、所述带件以及所述外部部件，足以回焊所述回焊元件且液化所述热塑性底板。在冷却到环境温度之后，带件被附着到外部部件，而工件与外部部件分离，且所述空间被填充而实质上不会留下任何空隙。
当所述装置是半导体芯片时，所述外部部件是适于所述芯片的倒装装配的衬底。当所述装置是含有多个半导体芯片的半导体晶圆时，所述外部部件是适于所述晶圆的倒装装配的衬底。当所述装置是囊封经装配半导体芯片的半导体封装或封装堆叠时，所述外部部件是适于所述封装或堆叠的倒装附着的板。
本发明的实施例涉及倒装芯片装配、球格栅阵列封装、芯片级以及芯片尺寸封装、封装上封装，和预期用于回焊附着到衬底和其它外部部件的其它装置。一技术优点在于，本发明提供一种方法以减小装置的半导体部件与具有不同热膨胀系数的衬底之间的热机械应力，同时控制基本装配参数，例如半导体部件与衬底之间的间隔、部件之间的粘着性，和装配工艺中所需的温度范围的选择。额外的技术优点源自以下事实：以热塑性带件制成的装置是可再加工的。另外，由于在倒装装配之后的常规底填充工艺被消除，因而简化了工艺流程。
附图说明
图1A示意展示根据本发明一实施例用于半导体组合件中的带件的横截面，以便说明各个绝缘层与粘着层的结构。
图1B示意展示根据本发明另一实施例用于半导体组合件中的带件的横截面，以便说明各个绝缘层与粘着层的结构。
图2示意展示图1A的带件的横截面，其具有经形成以穿透带件厚度的具有渐细壁的孔洞。
图3是图2的带件的横截面，其具有位于带件孔洞中的回焊金属元件。
图4展示图3的带件在去除带件结构的最外层之后的示意横截面。
图5是说明被装配在工件上的带件的一部分的示意横截面。
图6是说明图5的带件部分在去除分隔层以暴露附着的回焊元件之后的示意横截面。
图7是说明装配于外部部件上具有回焊元件的单一化带件与衬底单元的示意横截面。
图8是使用本发明的组合件带件而倒装附着于外板上的半导体封装堆叠的示意横截面。
具体实施方式
在图1A的示意横截面中将本发明的一个实施例描绘为一带件(一般表示为100)，其用作载体且尤其在半导体装置组合件中。带件100由聚合材料(优选为热塑性材料)的底板101组成，其厚度范围从约25到450μm；对于一些装置，所述厚度可达到约800μm。优选的热塑性底板材料包含：长链聚酰亚胺加上丙烯酸树脂或聚硅氧树脂、长链聚乙烯加上丙烯酸树脂，以及长链聚丙烯加上丙烯酸树脂。优选地，选择底板材料使得其在对被嵌入带件(见下文)中的回焊元件进行回焊所需的相同温度范围中软化并进入低粘度或液相。举例来说，此温度范围包含经选定用于装配所述装置的焊料的熔化温度。一技术优点在于，当所述底板选自热塑性材料时，所述热塑性材料的液化和固化的工艺可毫无困难地重复许多次。优选地，将热膨胀系数选择为介于约8与120ppm之间，且弹性模数介于约100与10000MPa之间。
底板101具有第一表面101a和第二表面101b。第一聚合粘着膜102被附着到所述第一表面101a，之后不同材料的第一箔片103附着到所述第一表面101a。以类似方式，第二聚合粘着膜104被附着到所述第二表面101b，之后不同材料的第二箔片105附着到所述第二表面101b。优选地，所述粘着膜102和104包含聚合物材料，例如环氧树脂、聚酰亚胺或聚硅氧，其不仅具有粘着性，而且还可轻易地被剥除；所述粘着膜具有从约25到100μm的优选厚度范围。所述箔片103和105包含例如PVC与PET的惰性材料，且具有从约25到50μm的优选厚度范围。箔片103与105有时称为“分隔层”。例如带件100的层压带件可在市场上购得，且也可例如由日本Lintec公司依据客户规格予以制作。
底板101、聚合粘着膜102和104以及箔片103和105的组合为带件100提供一厚度110。厚度110被带件100中的多个孔洞穿透以便提供空间供回焊元件(例如焊球)使用(见图3)。
图1B说明图1A中的带件的变化。中央底板由两个膜121和122组成，其在其整个区域上彼此附着。两个膜均由聚合物制成，优选地由热塑性聚硅氧材料制成，且还包含长链聚酰亚胺加上丙烯酸树脂或聚硅氧树脂、长链聚乙烯加上丙烯酸树脂，以及长链聚丙烯加上丙烯酸树脂。与仅一个膜相比，两个膜的优点是改进了与被插入贯穿带件的孔洞中的焊球的粘着性(见图3)。膜121与122可具有相等厚度或不同厚度；个别基底膜厚度通常在从约20到100μm的范围内，但整体来说，所述对的底板厚度120可达到450μm或更大。
带件厚度110或120由待插入带件孔洞中的焊球的尺寸确定；球尺寸又由预期的球间距确定。举例来说，0.8mm的球间距使用350到400μm的球直径；0.5mm的球间距使用250到300μm的球直径。当产品需要不同的球尺寸时，带件厚度也需要改变。
当带件100的形状为片状时，可在带件100中形成多个孔洞。这些孔洞的位置可选择为任何预定图案。图2更详细地展示一个特定的孔洞。所述孔洞在带件侧上具有稍大的直径201，在相对带件侧上具有较小的直径202，从而造成渐细轮廓。所述直径经选择使得可在孔洞中可靠地安装焊球或圆柱体。渐细壁在小直径开口处形成角度203。优选的角度203介于约70°与80°之间。
可用于开口工艺的技术之一为激光、机械钻孔和机械打孔。经验指出，激光技术优于钻孔或打孔技术。优选的激光方法为准分子激光，因为准分子激光用于界定深度110和直径201与202时具有±5μm的精确度。孔洞可为圆形或可为任何其它预定轮廓；孔洞直径可对于所有孔洞来说均相同，或其可不同。
图3展示位于深度110的孔洞中的一个回焊金属元件301。优选地，回焊元件301的直径302略小于孔洞直径201，但大于孔洞直径202。以此方式，回焊元件301牢牢地固定在孔洞中的适当位置，且无法移动或掉落。
为了突显带件100的技术上的优越特性，图4到7描述使用半导体装置的装配与装置制造的各种工艺步骤，所述半导体装置具有一轮廓和多个接触垫。在半导体工业的实施例中，所述装置是含有多个半导体芯片的半导体晶圆，或个别半导体芯片，或囊封衬底上的经装配半导体芯片的半导体封装，或是半导体封装堆叠。所述带件具备所述多个孔洞和在与装置的接触垫的位置匹配的位置中的插入的回焊元件。
工艺流程始于图4，其中已去除包围渐细孔洞的窄开口202的分隔层105。现暴露聚合粘着膜104。回焊元件301保持固定于适当位置，因为其与聚合基底膜101接触。对许多应用来说，元件301和孔洞的尺寸已经选定使得所述元件301在工艺流程的此阶段从所述孔洞略微突出。
接着提供半导体装置。作为特定装置的一实例，供应半导体晶圆，其具有多个朝上的半导体芯片。每一芯片具有多个朝上的接触垫。带件定位在晶圆上方，使得位于带件孔洞中的多个回焊元件的位置与晶圆上半导体芯片的接触垫的位置匹配。降低带件，且所述带件的每一回焊元件接触晶圆的其相应接触垫。优选地，聚合粘着膜104也接触所述装置，从而帮助稳定带件和所述装置。
作为特定装置的另一实例，提供模制实体，其含有装配(例如，通过附着与线焊接)在衬底上并通过模制化合物囊封的多个半导体芯片。所述衬底具有用于每一经装配芯片的多个朝上的接触垫。所述带件定位在所述模制实体上方，使得位于带件孔洞中的述多个回焊元件的位置与模制实体的衬底的接触垫的位置匹配。优选地，聚合粘着膜104也接触模制实体，从而帮助稳定带件和所述实体。
图5的示意横截面说明制造工艺的下一步骤。带件510的每一回焊元件503接触装置501的各自接触垫502(之前已提及，装置501可能是半导体芯片、半导体封装或封装堆叠)。此步骤可通过聚合粘着膜104将装置501固定在适当位置来促进。接着，热能被供应到装置501和带件510，足以回焊所述回焊元件503且液化热塑性底板504(在回焊之前，在图1A、2、3和4中表示为101)，借此带件510附着到装置501。
图5中，以两个结果示意指示加热循环的效应：回焊元件503(例如，焊球)已横跨垫605的全长而形成接点506，同时回焊元件的剩余表面已因表面张力而被拉成近似球形。经软化的热塑性材料504已填充接点506和经回焊金属颈部508周围的可用空间507。通过选择适当的加热温度和时间，周围的热塑性材料填充空间507且实质上不会留下任何空隙。
当其中所述装置是个别芯片或个别封装的那些实施例已冷却到环境温度时，所述热塑性材料已形成一轮廓，其实质上与工件的轮廓一致。如本文所定义，“一致”不仅包含接续工件的轮廓的直线；其还包含次要的凹形或凸形轮廓。然而，“一致”排除众所周知的弯月形，其在常规技术中通常通过施配热固性底填充材料而形成。在常规的制造工艺中，低粘性热固性材料通过表面张力来驱动以突出到所述装置轮廓外部而形成众所周知的弯月形。
在接下来的工艺步骤中，去除渐细孔洞的宽开口201周围的分隔层103，从而暴露第一聚合粘着膜102。结果显示在图6中。
当装置501不是个别半导体芯片而是含有多个半导体芯片的整个半导体晶圆时，作为图6中所示的阶段之后的下一工艺步骤，优选地执行将与带件装配在一起的晶圆分离为离散的经装配装置。优选的分离方法是锯切。
类似地，当装置501不是个别半导体封装，而是含有多个经装配与囊封的半导体芯片的整个模制实体时，图6中所示的阶段之后的下一工艺步骤优选地是将与带件装配在一起的实体分离为离散的经装配封装。优选的分离方法是锯切。
对于下一工艺步骤，提供一外部部件，其在与回焊元件的位置匹配的位置中具有多个终端垫。作为一实例，所述外部部件可为衬底，其适合于倒装装配先前已附着到带件的半导体芯片。作为另一实例，外部部件可为电路板，其适合于倒装装配先前已附着到带件的半导体封装。
在图7中，所述外部部件表示为701，且所述多个终端垫的一者表示为702。具有其接触垫502的装置501连同带件的附着的剩余部720和回焊元件一起形成单元710。注意，单元710已相对于图6中的定向被倒装。进一步注意，单元710的侧轮廓被展示为实质上直的轮廓711；所述直的轮廓是上文描述的单一化步骤，或是使用具有热塑性底板的带件进行装配所造成的结果。
带件的被焊接到装置接触垫502的回焊元件503被放置成与外部部件的终端垫702接触。此外，第一聚合粘着膜102可将所述外部部件701固定在适当位置。接着，将热能供应到装置501、带件720和外部部件701，足以回焊所述回焊元件503且液化带件720的热塑性底板504。在图7中，两个结果示意地指示加热循环的效应：回焊元件503已横跨终端垫702的全长形成接点706；及已软化的热塑性材料504已经填充接点706和经回焊金属颈部708周围的现有空间707。通过选择适当的加热温度和时间，周围的热塑性材料填充空间707且实质上不会留下任何空隙。此外，在冷却到环境温度之后，热塑性材料504大约维持其轮廓711，所述轮廓711实质上与装置的轮廓711一致。
由于装配工艺的结果，带件720和工件501附着到外部部件701，而所述装置501与外部部件701隔开。热塑性“底填充”材料处于适当位置，以由于其与常规热固性底填充材料相比不明显的热收缩的缘故而减轻回焊互连和焊点处的热机械应力。所完成的产品一般在图7中表示为700。
对于上文描述的装配工艺步骤，优选地选择用于聚合粘着膜102与104的材料使得其在从环境温度到约300℃和甚至更高的温度范围中保持具有粘性，不需要特定的固化工艺，且具有高于约300℃的分解温度。
从材料选择和工艺流程的以上描述中可明白，金属回焊与焊接作用不需要任何助熔剂，且温度循环期间金属回焊焊球上的任何工艺相关应力均由于热塑性聚合物的持续存在而减到最小。此外，热塑性材料填充任何现有空间，而实质上不会有任何空隙。经验已进一步展示，热塑性材料的选择以及其在制造工艺期间的持续存在使半导体产品在使用条件以及温度循环、湿度敏感度和落下试验的测试下具有可靠性性能的特性，所述可靠性性能比使用现有技术制造技术所制造的产品高三到十倍。
示意图8是半导体产品(一般表示为800)的实施例的实例，其中所述装置是半导体封装堆叠。第一封装801具有延伸衬底802，其在其与所附着芯片相对的表面上带有终端垫。这些终端垫借助带件810被附着到具有延伸衬底821的第二封装820。衬底821具有两组多个接触垫：位于芯片附着表面上的多个接触垫用于连接到封装801；位于相对衬底表面上的其它多个接触垫用于附着到外部部件840。所述具有两个封装的堆叠到外部部件840的附着通过带件830完成。作为一实例，外部部件840可以是电路布线板。
在回焊工艺步骤中，同时执行焊接接点成形以及实质无空隙底填充。注意，带件810与830分别具有轮廓811与831，其实质上为直的且与封装衬底的轮廓一致。此近似直的轮廓是带件基底材料的热塑性性质所造成的结果(对于从模制实体中单一化得到的封装，其也可通过封装分离工艺来产生)。
一般已知封装堆叠由于所分散组分(硅、金属、聚合物等)具有差异较大的热膨胀系数的缘故而对热机械应力敏感。因此，本发明的一独特技术优点是提供一种基于热塑性底填充材料的堆叠结构和制造方法，所述热塑性底填充材料因具有比常规技术的热固性材料小得多的热收缩而显著减小热机械应力。利用这个优点，所属领域的技术人员容易基于本发明的概念和方法来构造复合装置(例如图8中所示)，其在可靠度试验(例如落下试验)中具有卓越的性能。
虽然已参考说明性实施例描述了本发明，但此描述并不希望在限定的意义上加以解释。所属领域的技术人员在参考所述描述之后将明白说明性实施例以及本发明的其它实施例的各种修改与组合。作为一实例，对于具有显著较高或较低回焊温度的互连元件的组合件，适宜的底板热塑性物质以及粘着剂可通过对其材料的聚合物链进行修改而构成。作为另一实例，较低热膨胀系数的底填充材料可通过在聚合物基底材料中加入惰性(无机)填充物而构成。因此，希望所主张的本发明涵盖任何此类修改和实施例。

Claims (14)

1.一种用作载体的带件，其包括：
聚合物材料的底板，其具有第一和第二表面；
聚合粘着膜和不同材料的箔片，其被附着到所述底板的所述第一和所述第二表面侧上，从而为所述带件提供一厚度；
多个孔洞，其贯穿所述带件厚度；以及
回焊金属元件，其设置在所述孔洞的每一者中。
2.根据权利要求1所述的带件，其中所述底板的所述聚合物材料包含选自以下各项的热塑性材料：长链聚酰亚胺加上丙烯酸树脂或聚硅氧树脂、聚乙烯加上丙烯酸树脂，以及聚丙烯加上丙烯酸树脂。
3.根据权利要求1所述的带件，其中所述底板由彼此附着的两个聚合物膜组成。
4.根据权利要求1-3中任一权利要求所述的带件，其中所述孔洞为渐细状，以与所述表面形成介于约70°与80°之间的角度。
5.根据权利要求1-3中任一权利要求所述的带件，其中所述回焊金属元件是合金焊球或合金焊接圆柱体。
6.根据权利要求1-3中任一权利要求所述的带件：
其中所述底板具有约25与450μm之间的厚度；
其中所述聚合粘着膜具有约25与100μm之间的厚度且包括一个或一个以上聚合物，所述聚合物包含环氧树脂和聚酰亚胺以及聚硅氧；
其中所述不同材料的箔片具有约10与50μm之间的厚度且由包含PVC和PET的惰性材料制成；且
其中所述回焊金属元件具有约等于所述带件厚度的直径。
7.一种半导体封装，其包括：
半导体装置，其具有一轮廓和多个接触垫；
外部部件，其具有多个终端垫，所述部件与所述装置隔开，且所述终端垫分别与所述装置接触垫对准；
回焊元件，其将所述接触垫的每一者与其各自终端垫互连；以及
聚合材料，其填充所述装置与所述部件之间的空间，所述材料粘着到所述装置、所述部件和所述回焊元件，所述材料具有实质上与所述装置的所述轮廓一致的轮廓，且填充所述空间而实质上不具有任何空隙。
8.根据权利要求7所述的封装，其中所述装置具有至少一个半导体芯片，且所述外部部件是适于所述至少一个芯片的倒装装配的衬底。
9.根据权利要求7所述的装置，其中所述聚合材料是热塑性填充材料，其可操作以在用于回焊所述回焊元件的大致相同温度范围内转换成粘性流体。
10.一种用于装配半导体封装的方法，其包括以下步骤：
提供半导体装置，其具有一轮廓和多个接触垫；
提供带件，所述带件具有：热塑性材料的底板以及第一和第二表面；聚合粘着膜和不同材料的箔片，其附着到所述底板的所述第一和所述第二表面侧上，且为所述带件提供一厚度；多个孔洞，其贯穿所述带件厚度；位于所述孔洞中的每一者中的回焊金属元件，其与所述半导体装置接触垫的位置匹配；
从所述第一带件表面侧去除所述箔片，从而暴露所述第一带件侧上的所述聚合粘着膜；
放置所述带件的所述回焊元件使其接触装置接触垫；
将热能供应到所述装置和所述带件，足以回焊所述回焊元件且液化所述热塑性底板；以及
将所述装置和所述带件冷却到环境温度，因此将所述带件附着到所述装置。
11.根据权利要求10所述的方法，其进一步包括以下步骤：
提供外部部件，所述外部部件在与所述带件孔洞中的所述回焊元件的位置匹配的位置中具有多个终端垫；
从所述第二表面侧去除所述箔片，从而暴露所述第二带件侧上的所述聚合粘着膜；
放置所述带件的所述回焊元件使其接触所述外部部件的所述终端垫，使得所述第二带件侧上的所述聚合粘着膜将所述外部部件固定在适当位置；
将热能供应到所述装置、所述带件和所述外部部件，足以回焊所述回焊元件且液化所述热塑性底板；以及
将所述半导体装置、所述带件和所述外部部件冷却到环境温度，因而将所述带件附着到所述外部部件，同时将所述装置与所述外部部件隔开。
12.根据权利要求11所述的方法，其中所述经液化的热塑性底板实质上无空隙地填充工件与所述外部部件之间的空间。
13.根据权利要求10或11所述的方法，其中所述半导体装置是含有多个半导体芯片的半导体晶圆，且所述外部部件是适于所述晶圆的倒装装配的衬底。
14.根据权利要求13所述的方法，其进一步包括将所述经装配晶圆分离成离散的经装配芯片从而单一化半导体装置的步骤。
CNA2007800029648A 2006-01-24 2007-01-22 倒装附着且底填充堆叠的半导体装置 Pending CN101371354A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/337,985 2006-01-24
US11/337,985 US20070170599A1 (en) 2006-01-24 2006-01-24 Flip-attached and underfilled stacked semiconductor devices

Publications (1)

Publication Number Publication Date
CN101371354A true CN101371354A (zh) 2009-02-18

Family

ID=38284749

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2007800029648A Pending CN101371354A (zh) 2006-01-24 2007-01-22 倒装附着且底填充堆叠的半导体装置

Country Status (7)

Country Link
US (1) US20070170599A1 (zh)
EP (1) EP1982353A4 (zh)
JP (1) JP2009524937A (zh)
KR (1) KR20080092969A (zh)
CN (1) CN101371354A (zh)
TW (1) TW200742014A (zh)
WO (1) WO2007087502A2 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035600A (zh) * 2011-10-06 2013-04-10 台湾积体电路制造股份有限公司 具有保护结构的凸块
CN106098568A (zh) * 2015-05-01 2016-11-09 颀邦科技股份有限公司 具有中空腔室的半导体封装制造过程
CN111434191A (zh) * 2017-11-10 2020-07-17 Lpkf激光电子股份公司 集成半导体晶片的方法和装置

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060064773A1 (en) * 2004-06-28 2006-03-23 Pioneer Hi-Bred International, Inc. Cell cycle polynucleotides and polypeptides and methods of use
JP2006120935A (ja) * 2004-10-22 2006-05-11 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP5074738B2 (ja) * 2006-10-24 2012-11-14 リンテック株式会社 複合型半導体装置用スペーサーシート、及び複合型半導体装置の製造方法
JP5044189B2 (ja) * 2006-10-24 2012-10-10 リンテック株式会社 複合型半導体装置の製造方法、及び複合型半導体装置
TWI478257B (zh) * 2009-08-06 2015-03-21 Htc Corp 封裝結構及封裝製程
JP5965185B2 (ja) * 2012-03-30 2016-08-03 デクセリアルズ株式会社 回路接続材料、及びこれを用いた半導体装置の製造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0560072A3 (en) * 1992-03-13 1993-10-06 Nitto Denko Corporation Anisotropic electrically conductive adhesive film and connection structure using the same
JPH09213744A (ja) * 1996-02-07 1997-08-15 Toshiba Microelectron Corp 半導体装置及びその製造方法
US6028365A (en) * 1998-03-30 2000-02-22 Micron Technology, Inc. Integrated circuit package and method of fabrication
JP2004134817A (ja) * 1998-06-04 2004-04-30 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
WO2001035457A1 (en) * 1999-11-08 2001-05-17 Amerasia International Technology, Inc. Wafer level application of tack-free die-attach adhesive film
US6518096B2 (en) * 2001-01-08 2003-02-11 Fujitsu Limited Interconnect assembly and Z-connection method for fine pitch substrates
US20030155656A1 (en) * 2002-01-18 2003-08-21 Chiu Cindy Chia-Wen Anisotropically conductive film
JP4130747B2 (ja) * 2002-03-28 2008-08-06 旭化成エレクトロニクス株式会社 異方導電性接着シートおよびその製造方法
JP5197961B2 (ja) * 2003-12-17 2013-05-15 スタッツ・チップパック・インコーポレイテッド マルチチップパッケージモジュールおよびその製造方法
US7701071B2 (en) * 2005-03-24 2010-04-20 Texas Instruments Incorporated Method for fabricating flip-attached and underfilled semiconductor devices
US7528474B2 (en) * 2005-05-31 2009-05-05 Stats Chippac Ltd. Stacked semiconductor package assembly having hollowed substrate

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035600A (zh) * 2011-10-06 2013-04-10 台湾积体电路制造股份有限公司 具有保护结构的凸块
CN103035600B (zh) * 2011-10-06 2016-05-04 台湾积体电路制造股份有限公司 具有保护结构的凸块
CN106098568A (zh) * 2015-05-01 2016-11-09 颀邦科技股份有限公司 具有中空腔室的半导体封装制造过程
CN111434191A (zh) * 2017-11-10 2020-07-17 Lpkf激光电子股份公司 集成半导体晶片的方法和装置
CN111434191B (zh) * 2017-11-10 2023-10-20 Lpkf激光电子股份公司 集成半导体晶片的方法和装置

Also Published As

Publication number Publication date
JP2009524937A (ja) 2009-07-02
US20070170599A1 (en) 2007-07-26
WO2007087502A3 (en) 2008-04-24
KR20080092969A (ko) 2008-10-16
EP1982353A4 (en) 2009-04-29
WO2007087502A2 (en) 2007-08-02
TW200742014A (en) 2007-11-01
EP1982353A2 (en) 2008-10-22

Similar Documents

Publication Publication Date Title
US6701614B2 (en) Method for making a build-up package of a semiconductor
CN101371354A (zh) 倒装附着且底填充堆叠的半导体装置
US6309915B1 (en) Semiconductor chip package with expander ring and method of making same
US6020629A (en) Stacked semiconductor package and method of fabrication
US6737300B2 (en) Chip scale package and manufacturing method
US7148081B2 (en) Method of manufacturing a semiconductor device
JP4830120B2 (ja) 電子パッケージ及びその製造方法
KR100652242B1 (ko) 플립칩형 반도체장치, 이의 제조를 위한 제조방법 및 이런 플립칩형 반도체장치를 사용하여 전자제품을 제조하기 위한 제조방법
US7880291B2 (en) Integrated circuit package and integrated circuit module
US20040229401A1 (en) Method for fabricating semiconductor component having stacked, encapsulated dice
JP2003115560A (ja) 半導体装置、積層半導体装置、半導体装置の製造方法及び積層半導体装置の製造方法
US20090065927A1 (en) Semiconductor Device and Methods of Manufacturing Semiconductor Devices
KR20170016550A (ko) 반도체 패키지의 제조 방법
US8193085B2 (en) Method for fabricating flip-attached and underfilled semiconductor devices
KR100405771B1 (ko) 반도체장치 및 그 제조방법
CN110634880A (zh) 半导体装置及其制造方法
US8598029B2 (en) Method for fabricating flip-attached and underfilled semiconductor devices
JP2006222470A (ja) 半導体装置および半導体装置の製造方法
JP2007294560A (ja) 半導体装置およびその製造方法
US20220384468A1 (en) Semiconductor device and semiconductor device manufacturing method
KR20240111079A (ko) 티에스브이구조를 가지는 다수개의 칩 적층구조를 포함하는 티에스브이 반도체 패키지 제조방법 및 이에 의해 제조된 티에스브이 반도체 패키지

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Open date: 20090218