CN101335224A - 半导体封装结构及其制造方法 - Google Patents

半导体封装结构及其制造方法 Download PDF

Info

Publication number
CN101335224A
CN101335224A CNA2008100046156A CN200810004615A CN101335224A CN 101335224 A CN101335224 A CN 101335224A CN A2008100046156 A CNA2008100046156 A CN A2008100046156A CN 200810004615 A CN200810004615 A CN 200810004615A CN 101335224 A CN101335224 A CN 101335224A
Authority
CN
China
Prior art keywords
substrate
semiconductor package
manufacture method
interlayer
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2008100046156A
Other languages
English (en)
Other versions
CN101335224B (zh
Inventor
陈承先
张国钦
卢思维
曹佩华
王忠裕
曾汉良
李明机
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN101335224A publication Critical patent/CN101335224A/zh
Application granted granted Critical
Publication of CN101335224B publication Critical patent/CN101335224B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02319—Manufacturing methods of the redistribution layers by using a preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02321—Reworking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/08235—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bonding area connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

本发明公开一种半导体封装结构及其制造方法。在一个实施例中，首先提供半导体芯片，其上露出多个导电层。提供第一基板，其具有第一表面与第二表面，第一表面露出多个介层插塞。将半导体芯片与第一基板接合，使导电层对准并接触介层插塞。从第二表面去除部分的第一基板，以露出介层插塞的另一端。于介层插塞露出的另一端形成凸块底层金属，并于凸块底层金属上形成焊料凸块。提供第二基板，其具有第一表面与第二表面，将焊料凸块设置在第二基板的第一表面。本发明可使焊料凸块较为坚固，大大减少焊料凸块破裂的机会。

Description

半导体封装结构及其制造方法
技术领域
本发明涉及半导体芯片封装，且特别涉及一种低翘曲、高结构强度的球栅阵列(BGA，ball grid array)封装。
背景技术
球栅阵列(BGA，ball grid array)封装是一种先进的半导体封装技术，其特点是将半导体芯片设置在具有焊球阵列的BGA基板上。在进行表面粘着时，BGA基板可以通过这些焊球电性连接到印刷电路板(PCB，printed circuitboard)上。
覆晶(flip chip)球栅阵列是比BGA更为先进的封装技术，覆晶的名称源自于将芯片倒置后再连接至基板。请参照图1，其显示传统覆晶封装半成品的剖面图。覆晶封装2包含芯片4，其具有上表面6及下表面8。芯片4下具有一组焊料凸块(solder bump)10连接至芯片下表面8的接触垫(未显示)。芯片4固定在基板12上，且焊料凸块10连接至基板12上表面的接触垫(未显示)。在芯片4与基板12之间可填充底部填充胶(underfill)14以增加覆晶封装2的坚硬度，避免芯片4受弯曲破坏。基板12底下可设置一组焊球以连接基板12下表面的连接垫(未显示)与印刷电路板18上的接触垫(未显示)。
覆晶封装2可还包含散热器(heat spreader)20与补强材(stiffener)22以帮助散热与避免翘曲。散热器20设置在芯片4表面上，除了帮助芯片4散热外还可抵消芯片4与基板12因为热膨胀不同所产生的作用力。传统的覆晶封装2在芯片4与散热器20之间可还包括热界面材料(thermal interfacematerial)26，将芯片4的热能传导至散热器20。
由于芯片4与基板12通常是由不同材料构成，热膨胀系数(CTE，coefficient of thermal expansion)并不一致。因此两者在经历热循环与机械应力循环(thermal and mechanical stress cycles)时会有不同的尺寸变化，造成芯片4与基板12之间产生相当大的热应力。所造成的热应力与翘曲不只会使芯片4中的低介电常数层脱层(delamination)，并会造成焊料凸块破裂，严重影响覆晶封装的长期操作可靠度。虽然补强材与散热器可以减缓翘曲的程度，却无法完全解决上述问题。
在内连线结构中使用超低介电常数材料(extreme low dielectric constantmaterial，ELK material)为下个世代的趋势，由于超低介电常数材料比一般的低介电常数材料更加脆弱且更不致密，因此芯片与基板的CTE不一致所造成的影响会更加严重。
由以上说明可知，业界急需针对BGA封装进行改良以解决上述问题。
发明内容
本发明的目的在于提供一种低翘曲、高结构强度的球栅阵列(BGA，ballgrid array)封装，以克服上述的焊料凸块破裂，严重影响覆晶封装的长期操作可靠度等缺陷。
本发明提供一种半导体封装结构的制造方法，包括下列步骤：提供半导体芯片，其上露出多个导电层；提供第一基板，其具有第一表面与第二表面，第一表面露出多个介层插塞；将半导体芯片与第一基板接合，其中导电层对准并接触介层插塞；从第二表面去除部分第一基板，以露出介层插塞的另一端；于介层插塞露出的另一端形成多个凸块底层金属；于凸块底层金属上形成多个焊料凸块；以及，提供第二基板，其具有第一表面与第二表面，并将焊料凸块设置在第二基板的第一表面。
如上所述的半导体封装结构的制造方法，其中所述多个导电层包括接合垫或金属层。
如上所述的半导体封装结构的制造方法，其中所述第一基板包括硅、二氧化硅、玻璃、或前述的组合，且所述第一基板的厚度约200-775μm。
如上所述的半导体封装结构的制造方法，其中所述半导体芯片与所述第一基板的接合是以下列方式之一进行：直接接合、阳极接合、共晶接合、粘着接合、或玻璃介质接合。
如上所述的半导体封装结构的制造方法，其中去除部分的所述第一基板是以下列方式之一进行：抛光研磨、化学机械研磨、电化学机械研磨、湿蚀刻、或干蚀刻。
如上所述的半导体封装结构的制造方法，其中去除部分的所述第一基板后，所述第一基板剩余的厚度约50-300μm。
如上所述的半导体封装结构的制造方法，还包括在第一基板与所述第二基板之间填入底部填充胶。
如上所述的半导体封装结构的制造方法，还包括于所述第二基板的第二表面形成多个焊球。
如上所述的半导体封装结构的制造方法，还包括将所述多个焊球设置在第三基板上。
本发明还提供一种半导体封装结构，包括：半导体芯片，其上露出多个导电层；第一基板，其具有多个介层孔洞，介层孔洞中具有介层插塞，第一基板的第一侧露出介层插塞的一端，第一基板的第二侧露出介层插塞的另一端，其中半导体芯片与第一基板接合，且导电层对准并接触第一侧的介层插塞；多个凸块底层金属设置在介层插塞的另一端；多个焊料凸块设置在凸块底层金属上；以及第二基板，其具有第一表面与第二表面，其中焊料凸块设置在第二基板的第一表面。
如上所述的半导体封装结构，还包括多个焊球设置于所述第二基板的第二表面。
如上所述的半导体封装结构，还包括第三基板，其上设置所述多个焊球。
如上所述的半导体封装结构，其中所述导电层包括接合垫或金属层。
如上所述的半导体封装结构，其中所述第一基板包括硅、二氧化硅、玻璃、或前述的组合，且所述第一基板的厚度约50-300μm。
如上所述的半导体封装结构，其中在第一基板与所述第二基板之间还包括底部填充胶。
综上所述，本发明可提供以下优点：(1)由于超低介电常数材料比一般低介电常数材料更加脆弱且更不致密，其芯片容易发生脱层，本发明的含硅基板在热循环与机械应力循环时可以舒缓芯片与第二基板之间的应力，而得到更坚固的覆晶封装结构；(2)由于焊料凸块并非形成在含有超低介电常数材料的芯片上，而是形成在舒缓应力的含硅基板上，因此焊料凸块较为坚固，大大减少焊料凸块破裂的机会。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出较佳实施例，并结合附图，作详细说明如下。
附图说明
图1显示传统覆晶封装半成品的剖面图。
图2为一剖面图，其显示本发明一个实施例的覆晶封装半成品，其中第一基板的第一表面具有多个介层插塞。
图3为一剖面图，其显示将图2的第一基板与半导体芯片接合。
图4为一剖面图，其显示对图3的第一基板进行薄化，以露出介层插塞的另一端。
图5为一剖面图，其显示在图4的介层插塞上形成凸块底层金属与焊料凸块。
图6为一剖面图，其显示将图5的焊料凸块设置在第二基板的第一表面上，然后在第二基板的第二表面上设置焊球，并将焊球设置在第三基板上。
并且，上述附图中的各附图标记说明如下：
2   覆晶封装
4   芯片
6   芯片的上表面
8   芯片的下表面
10  焊料凸块
12  基板
14  底部填充胶
20  散热器
22  补强材
26  热界面材料
3   覆晶封装
16  焊球
28  第一基板
29  第一基板的第一表面
31  第一基板的第二表面
30  介层孔
32  介层插塞
34  导电层
36  半导体芯片
38  凸块底层金属
40  焊料凸块
42  第二基板
43  第二基板的第一表面
45  第二基板的第二表面
46  第三基板
具体实施方式
图2显示本发明一个实施例的覆晶封装半成品3，其中第一基板28具有第一表面29与第二表面31，第一表面29具有多个介层孔30，介层孔30中填充有导电材料以形成介层插塞32。第一基板28为应力舒缓基板(stressrelieving substrate)，其材质可包括硅、二氧化硅、玻璃、或前述的组合，其作用为缓和覆晶封装3在热循环与机械循环(mechanical cycling)所受的应力，并增加覆晶封装中焊料凸块的支撑力。应力舒缓基板特别适合用在具有超低介电常数材料的半导体芯片，因为超低介电常数材料比一般的低介电常数材料更加脆弱且更不致密，所以遭遇热循环与机械应力循环时特别容易有脱层的现象。在一个实施例中，第一基板28包含硅，厚度约200-775μm。
第一基板28的第一表面29具有多个介层孔30。介层孔30可以传统的光刻与蚀刻技术形成，在一个实施例中，介层孔30的宽度约40-125μm，深度约50-300μm。接着，以传统的电镀方式将导电材料沉积在介层孔30中。电镀工艺持续到预定时间结束，或者持续到终点检测装置显示出导电材料已沉积到预定的厚度。沉积完毕后导电材料将介层孔30完全填满且形成大抵平坦的上表面。
之后，将介层孔30以外多余的导电材料去除，留下如图2所示的介层插塞32。多余的导电材料可用化学机械研磨(CMP)、电化学机械研磨(electrochemical mechanical planarization，ECMP)、湿蚀刻或其他适合的方式去除。
请参照图3，将图2的第一基板28与半导体芯片36接合，并使介层插塞32对准并接触半导体芯片36表面的上导电层34。半导体芯片36为具有各种半导体元件与材料的基板，例如导电层、半导体层、介电层、有源元件、无源元件等(未显示)。其中介电层可为氧化硅、氮化硅、氮氧化硅、低介电常数层、高介电常数层、或前述的组合。在一个实施例中，介电层包含超低介电常数层(ELK)。此处所指的低介电常数层是指介电常数在2.5-3.0之间的材料，而超低介电常数层是指介电常数在2.5以下，甚至2.0以下的材料。超低介电常数层的材质可为无机材料、有机材料、混合材料(hybrid material)、或具有孔洞的前述材料。本领域技术人员应可了解，基板的种类可依据所采用的工艺作适当选择。
半导体芯片36表面具有多个上导电层34，其可为金属层或结合焊盘(bond pads)。上导电层34用来作为芯片36与后续焊料凸块的电性接触。半导体芯片36与第一基板28接合时，将芯片36的上导电层34对准并接触第一基板28的介层插塞32。上述的接合方式可采用传统的晶片对准接合技术例如直接接合、阳极接合、共晶接合、粘着接合、玻璃介质接合(Glass FritBonding)等。
请参照图4，从第二表面31去除部分的第一基板28以露出介层插塞32的另一端。例如可利用抛光研磨(grinding)、干蚀刻、湿蚀刻、CMP、ECMP、或前述的组合对第一基板28的第二表面31进行研磨或薄化，直到露出介层孔30的介层插塞32。第一基板28可以薄化至任意适当厚度。在一个实施例中，第一基板28薄化后的厚度约50-300μm，例如约150μm。
请参照图5，在介层插塞32的另一端形成凸块底层金属(under-bumpmetallization，UBM)38，并在凸块底层金属38上形成焊料凸块40。凸块底层金属38可由数层不同的金属材料所构成，例如粘着层、阻障层、润湿层(wettable layer)等，其沉积方式可采用电镀、无电电镀、溅镀等各种方式。形成凸块底层金属38后，接着以传统方式将焊料凸块40形成在凸块底层金属38之上。
请参照图6，将覆晶封装3的焊料凸块40设置在第二基板42的第一表面43上，然后在第二基板42的第二表面45上设置焊球16，并将焊球16设置在第三基板46上。焊料凸块40设置在第二基板42的第一表面43上的接触垫(未显示)。在第一基板28与第二基板42之间可填入底部填充胶44以增加覆晶封装3的坚硬度，避免覆晶封装3受弯曲破坏。焊球16可设置在第二基板42的第二表面45上的接触垫(未显示)。焊球16也可设置在第三基板46上的接触垫(未显示)。第三基板46可为印刷电路板或是其他公知的多层模块(multilayer module)。
根据本发明的实施例，在含有超低介电常数材料的半导体芯片与第二基板之间插入舒缓应力的含硅基板至少可提供以下优点：(1)由于超低介电常数材料比一般低介电常数材料更加脆弱且更不致密，其芯片容易发生脱层，本发明的含硅基板在热循环与机械应力循环时可以舒缓芯片与第二基板之间的应力，而得到更坚固的覆晶封装结构；(2)由于焊料凸块并非形成在含有超低介电常数材料的芯片上，而是形成在舒缓应力的含硅基板上，因此焊料凸块较为坚固，大大减少焊料凸块破裂的机会。
虽然本发明已以数个较佳实施例公开如上，但是其并非用以限定本发明，任何本领域技术人员在不脱离本发明的精神和范围内当可作任意的改动与润饰，因此本发明的保护范围当视随附的权利要求所界定的范围为准。

Claims (15)

1.一种半导体封装结构的制造方法，包括下列步骤：
提供半导体芯片，其上露出多个导电层；
提供第一基板，其具有第一表面与第二表面，所述第一表面露出多个介层插塞；
将所述半导体芯片与所述第一基板接合，其中所述多个导电层对准并接触所述多个介层插塞；
从所述第二表面去除部分所述第一基板，以露出所述多个介层插塞的另一端；
于所述多个介层插塞露出的另一端形成多个凸块底层金属；
于所述多个凸块底层金属上形成多个焊料凸块；以及
提供第二基板，其具有第一表面与第二表面，并将所述多个焊料凸块设置在所述第二基板的第一表面。
2.如权利要求1所述的半导体封装结构的制造方法，其中所述多个导电层包括接合垫或金属层。
3.如权利要求1所述的半导体封装结构的制造方法，其中所述第一基板包括硅、二氧化硅、玻璃、或前述的组合，且所述第一基板的厚度约200-775μm。
4.如权利要求1所述的半导体封装结构的制造方法，其中所述半导体芯片与所述第一基板的接合是以下列方式之一进行：直接接合、阳极接合、共晶接合、粘着接合、或玻璃介质接合。
5.如权利要求1所述的半导体封装结构的制造方法，其中去除部分的所述第一基板是以下列方式之一进行：抛光研磨、化学机械研磨、电化学机械研磨、湿蚀刻、或干蚀刻。
6.如权利要求1所述的半导体封装结构的制造方法，其中去除部分的所述第一基板后，所述第一基板剩余的厚度约50-300μm。
7.如权利要求1所述的半导体封装结构的制造方法，还包括在第一基板与所述第二基板之间填入底部填充胶。
8.如权利要求1所述的半导体封装结构的制造方法，还包括于所述第二基板的第二表面形成多个焊球。
9.如权利要求8所述的半导体封装结构的制造方法，还包括将所述多个焊球设置在第三基板上。
10.一种半导体封装结构，包括：
半导体芯片，其上露出多个导电层；
第一基板，其具有多个介层孔洞，所述多个介层孔洞中具有多个介层插塞，所述第一基板的第一侧露出所述多个介层插塞的一端，所述第一基板的第二侧露出所述多个介层插塞的另一端，其中所述半导体芯片与所述第一基板接合，且所述多个导电层对准并接触第一侧的所述多个介层插塞；
多个凸块底层金属，设置在所述多个介层插塞的另一端；
多个焊料凸块，设置在所述多个凸块底层金属上；以及
第二基板，其具有第一表面与第二表面，其中所述多个焊料凸块设置在所述第二基板的第一表面。
11.如权利要求10所述的半导体封装结构，还包括多个焊球设置于所述第二基板的第二表面。
12.如权利要求11所述的半导体封装结构，还包括第三基板，其上设置所述多个焊球。
13.如权利要求10所述的半导体封装结构，其中所述导电层包括接合垫或金属层。
14.如权利要求10所述的半导体封装结构，其中所述第一基板包括硅、二氧化硅、玻璃、或前述的组合，且所述第一基板的厚度约50-300μm。
15.如权利要求10所述的半导体封装结构，其中在第一基板与所述第二基板之间还包括底部填充胶。
CN2008100046156A 2007-01-22 2008-01-21 半导体封装结构及其制造方法 Expired - Fee Related CN101335224B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/655,844 US7662665B2 (en) 2007-01-22 2007-01-22 Method for fabricating a semiconductor package including stress relieving layer for flip chip packaging
US11/655,844 2007-01-22

Publications (2)

Publication Number Publication Date
CN101335224A true CN101335224A (zh) 2008-12-31
CN101335224B CN101335224B (zh) 2010-06-02

Family

ID=39640446

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008100046156A Expired - Fee Related CN101335224B (zh) 2007-01-22 2008-01-21 半导体封装结构及其制造方法

Country Status (2)

Country Link
US (1) US7662665B2 (zh)
CN (1) CN101335224B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106573833A (zh) * 2014-09-25 2017-04-19 日本电气硝子株式会社 支承玻璃基板及使用其的层叠体
CN109119382A (zh) * 2017-06-26 2019-01-01 台湾积体电路制造股份有限公司 封装结构

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7977160B2 (en) * 2009-08-10 2011-07-12 GlobalFoundries, Inc. Semiconductor devices having stress relief layers and methods for fabricating the same
US20110115067A1 (en) * 2009-11-18 2011-05-19 Jen-Chung Chen Semiconductor chip package with mold locks
US8653671B2 (en) 2010-11-05 2014-02-18 Stmicroelectronics, Inc. System for relieving stress and improving heat management in a 3D chip stack
US8564137B2 (en) * 2010-11-05 2013-10-22 Stmicroelectronics, Inc. System for relieving stress and improving heat management in a 3D chip stack having an array of inter-stack connections
FR3096173B1 (fr) * 2019-05-15 2021-05-28 Commissariat Energie Atomique Procédé d'auto-assemblage avec collage moléculaire hybride

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6081429A (en) * 1999-01-20 2000-06-27 Micron Technology, Inc. Test interposer for use with ball grid array packages assemblies and ball grid array packages including same and methods
US6281046B1 (en) * 2000-04-25 2001-08-28 Atmel Corporation Method of forming an integrated circuit package at a wafer level
DE10164494B9 (de) * 2001-12-28 2014-08-21 Epcos Ag Verkapseltes Bauelement mit geringer Bauhöhe sowie Verfahren zur Herstellung
TWI256719B (en) 2002-03-06 2006-06-11 Via Tech Inc Semiconductor device package module and manufacturing method thereof
JP2004186422A (ja) * 2002-12-03 2004-07-02 Shinko Electric Ind Co Ltd 電子部品実装構造及びその製造方法
US7235889B2 (en) * 2004-09-10 2007-06-26 Lsi Corporation Integrated heatspreader for use in wire bonded ball grid array semiconductor packages

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106573833A (zh) * 2014-09-25 2017-04-19 日本电气硝子株式会社 支承玻璃基板及使用其的层叠体
US11749574B2 (en) 2014-09-25 2023-09-05 Nippon Electric Glass Co., Ltd. Method of manufacturing semiconductor package
CN109119382A (zh) * 2017-06-26 2019-01-01 台湾积体电路制造股份有限公司 封装结构

Also Published As

Publication number Publication date
US20080174002A1 (en) 2008-07-24
CN101335224B (zh) 2010-06-02
US7662665B2 (en) 2010-02-16

Similar Documents

Publication Publication Date Title
US6639324B1 (en) Flip chip package module and method of forming the same
US10867897B2 (en) PoP device
KR102108236B1 (ko) 반도체 패키지들 내의 금속화 패턴들 및 그 형성 방법들
KR102450822B1 (ko) 반도체 장치의 제조 방법
US7964446B2 (en) Semiconductor device and method of manufacturing the same
US11967570B2 (en) Semiconductor package having improved thermal interface between semiconductor die and heat spreading structure
TWI415244B (zh) 半導體裝置及其製造方法
TWI553718B (zh) 半導體裝置及藉由形成保護材料於堆疊在半導體晶圓上之半導體晶粒之間以製造半導體裝置之方法以減少於切割時之缺陷
JP4361820B2 (ja) ウエハーレベルパッケージ、マルチ積層パッケージ及びその製造方法
CN101335224B (zh) 半导体封装结构及其制造方法
US20140295620A1 (en) Method of manufacturing semiconductor device having plural semiconductor chips stacked one another
KR101107858B1 (ko) 반도체 기판을 위한 도전 필러 구조 및 그 제조 방법
US20060035416A1 (en) Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
US7081405B2 (en) Package module for an IC device and method of forming the same
CN109273417A (zh) 封装结构、集成扇出型封装及其制作方法
US20230335540A1 (en) Semiconductor package and method of fabricating the same
KR102505853B1 (ko) 반도체 패키지
TW201351579A (zh) 高密度立體封裝
TWI397161B (zh) 具改良熱及機械特性之焊墊之積體電路
CN104851816A (zh) 一种多芯片高密度封装方法
Hara et al. Optimization for chip stack in 3-D packaging
JP2007142026A (ja) インターポーザとその製造方法及び半導体装置
CN100390983C (zh) 芯片封装体
CN113990815A (zh) 一种硅基微模组塑封结构及其制备方法
KR101440340B1 (ko) 반도체 패키지 제조용 서포팅 장치 및 이를 이용한 반도체 패키지 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20100602

CF01 Termination of patent right due to non-payment of annual fee