CN101305462A - 物理上高度安全的多芯片组件 - Google Patents

物理上高度安全的多芯片组件 Download PDF

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CN101305462A
CN101305462A CNA2006800421324A CN200680042132A CN101305462A CN 101305462 A CN101305462 A CN 101305462A CN A2006800421324 A CNA2006800421324 A CN A2006800421324A CN 200680042132 A CN200680042132 A CN 200680042132A CN 101305462 A CN101305462 A CN 101305462A
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substrate
plane surface
nude film
conductive path
electric conductor
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V·康多雷利
C·菲格
K·高特泽
N·哈德兹克
J·尼克博克
E·斯波罗吉斯
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International Business Machines Corp
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Abstract

提供一种物理上安全的处理组件，其包括安装在衬底上的裸片以将裸片的电接触夹在裸片和衬底之间。衬底具有衬底接触以及与裸片接触电耦接并延伸穿过衬底的导电路径。电导体围绕导电路径。监视电路检测电导体中的一个或更多个电导体的连续性的中断，并且优选地使得组件不能工作。优选地，设置环氧树脂封装以防止探测工具能够到达裸片或衬底接触。

Description

物理上高度安全的多芯片组件
技术领域
本发明一般涉及集成电路，更特别地，涉及针对逆向设计(reverseengineering)在物理上高度安全的计算模块。
背景技术
在计算机架构设计的所有层级上，防止逆向设计和数据盗窃都是重要的考虑。为了保护他们的IP投资，设计人员当前利用两种主要的方法以实现物理上高度安全的计算模块。这样的“高度安全的”计算模块适合于用于密码模块的NIST的FIPS 140-2第4级证明。实现在物理上高度安全的计算模块的第一种方法是将功能整个实施到单个的半导体芯片中，该半导体芯片的尺寸如此小，使得在物理上探测或在光学上确定秘密信息是不可行的。实现安全性的第二种方法是将一组半导体器件(诸如CPU、ASIC、FPGA、DRAM和SRAM)封入干预检测外壳(tamper detecting envelope)内，所述干预检测外壳完全封住这些器件，并且一旦被入侵就导致系统中的所有敏感信息被破坏。
构建单个芯片方案的常见问题是，单个芯片常常太小，以至于不能以经济的方式适合整个复杂系统设计。另外，由于半导体处理技术的限制，因此可能不能在单个半导体制造过程中制造系统中可能需要的所有的半导体器件。
虽然被封入的多芯片方案缓解了单个芯片方案的一些问题，但使用完全封入的外壳引入一系列的新的挑战。这些外壳(以及它们的相关的封装材料)常常是高度热绝缘的，并因此限制可作为热在器件内被消耗以及被传送通过外壳的功率量。这些设计所需要的严格的功率预算常常不利地影响器件的总体性能。另外，由于外壳材料必须对潜在的探测尝试尽可能地敏感，因此与错误的确实(positive)干预相关的可靠性问题是重要的。
发明内容
本发明的一个实施例提供一种物理上安全的衬底组件，该物理上安全的衬底组件包括衬底、位于衬底上和/或衬底内的电导体、连接电导体中的至少两个电导体的至少一条导电路径、和用于检测电导体中的至少一个电导体的连续性的中断的至少一组电接触。
本发明另一实施例提供一种安全处理组件，该安全处理组件包括具有第一平面表面和第二平面表面的衬底、在第一表面上具有电接触的第一裸片(die)、在第一表面上具有电接触的第二裸片、与第一裸片的电接触中的至少一个电接触连接的第一导电路径、与第二裸片的电接触中的至少一个电接触连接的第二导电路径、围绕第一和第二导电路径的至少一部分的电导体、和与电导体耦接的监视电路。第一裸片被安装在衬底的第一平面表面上，使得第一裸片的电接触位于第一裸片的第一表面和衬底的第一平面表面之间。第二裸片被安装在衬底的第一平面表面上，使得第二裸片的电接触位于第二裸片的第一表面和衬底的第一平面表面之间。第一导电路径的至少一部分位于衬底内，第二导电路径的至少一部分位于衬底内。监视电路检测电导体中的一个或更多个电导体的连续性的中断。
附图说明
与以下的详细说明一起被加入说明书中并形成说明书的一部分的附图用于进一步示出根据本发明的各种实施例并用于解释根据本发明的各种原理和优点，在这些附图中，类似的附图标记在各个图中指的是相同或在功能上类似的要素。
图1是示出根据本发明的实施例的物理上高度安全的多芯片模块的侧视图的框图。
图2是根据本发明的实施例的硅衬底组件的等距视图。
图3是示出硅衬底布线被键合(bond)到芯片载体的图1的物理上高度安全的多芯片模块的侧视图的框图。
图4是根据本发明的实施例的具有贯通通路(through via)的衬底的部分剖面图。
图5A和图5B是图1的裸片和衬底的示图。
具体实施方式
这里如需要的那样公开本发明的详细实施例；但是，应当理解，所公开的实施例仅是可以以各种形式实施的本发明的示例。因此，这里公开的特定结构和功能细节不应被解释为限制，而仅应被解释为权利要求的基础以及用于教导本领域技术人员以几乎任何适当详细的结构通过各种各样的方式来使用本发明的代表性基础。并且，这里使用的术语和短语并不意在限制，而是要提供本发明的可理解的说明。
根据优选实施例的本发明提供物理上高度安全的多芯片模块，而没有与常规的安全外壳相关的诸如高温、有限的功率预算和不稳定(temperamental)的干预对策的限制。
根据本发明的原理，一个实施例提供利用硅上硅(silicon onsilicon)技术的物理上高度安全的多芯片模块。具体而言，在IP安全性的多芯片方案的背景中，倒装芯片硅裸片以使得逆向设计和数据盗窃几乎不可能的方式被直接安装在硅衬底上。
密码术被用于为敏感数据提供数据安全。
密码术实施用于转变数据以隐藏其信息内容、防止其未检测的修改并防止其未授权的使用的原理、手段和方法。密码术涉及通过加密而将普通文本转变成编码的形式(密码文本)和通过解密而将密码文本转变回成明码文本。
用于保护敏感数据的一种当前标准是国家标准技术局(NIST)的联邦信息处理标准(FIPS)140-2密码模块安全要求。该标准可应用于所有使用基于密码的安全系统的联邦机构，以保护计算机和远程通信系统(包括声音系统)中的敏感信息，如在公共法104-106，1996年的信息技术管理改革法的第5131部分中所限定。在按照合同设计和实现联邦部门和机构操作或为其操作的密码模块时，必须遵从该标准。一些私人和商业组织也遵从该标准。
FIPS 140-2标准的一个关键要求是物理安全。在多芯片器件中，一个主要的物理安全弱点在于通过探测芯片之间的互连而逆向设计(即，发现器件的内部工作方式或捕获数据)的能力。本发明的优选实施例通过直接在硅衬底上安装倒装芯片硅裸片而使得互连是无法探测的。在该配置中，连接被夹在裸片和衬底之间以被隐藏。本发明的优选实施例利用材料和技术，以保证多芯片器件在不致使其无用的情况下不能被拆开。
现在参照图1，示出根据本发明的实施例的多芯片计算模块100。模块100包含至少用于实现芯片互连和与外面世界的连接性的硅衬底102。可通过使用常规的“生产线后端”(BEOL)工艺制造硅衬底102。空白晶片跳过制造晶体管结构的标准化学和光刻步骤并直接到BEOL步骤以制造金属层。在硅衬底上形成金属层，以便形成从直接附接到硅衬底102的多个芯片之间的简单直接互连到复杂网型栅格(mesh-type grid)的配置。
图2示出根据本发明的一个实施例的包含电导体204的网型栅格的衬底202的更详细示图。栅格204可被设置在衬底202的外表面206的上面或附近。在该实施例中，电导体相互进出而交织。在其它的实施例中，简单地在十字形图案中设置导体。在另外的实施例中，导体被配置为使得沿相同的方向并且在基本上平行的线中排列所有的导体。导体204可被封入氧化硅中，以使导体204与硅衬底绝缘以及相互绝缘。
图2的网型栅格提供了保护衬底的内部免受探测仪器的引入的优点。如果导体被配置为使得栅格204中的空间足够小，那么探测仪器将不能在导体之间配合(fit)，并且当导体中的一个被接触或破裂时，将导致在栅格中出现不连续性。可以使用监视电路以检测这些不连续性，并且以防止模块的表征的方式来响应(诸如通过删除存储器、将寄存器清零或产生错误读取)。
可以以多种方式实现监视电路228。在一个实施例中，衬底提供有通过外部电路228允许导体中的一个或更多个的连续性测试的接触224和226。可存在用于各个导体的一组接触、与所有导体耦接的一组接触、或者与各接触耦接的导体子集。
监视电路被设置在裸片中的一个或更多个、衬底102、芯片载体110的内部，组件的外部，或其组合。可通过任何一组公知的建立的电测试来检测不连续性。这些测试包含电阻测量、电流测量、电压测量和其组合。
图4示出根据本发明的一个实施例的具有通路的衬底。通路是穿过硅衬底的导电路径。通路可贯穿硅衬底102或仅仅穿过一定数量的层。因此，通路使得附接到衬底表面的部件能够与附接到衬底的同一表面或任何其它表面的其它部件通信。
在图4中示出示例性的通路400。通过打开从衬底的一个表面穿透到相对表面的一个或更多个孔或通道的钻取过程，产生通过硅衬底102的路径。一旦完成钻取过程，就用阻挡层404覆盖整个硅衬底102和通道的内表面区域，该阻挡层404使衬底与即将要被涂敷的导电材料绝缘并防止其扩散到硅衬底102内。在一个实施例中，绝缘阻挡层404是硅硝酸盐，并且利用化学气相沉积(CVD)被沉积。阻挡层404防止置于通道中的导电材料与硅反应，所述硅与其它金属是高度易起反应的。它还用于防止硅在半导体电路的操作中用作导电材料。
用作导电材料的金属物质406被放在通道中。在一个实施例中，金属物质406是铜并且利用物理气相沉积被放置。可以替代性地利用电镀以用金属物质填充通道。如在常规的电镀中那样，过量的材料被沉积在晶片的表面上并且利用化学机械抛光(CMP)被抛去。
本领域技术人员熟悉将导电材料沉积到硅衬底中的通道中所涉及的过程。根据本发明可以使用任何制造方法。
在图2中示出通路214。通路214在硅衬底102的上表面206上的第一接触焊盘(pad)216处开始，并且经由穿过衬底102的整个高度的导电路径222在硅衬底102的下表面220上的第二接触焊盘218处终止。图2还示出在位于衬底102的同一表面206上的部件之间提供电通信的第二类型的通路208。第二类型的通路208在硅衬底102的上表面206上的第一接触焊盘210处开始，并且向下穿过网格204并进入衬底102的内部区域。通路208然后行进到衬底内的更中心的位置，并且从网格204再度出现以在与第一接触焊盘210相同的上表面206上的第二接触焊盘212处终止。
在本发明的其它实施例中，硅衬底102被用于提供诸如内置的去耦电容器、电阻器桥和其它的有源和无源电路的其它电部件和功能。
具有通路208和214以及网格204的衬底102是通过定义清楚的和简化的制造过程制造的，因此导致很少的制造缺陷。由于能够以小于或等于较小的常规芯片的价格制造比典型的芯片大的衬底，因此该架构在经济上是有利的。更具体而言，在包含晶体管的普通芯片上，在器件上的最小的结构(即，晶体管和最小的引线)中导致芯片缺陷的较大部分(bulk)。由于硅衬底仅包含相对较大的金属结构，因此具有缺陷的可能性要小得多。因此，其产量应当高并且制造成本低。
现在重新参照图1，示出两个裸片104和106位于衬底102的顶部上。裸片104和106被安装在“倒装芯片”配置中并被附接到衬底102上。“倒装芯片”附接允许在不需要在其间的引线的情况下将集成电路芯片直接键合到衬底接触上。在该实施例中，通过使用诸如导电糊或焊料“微球”108的导电材料实现倒装芯片附接。芯片104和106被“倒装”，即，上下颠倒，使得芯片的表面上的裸片电接触焊盘与衬底102上的焊盘对准。
少量的导电材料108(即，微球)被设置在芯片的电接触焊盘和衬底上的焊盘之间，使得在其间存在电通信。多芯片计算模块100于是经受升高的温度和压力，以将导电材料108转变成复合物以使得附接变为永久性的。在理想情况下，选择材料使得不破坏模块的功能部分就根本不能将部件分开。优选地，该材料将为诸如锡和铅的瞬变(transient)液体。锡具有低的熔点并与铅结合。在结合出现之后，为了将两者分开，必须使材料经受非常高的温度以达到铅的熔点。
在一个实施例中，导电材料108不是必要的。在该实施例中，裸片和衬底之间的键合是诸如铜对铜键合的金属之间的直接键合。在该实施例中，接触端子中的每一个至少部分地由铜制成。部件经受约400℃的温度和约100psi的压力。铜表面经历“晶粒生长”，这里，它们的价电子层中的外层电子结合以形成永久键。从而，不使单个铜结经受约1083℃(铜的熔点)的温度就不能使该结分开。在该温度，部件将在铜接触分开之前被破坏。
现在来看图5A，进一步示出倒装芯片配置。在图5A中，可以从部分底视图看到裸片104和106。从该底视图中可看到在裸片104和106中的每一个上有四个电接触。裸片104具有电接触501～504，裸片106具有电接触505～508。裸片106还具有附加的一组接触534～537。
图5B表示示例性衬底102的侧视图。该衬底具有三个通路510、512和514。通路510和514产生从衬底的第一平面表面516到衬底的第二平面表面518完全延伸通过衬底102的导电路径。通路512从第一平面表面516上的与第一裸片104的电接触502排齐(line up with)的第一位置延伸，穿过第一平面表面516下面的衬底的一部分，到达第一平面表面516上的与第二裸片106的电接触505排齐的第二位置。通路512使两个裸片104和106相互电通信。
当裸片104和106被旋转(“倒装”)并被放在衬底102的顶部上时，电接触501与通路510对准，电接触502与通路512对准，电接触505与通路512的第二边对准，并且电接触506与通路514对准。焊料微球520或其它类型的导电糊被设置在裸片的电接触和衬底上的焊盘之间，使得在其间存在电通信。该组件然后经受升高的温度和压力，以将微球520转变成复合物以使得附接变为永久性的。
在该实施例中，如从图5A中的裸片104和106的底视图可以看出，电接触501～508有利地分别与裸片104和106的边缘522、524、526和528、530、532隔开。因此，当裸片处于它们的倒装位置并被附接到衬底上时，在裸片和衬底之间插入测量仪器以探测接触变得是极其困难的。
现在重新参照图1，为了进一步增加器件的安全性，使用环氧树脂或其它的粘接剂材料114以封装裸片104和106。环氧树脂封装包含进一步增加用测量探针来探测微凸点(microbump)108或互连球的难度的环氧树脂底层填料(underfill)116。另外，环氧树脂封装114和116使得不破坏芯片104和106而去除它们是不可行的。
通过使得裸片足够薄以至于与其它部件的分离将导致薄件的断裂，而在该实施例中实现进一步的安全性。例如，衬底102在一个实施例中约为50～150微米厚。一般地，裸片约为730微米厚，但在一些实施例中，仅约为350微米厚。
由于器件中的所有结构均处于单个芯片的结构的规模(scale)上，并且在不破坏的情况下拆开系统实际上是不可能的，因此，上述的结构实际上在物理上与单个芯片一样安全。由于微凸点的薄尺寸、使用区域阵列互连的机会、芯片的邻近的放置和层叠或使用3-D硅的机会，因此，探测连接芯片与衬底的微凸点将是十分困难的。
在图1所示的实施例中，硅衬底102位于芯片载体110的顶部。芯片载体110附接到硅衬底102，并使硅衬底102与附接到芯片载体110的其它器件电通信。与附接的倒装芯片/衬底方法类似，硅衬底102通过耦接两个部件102和110的电接触焊盘的多个焊料微球112被附接到芯片载体。这种类型的附接在现有技术中被称为球栅阵列(BGA)。
还能够如图5所示通过以行(in rows)来放置电接触而增加进一步的保护。裸片106具有被一组裸片电接触505～508围绕的一组裸片电接触534～537。使用这种类型的架构，处于外面的、更容易被探测的行505～508中的微凸点可被用于承载非敏感信息或仅仅是功率/接地连接。在其它的实施例中，芯片可被设计为如果芯片被危及安全或被探测就使得敏感信息缺少(default)。可以使用已知的监视电路来影响缺少。
现在参照图3，示出本发明的另一实施例。在图3的实施例中，图1的硅衬底102被键合到芯片载体110，但不是如前面说明的那样通过使用微球。在图3的实施例中，使用诸如环氧树脂、粘接剂、硬件或其它方法的另一附接技术以将硅衬底102键合到芯片载体110。引线302提供从硅衬底102的在本实施例中包含部件的接触的上表面到下面的芯片载体110的导电路径。然后在引线302之上放置环氧树脂材料以形成保护引线免受损害和环境条件的封装114。如果由引线302承载的信息需要被保护以免被监视，如裸片和衬底之间的接触那样，那么，适当地选择引线320和环氧树脂114使得环氧树脂的去除将损坏引线并使得模块不能工作。
因此，本发明允许制造商不必服从诸如高温、有限的功率预算和不稳定的干预对策的与使用安全外壳有关的限制，就可构建具有多个芯片的物理上高度安全的模块，其可被用户定制设计或批量(commodity)和构建于标准逻辑、DRAM、闪存、模拟或另一处理技术上。
这里使用的术语“某一”或“某一个”被定义为一个或多于一个。这里使用的术语“多个”被定义为两个或多于两个。这里使用的术语“另一”被定义为至少第二个或更多个。这里使用的术语“包括”和“具有”被定义为包含(即，开放的语言)。这里使用的术语“耦接”被定义为连接，但不必是直接地，并且不必是机械地。
虽然公开了本发明的特定实施例，但本领域技术人员可以理解，在不背离本发明的精神和范围的条件下，可以对特定实施例进行变化。因此，本发明的范围不应限于特定的实施例，并且其意图在于所附的权利要求覆盖本发明的范围内的任意和全部的这些应用、修改和实施例。

Claims (13)

1.一种物理上安全的衬底组件，包括：
衬底；
位于衬底上和/或衬底内的多个电导体；
连接电导体中的至少两个电导体的至少一条导电路径；和
用于检测电导体中的至少一个电导体的连续性的中断的至少一组电接触。
2.根据权利要求1的物理上安全的衬底组件，其中，导电路径中的至少一条从第一平面表面延伸穿过衬底到达与第一平面表面相对的第二平面表面。
3.根据权利要求1的物理上安全的衬底组件，其中，导电路径中的至少一条从衬底的第一平面表面上的第一位置延伸穿过第一平面表面下的衬底的至少一个层，到达第一平面表面上的第二位置。
4.根据权利要求1的物理上安全的衬底组件，还包括与所述一组电接触耦接的监视电路，所述监视电路检测电导体中的至少一个电导体的连续性的中断。
5.根据权利要求4的安全处理组件，其中，监视电路在检测到连续性的中断时擦除存储器的至少一部分。
6.根据权利要求1的安全处理组件，其中，衬底具有约50～150微米的厚度。
7.一种安全处理组件，包括：
具有第一平面表面和第二平面表面的衬底；
在第一表面上具有电接触的第一裸片，所述第一裸片被安装在衬底的第一平面表面上，使得第一裸片的电接触位于第一裸片的第一表面和衬底的第一平面表面之间；
在第一表面上具有电接触的第二裸片，所述第二裸片被安装在衬底的第一平面表面上，使得第二裸片的电接触位于第二裸片的第一表面和衬底的第一平面表面之间；
与第一裸片的电接触中的至少一个电接触连接的第一导电路径，所述第一导电路径的至少一部分位于衬底内；
与第二裸片的电接触中的至少一个电接触连接的第二导电路径，所述第二导电路径的至少一部分位于衬底内；
围绕第一和第二导电路径的至少一部分的多个电导体；和
与电导体耦接的监视电路，所述监视电路检测电导体中的一个或更多个电导体的连续性的中断。
8.根据权利要求7的安全处理组件，其中，第一和第二导电路径中的至少一条从衬底的第一平面表面延伸穿过衬底到达衬底的第二平面表面。
9.根据权利要求7的安全处理组件，还包括设置在衬底与第一和第二裸片之间的粘接剂材料，所述粘接剂材料永久性地将裸片附接到衬底上。
10.根据权利要求7的安全处理组件，还包括封装第一和第二裸片的环氧树脂材料。
11.根据权利要求7的安全处理组件，其中，监视电路在检测到连续性的中断时擦除存储器的至少一部分。
12.根据权利要求7的安全处理组件，其中，电导体的至少一部分位于衬底的第一平面表面和第二平面表面之间。
13.根据权利要求7的安全处理组件，还包括在衬底的第二平面表面处与第一导电路径和第二导电路径中的至少一条电耦接的芯片载体。
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