CN101232021B - 半导体结构 - Google Patents
半导体结构 Download PDFInfo
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- CN101232021B CN101232021B CN 200810002671 CN200810002671A CN101232021B CN 101232021 B CN101232021 B CN 101232021B CN 200810002671 CN200810002671 CN 200810002671 CN 200810002671 A CN200810002671 A CN 200810002671A CN 101232021 B CN101232021 B CN 101232021B
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Abstract
本发明涉及一种半导体结构,包括:半导体基底;第一导电型的第一金属氧化物半导体装置,包括:第一栅极介电层,形成于半导体基底上;含有金属的第一栅极电极层,形成于第一栅极介电层上;硅化层,形成于含有金属的第一栅极电极层上;以及第二导电型的第二金属氧化物半导体装置,其导电型与第一导电型相反,包括:第二栅极介电层,形成于半导体基底上;含有金属的第二栅极电极层,形成于第二栅极介电层上;以及接触蚀刻停止层,具有一部分形成于含有金属的第二栅极电极层上,其中介于接触蚀刻停止层的上述部分与含有金属的第二栅极电极层之间的区域实质上不含硅。本发明可以取其利用具有能带边缘的功函数的优点,同时克服耗尽效应等缺陷。
Description
技术领域
本发明涉及一种半导体装置,且特别涉及一种金属氧化物半导体(MOS)装置的结构与制造方法。
背景技术
MOS装置是在集成电路中基本的构造元件。一般而言,公知的金属氧化物半导体装置,具有包含掺杂有P型或N型不纯物的多晶硅栅极电极,此金属栅极使用例如离子注入或热扩散的掺杂操作所形成的。较佳的实施方式,是将上述栅极电极的功函数调整至其硅原子的能带边缘(band-edge)。也就是,针对N型金属氧化物半导体(NMOS)装置,调整此栅极电极的功函数至接近导带(conduction band);针对P型金属氧化物半导体(PMOS)装置,则调整其功函数至接近价带(valance band)。通过选择适当的不纯物,即可实现上述栅极电极的功函数的调整。
具有多晶硅栅极电极的MOS装置会呈现出载流子耗尽效应(carrierdepletion effect),此效应也可当作是多晶硅耗尽效应。其中此多晶硅耗尽效应是在使用电场清除靠近栅极介电层的电子,形成耗尽层(depletion layer)时所发生的。在掺杂有N型不纯物的多晶硅层中,此耗尽层包含离子化的不可移动的受体部位(donor site),而在掺杂有P型不纯物的多晶硅层中,此耗尽层则包含离子化的不可移动的施体部位(acceptor site)。值得注意的是,此耗尽效应会造成有效栅极介电层的厚度增加,而使得要在此半导体表面上形成反转层(inversion layer)更为困难。
使用薄的栅极介电层会使得此载流子耗尽效应更趋严重(worse)。当使用薄的栅极介电层时,上述多晶硅栅极中的耗尽层的厚度相比于此薄的栅极介电层的厚度会变得更明显,因而使得装置的性能降低得更严重。由于可减少的有效栅极介电层的厚度有限,因此,上述栅极电极中的载流子耗尽效应会限制住装置的可调整尺寸的能力(scalability)。
现有发明通过形成金属栅极电极或金属硅化物栅极电极来解决上述的载流子耗尽效应,其中在NMOS装置及PMOS装置中所使用的金属栅极较佳为具有能带边缘(band-edge)的功函数。目前已经发现可适用于形成NMOS装置的金属栅极材料,例如碳化钽(TaC)。然而,对于PMOS装置,即使具有能带边缘功函数的金属材料已被开发出来,但这些材料的热稳定性都很差。当这些材料暴露在前段工艺的高温下,其功函数会朝向例如中间能隙的能阶移动(shift)。因而对于所产生的PMOS装置的性能会有不利的影响。
现有的形成双金属互补型金属氧化物半导体(CMOS)工艺的方法主要包含两种,即前栅极(gate-first)与后栅极(gate-last)工艺法。一般而言,前栅极工艺法具有两种不同功函数的金属层,分别形成于PMOS区与NMOS区。随后图案化此金属层,以形成栅极电极。然后再形成其他例如间隔层、轻掺杂的源极/漏极区、源极/漏极区、硅化层及接触蚀刻停止层等MOS装置的元件。此工艺相当简单,且形成连续的接触蚀刻停止层,使其可以有效地施加应力。然而,因为这些金属栅极形成于轻掺杂的源极/漏极区(LDD)及源极/漏极区的活化与形成步骤之前,所以它们会遭遇到高的热预算,因而可能会造成PMOS装置的功函数的移动。此外,通过蚀刻来图案化金属层是相当困难的。
另一方面,后栅极工艺法一般包括形成PMOS装置与NMOS装置的虚置栅极(dummy gate)的步骤。随后再形成轻掺杂的源极/漏极区、栅极间隔层、源极/漏极区及接触蚀刻停止层。接下来,移除PMOS装置与NMOS装置的虚置栅极,再填入具有不同功函数的金属至PMOS装置与NMOS装置的开口内。在上述后栅极工艺中,因为PMOS装置与NMOS装置的金属栅极形成于轻掺杂的源极/漏极区及源极/漏极区的活化与形成步骤之后,所以这些栅极金属具有低的热预算。然而,上述工艺是很复杂的。此外,在移除上述虚置栅极的步骤期间,也会移除接触蚀刻停止层覆盖在此栅极上的部分,而造成此接触蚀刻停止层施加应力的能力明显降低。
因此,在现有技术中,需要一种半导体结构与双金属栅极的各自形成的方法,以取其利用具有能带边缘的功函数的优点,同时可克服上述现有技术的缺点。
发明内容
本发明的目的在于提出一种半导体结构,以取其利用具有能带边缘的功函数的优点,同时克服上述耗尽效应等导致的缺陷。
本发明提供一种半导体结构,包括:半导体基底;第一导电型的第一金属氧化物半导体装置,包括:第一栅极介电层,形成于该半导体基底上;含有金属的第一栅极电极层,形成于该第一栅极介电层上,其中该含有金属的第一栅极电极层包括一金属层与一多晶硅层,该金属层形成于该第一栅极介电层上,而该多晶硅层形成于该金属层之上;硅化层,形成于该多晶硅层上;以及第二导电型的第二金属氧化物半导体装置,其导电型与该第一导电型相反,包括:第二栅极介电层,形成于该半导体基底上;含有金属的第二栅极电极层,形成于该第二栅极介电层上;以及接触蚀刻停止层,具有一部分形成于该含有金属的第二栅极电极层上,其中介于该接触蚀刻停止层的该部分与该含有金属的第二栅极电极层之间的区域实质上不含硅。
如上所述的半导体结构,其中该接触蚀刻停止层包含一部分形成于该硅化层上。
如上所述的半导体结构,其中该含有金属的第一栅极电极层具有约小于4.4eV的功函数,且其中该含有金属的第二栅极电极层具有约大于4.9eV的功函数。
如上所述的半导体结构,其中该含有金属的第一栅极电极层包含钽。
如上所述的半导体结构,其中该第一金属氧化物半导体装置还包含至少黏着层及覆盖层其中之一,且其中该黏着层介于该第一栅极介电层与该含有金属的第一栅极电极层之间,且该覆盖层形成于该含有金属的第一栅极电极层上。
如上所述的半导体结构,其中该第二金属氧化物半导体装置还包含黏着层,该黏着层介于该第二栅极介电层与该含有金属的第二栅极电极层之间。
如上所述的半导体结构,其中该第一金属氧化物半导体装置还包括:源极/漏极区,邻接该第一栅极介电层;硅化区,形成于该源极/漏极区上,其中该硅化区与该硅化层包含不同的金属。
如上所述的半导体结构,其中该第一金属氧化物半导体装置为N型金属氧化物半导体装置,且该第二金属氧化物半导体装置为P型金属氧化物半导体装置。
本发明还提供一种半导体结构,包括:半导体基底;N型金属氧化物半导体装置,包括:第栅极介电层,形成于该半导体基底上;含有金属的第一栅极电极层,形成于该第一栅极介电层上,其中该含有金属的第一栅极电极层包括一金属层与一多晶硅层,该金属层形成于该第一栅极介电层上,而该多晶硅层形成于该金属层之上;硅化区,形成于该多晶硅层上;以及第一接触蚀刻停止层,其具有一部分在该硅化区上,且以物理接触该硅化区;以及P型金属氧化物半导体装置,包括:第二栅极介电层,形成于该半导体基底上;含有金属的第二栅极电极层,形成于该第二栅极介电层上,其中该含有金属的第一栅极电极层具有第一功函数,且该第一功函数与该含有金属的第二栅极电极层的第二功函数不同;以及第二接触蚀刻停止层,具有一部分形成于该含有金属的第二栅极电极层上,且以物理接触该含有金属的第二栅极电极层。
如上所述的半导体结构,其中该第一功函数低于该第二功函数。
如上所述的半导体结构,其中该第一功函数约低于4.4eV,且该第二功函数约大于4.9eV。
如上所述的半导体结构,其中该含有金属的第一栅极电极层包含钽,且该含有金属的第二栅极电极层包含金属,该金属择自实质上由钨、钌及钼或其组合所组成的族群。
如上所述的半导体结构,其中该N型金属氧化物半导体装置还包括:源极/漏极区,邻接该第一栅极介电层;以及外加的硅化区,形成于该多晶硅层上,其中该硅化区与该外加的硅化区包含不同的金属。
如上所述的半导体结构,其中该第一与该第二接触蚀刻停止层属于同一层。
本发明还提供一种半导体结构,包括:半导体基底;第一导电型的第一金属氧化物半导体装置,包括:第一栅极介电层,形成于该半导体基底上;含有金属的第一栅极电极层,形成于该第一栅极介电层上;具有第一部分的第一接触蚀刻停止层,形成于该含有金属的第一栅极电极层上;第一区域,介于该具有第一部分的第一接触蚀刻停止层与该含有金属的第一栅极电极层之间;以及第二导电型的第二金属氧化物半导体装置,其导电型与该第一导电型相反,该第二金属氧化物半导体装置包括:第二栅极介电层,形成于该半导体基底上;含有金属的第二栅极电极层,形成于该第二栅极介电层上; 具有第二部分的第二接触蚀刻停止层,形成于该含有金属的第二栅极电极层上;以及第二区域,介于该含有金属的第二栅极电极层与该具有第二部分的第二接触蚀刻停止层之间,其中该第一区域包含比该第二区域还多的硅。
因此,本发明可以取其利用具有能带边缘的功函数的优点,同时克服耗尽效应等导致的缺陷。
附图说明
图1至图13为一系列的按照本发明实施例所制造的半导体结构的剖面图。
并且,上述附图中的各附图标记说明如下:
20 基底
24、124、224 栅极介电层
26、50、126、226 金属层
28、128、228 多晶硅层
29、129、229 掩模层
30、246 黏着层
32 覆盖层
42 涂布层
54 接触蚀刻停止层
56 层间介电层
100 NMOS区
134、234 栅极堆叠层
136、236 轻掺杂的源极与漏极
138、238 源极/漏极区
139 碳化硅(SiC)应力层
140、240 间隔层
141、241 硅化区
152 硅化层
160NMOS 装置
200 PMOS区
224 栅极介电层
239 硅锗(SiGe)应力层
244 金属材料层
248 栅极电极
260 PMOS装置
具体实施方式
本发明较佳实施例的制造与使用的说明详述如下,然而,值得注意的是,本发明提供许多可应用的发明概念并于特定的内容中广泛地具体说明。这些实施例仅以特定的附图阐述本发明的制造与使用,但不用以限制本发明的范围。
本发明提供一种形成具有双金属栅极的互补型金属氧化物半导体的混合的方法。此混合的方法结合前栅极与后栅极工艺方法,以获得较佳的效果。以下通过各种附图及图例说明本发明较佳实施例的制造过程,本发明各种不同的实施例中,相同的符号代表相同或类似的元件。
请参照图1,提供基底20,此基底可由例如本体硅基底(bulk silicon)、绝缘层上覆硅(SOI)、硅锗(SiGe)、嵌入式硅锗(SiGe)以及锗或类似的材料等一般所使用的半导体材料或结构来形成。首先,形成浅沟槽绝缘区(图未显示)于基底20内,此隔离区用以定义NMOS区100与PMOS区200。随后于基底20上,形成栅极介电层24、金属层26、多晶硅层28以及掩模层29。在一个实施例中,使用氧化硅来形成栅极介电层24。而在其他实施例中,栅极介电层24包含具有高介电常数(high-k)的材料,具体的高介电常数材料包含例如氧化铪(HfO2)、氧化锆(ZrO2)、硅酸氮氧硅铪(HfSiON)、以及例如锆氧化物铪(HfZrO)、钽氧化物铪(HfTaO)、钛氧化物铪(HfTiO)以及铝氧化物铪(HfAlO)的金属合金属氧化物化物或其组合。在一个具体实施例中,栅极介电层24的厚度约介于1nm与10nm之间。此外,本领域技术人员将可了解,全文中所叙述的厚度与其他的尺寸有关于此集成电路的形成技术的等级(scale)。
较佳的金属层26具有适合用以形成NMOS装置的功函数(workfunction),且此功函数较佳约介于4.0eV与4.4eV之间,且更佳约接近能带 边缘的4.1eV。上述具体的材料包括例如碳化钽(SiC)、氮化钽(TaN)及氮化硅钽(TaSiN)或其组合的含有钽的材料。此外,金属层26可具有约介于1nm与10nm之间的厚度。其中,栅极介电层24与金属层26的形成方法可包括原子层沉积(ALD);物理气相沉积(PVD);有机金属化学气相沉积(MOCVD)或类似的方法。
多晶硅层28可具有约30nm与100nm之间的厚度。此多晶硅层28的功能包括避免金属层26的污染以及维持堆叠层的高度到方便于现有工艺进行的高度。另外,掩模层29较佳可由例如氮化硅、氮氧化硅、碳化硅或类似的介电材料来形成。
在一个可替代的实施例中,黏着层30及/或覆盖层32可以分别形成于金属层26的上下位置。在较佳的实施例中,黏着层30用以改善栅极介电层24与金属层26之间的黏着性,且可进一步避免栅极介电层24与金属层26之间的交互作用及/或反应。而覆盖层32是用以避免上述金属层26的氧化。此外,黏着层30与覆盖层32可各自包含氮化钛(TiN)、氮化硅钽(TaSiN)或其组合。上述的黏着层30与覆盖层32各自的厚度,较佳约介于1nm与10nm之间。如果有形成黏着层30与覆盖层32,黏着层30与覆盖层32的厚度将保留在此所形成的NMOS装置中。为了简化,此两层并未显示于随后的附图中。
图2显示图案化上述所形成的堆叠层,分别形成栅极堆叠层134于NMOS装置100中,以及栅极堆叠层234于PMOS装置200中。其中栅极堆叠层134包含栅极介电层124、金属层126、多晶硅层128以及掩模层129。而栅极堆叠层234包含栅极介电层224、金属层226、多晶硅层228以及掩模层229。上述包含金属层226及多晶硅层228的栅极电极将于随后的步骤中移除,因此,将其作为选择性的虚置栅极。
接着如图3A显示,可通过注入N型不纯物,以在NMOS装置100中形成轻掺杂的源极与漏极(LDD)区136。同样地,较佳可利用注入P型不纯物,以在PMOS装置200中形成轻掺杂的源极与漏极区236。当注入NMOS装置100及PMOS装置200其中之一时,在注入前先形成掩模层以遮蔽不要注入的另一方。随后形成间隔层140及240。间隔层140及240均可包括单层或复合层(composite layer),例如形成于衬底氧化层(oxide liner)上的氮化硅层。 在随后的步骤中,分别形成源极及/或漏极区(此后以源极/漏极区来表示)138及238于NMOS装置100及PMOS装置200中。图3B显示本发明另一个代替的实施例,此实施例通过形成应力层(stressors)来改善沟道区的应力。在PMOS装置200中,可形成硅锗(SiGe)应力层239,以施加压缩应力于上述各自的PMOS装置的沟道区,而在NMOS装置100中,则形成碳化硅(SiC)应力层139,其施加拉伸应力于上述各自的NMOS装置的沟道区。此外,进行例如快速热退火(RTA)、激光退火(Laser anneal)、快闪退火(flash anneal)的退火工艺,以活化轻掺杂的源极与漏极区136及236与源极/漏极区138及238。在此较佳实施例中,上述的活化步骤可在形成PMOS装置的金属栅极前的任何时候来进行,此步骤如图8所示。由于形成轻掺杂的源极与漏极区136及236、间隔层140及240以及源极/漏极区138及238的详细工艺均为公知的技术,故此处不再重复叙述。
图4显示分别在源极/漏极区138上形成硅化区141,以及在源极/漏极区238上形成硅化区241的硅化工艺。此硅化工艺可包括以毯覆式形成金属层,此金属层包括镍(Ni)、铂(Pt)、钯(Pd)、钛(Ti)、钴(Co)或其组合,且加热此基底,使得在源极/漏极区138及238上的硅与所接触的上述金属反应,因而形成金属硅化区。随后通过使用会攻击金属但不会攻击硅化物的蚀刻剂,以选择性的移除上述未反应的金属。
图5显示涂布层42的形成方式,其顶部表面高于掩模层129及229的顶部表面。在一个实施例中,涂布层42包含例如一般使用于层间介电层(ILD)的介电材料,此材料包括含碳的氧化物。在其他的实施例中,涂布层42为光致抗蚀剂层。
请参照图6,进行化学机械研磨工艺(CMP),以移除部分的涂布层42,以及掩模层129及229,使露出多晶硅层128及228。在以光致抗蚀剂所形成的涂布层42的例子中,此涂布层42可通过研磨或回蚀刻以露出掩模层129及229。
图7显示选择性的移除上述包含多晶硅层228与金属层226的虚置栅极。其中多晶硅层228可使用干式或湿式蚀刻来移除,但较佳使用湿式蚀刻来移除金属层226,以避免损伤其下层的栅极介电层224。移除此虚置栅极后,便露出栅极介电层224。
请参照图8,填入金属材料层244至上述虚置栅极移除后所留下的开口中,此金属材料可具有适合用以形成PMOS装置的功函数。此外,较佳的金属材料层244具有低电阻率与良好的间隙填充能力(Gap filling)。在一个具体实施例中,金属材料层244可包括用来实现所需的功函数的金属层及用来改善间隙填充能力的金属层。其中用来实现所需的功函数的金属层较佳具有约介于1nm与5nm之间的厚度,而用来改善间隙填充能力的金属层较佳包含例如钨(W)的具有良好的间隙填充能力的材料。金属材料层244(假如金属材料层244包含超过一层,则为用来改善间隙填充能力的金属层)的较佳功函数约介于4.9eV与5.2eV之间,且更佳约为接近能带边缘功函数的5.2eV。上述具体的材料包含例如钨(W)及氮化钨(WN)的含有钨的材料、例如钌(Ru)及钌氧化物的含有钌的材料、以及例如钼(Mo)及氮化钼(MoN)的含有钼的材料或其组合。另外,可选择在金属材料层244的形成步骤之前,先形成黏着层246,以改善金属材料层244与栅极介电层224之间的黏着性,其中黏着层246可包含氮化钛(TiN)、氮化钽(TaN)及氮化硅钽(TaSiN)或其组合。且黏着层246的厚度较佳约介于1nm与5nm之间。为了简化,黏着层246未显示于后续的附图中。此外,黏着层246与金属材料层244的形成方法包括原子层沉积(ALD);物理气相沉积(PVD);有机金属化学气相沉积(MOCVD)或类似的方法。更佳的方法为低温的形成法,可降低上述所形成的栅极电极的功函数的偏移。
图9显示过量的金属材料层244的移除,可通过化学机械研磨或湿式蚀刻来完成。在移除金属材料层244后,也会露出多晶硅层128。最后余留下来的金属材料层244,便成为上述所形成的PMOS装置中的栅极电极248。
随后将多晶硅层128的顶部的部分硅化。请参照图10,毯覆式沉积薄的金属层50并加热,以形成如图11所示的硅化层152。然后再移除未反应的金属层50。此外,因为硅化层152及源极/漏极硅化区141与241是分开来形成的,所以它们可能包含不同的金属硅化物(salicide)。例如,源极/漏极硅化区141与241可能包含热稳定的金属,而硅化层152可能包含具有良好的阻值下降特性的金属。
图12显示将涂布层42移除。在由氧化物所形成的涂布层42的例子中,可使用稀释的氢氟酸(HF)移除涂布层42。如果涂布层42是由光致抗蚀剂所 形成的,则使用标准的去光致抗蚀剂工艺来移除涂布层42。接下来,如图13所示,在后续的步骤中,形成接触蚀刻停止层(CESL)54及层间介电层56,其中接触蚀刻停止层54较佳具有固有应力。由于详细的接触蚀刻停止层54为公知的技术,因此,此处不再重复叙述。本领域技术人员将可了解,接触蚀刻停止层54可在NMOS区100中形成第一部分,以及在PMOS区200中形成第二部分,且上述第一及第二部分可具有不同的应力。值得注意的是,因为接触蚀刻停止层54是在栅极电极的形成步骤之后形成的,所以有部分的接触蚀刻停止层54直接覆盖于多晶硅层128与栅极电极248上,且此部分还与覆盖于所有的上述NMOS装置160与PMOS装置260的各自的源极与漏极区上的部分接触蚀刻停止层54桥接。因此,相比于传统的后栅极工艺方法,较大的应力可通过接触蚀刻停止层54施加到NMOS装置160与PMOS装置260的沟道区。
上述NMOS装置160的栅极电极的功函数是由金属层126的功函数所决定,其中金属层126与栅极电极248中的金属不同。因此,在NMOS装置160与PMOS装置260中的栅极电极都可具有能带边缘的功函数,以供适当的材料使用。在此较佳实施例中,使用前栅极工艺法作为NMOS装置160的金属栅极的形成方法,此工艺方法节省了移除虚置栅极、填入金属材料及化学机械研磨等工艺的成本。另一方面,使用后栅极工艺法作为PMOS装置260的金属栅极的形成方法。此外,因为栅极电极248是在轻掺杂区136及236与源极/漏极区138及238的活化与形成步骤之后形成的,所以施加在栅极电极248的热预算是很低的,因而降低栅极电极248的功函数的偏移。值得注意的是,NMOS装置160的金属层126,即使在高温下退火仍然相当的稳定,且具有明显较低的功函数偏移。
虽然本发明已以较佳实施例公开如上,但是其并非用以限定本发明,任何本领域技术人员在不脱离本发明的精神和范围内可做改动与润饰,因此本发明的保护范围当视随附的权利要求所界定的范围为准。
Claims (14)
1.一种半导体结构,包括:
半导体基底;
第一导电型的第一金属氧化物半导体装置,包括:
第一栅极介电层,形成于该半导体基底上;
含有金属的第一栅极电极层,形成于该第一栅极介电层上,其中该含有金属的第一栅极电极层包括一金属层与一多晶硅层,该金属层形成于该第一栅极介电层上,而该多晶硅层形成于该金属层之上;以及
硅化层,形成于该多晶硅层上;
以及,第二导电型的第二金属氧化物半导体装置,其导电型与该第一导电型相反,包括:
第二栅极介电层,形成于该半导体基底上;
含有金属的第二栅极电极层,形成于该第二栅极介电层上;以及
接触蚀刻停止层,具有一部分形成于该含有金属的第二栅极电极层上,其中介于该接触蚀刻停止层的该部分与该含有金属的第二栅极电极层之间的区域不含硅,且该含有金属的第一栅极电极层中的金属与该含有金属的第二栅极电极层中的金属不同。
2.如权利要求1所述的半导体结构,其中该接触蚀刻停止层包含一部分形成于该硅化层上。
3.如权利要求1所述的半导体结构,其中该含有金属的第一栅极电极层具有小于4.4eV的功函数,且其中该含有金属的第二栅极电极层具有大于4.9eV的功函数。
4.如权利要求1所述的半导体结构,其中该含有金属的第一栅极电极层包含钽。
5.如权利要求1所述的半导体结构,其中该第一金属氧化物半导体装置还包含至少黏着层及覆盖层其中之一,且其中该黏着层介于该第一栅极介电层与该含有金属的第一栅极电极层之间,且该覆盖层形成于该含有金属的第一栅极电极层上。
6.如权利要求1所述的半导体结构,其中该第二金属氧化物半导体装置还包含黏着层,该黏着层介于该第二栅极介电层与该含有金属的第二栅极电极层之间。
7.如权利要求1所述的半导体结构,其中该第一金属氧化物半导体装置还包括:
源极/漏极区,邻接该第一栅极介电层;
硅化区,形成于该源极/漏极区上,其中该硅化区与该硅化层包含不同的金属。
8.如权利要求1所述的半导体结构,其中该第一金属氧化物半导体装置为N型金属氧化物半导体装置,且该第二金属氧化物半导体装置为P型金属氧化物半导体装置。
9.一种半导体结构,包括:
半导体基底;
N型金属氧化物半导体装置,包括:
第一栅极介电层,形成于该半导体基底上;
含有金属的第一栅极电极层,形成于该第一栅极介电层上,其中该含有金属的第一栅极电极层包括一金属层与一多晶硅层,该金属层形成于该第一栅极介电层上,而该多晶硅层形成于该金属层之上;
硅化层,形成于该多晶硅层上;以及
第一接触蚀刻停止层,其具有一部分在该硅化层上,且以物理接触该硅化层;
以及,P型金属氧化物半导体装置,包括:
第二栅极介电层,形成于该半导体基底上;
含有金属的第二栅极电极层,形成于该第二栅极介电层上,其中该含有金属的第一栅极电极层具有第一功函数,且该第一功函数与该含有金属的第二栅极电极层的第二功函数不同,且该含有金属的第一栅极电极层中的金属与该含有金属的第二栅极电极层中的金属不同;以及
第二接触蚀刻停止层,具有一部分形成于该含有金属的第二栅极电极层上,且以物理接触该含有金属的第二栅极电极层。
10.如权利要求9所述的半导体结构,其中该第一功函数低于该第二功函数。
11.如权利要求10所述的半导体结构,其中该第一功函数低于4.4eV,且该第二功函数大于4.9eV。
12.如权利要求10所述的半导体结构,其中该含有金属的第一栅极电极层包含钽,且该含有金属的第二栅极电极层包含金属,该金属择自由钨、钌及钼或其组合所组成的族群。
13.如权利要求10所述的半导体结构,其中该N型金属氧化物半导体装置还包括:
源极/漏极区,邻接该第一栅极介电层;以及
硅化区,形成于该多晶硅层上,其中该硅化层与该硅化区包含不同的金属。
14.如权利要求9所述的半导体结构,其中该第一与该第二接触蚀刻停止层属于同一层。
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TWI379385B (en) | 2012-12-11 |
CN101232021A (zh) | 2008-07-30 |
US7812414B2 (en) | 2010-10-12 |
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