CN101227800A - Apparatus and method for implementing high-precision buried resistance - Google Patents
Apparatus and method for implementing high-precision buried resistance Download PDFInfo
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- CN101227800A CN101227800A CNA2008100575624A CN200810057562A CN101227800A CN 101227800 A CN101227800 A CN 101227800A CN A2008100575624 A CNA2008100575624 A CN A2008100575624A CN 200810057562 A CN200810057562 A CN 200810057562A CN 101227800 A CN101227800 A CN 101227800A
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- resistance
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Abstract
The invention discloses a method for realizing embedding resistance with high accuracy and a device, which belongs to the field of electronic equipment. The method comprises: etching prearranged embedded resistance pattern connecting terminals and a conducting layer outside interconnecting circuits in a non embedded resistance zone, obtaining molded dimension on the embedding resistance length direction and the interconnecting circuits in the non embedded resistance zone, measuring the molded dimension on the embedding resistance length direction, calculating correctional molded dimension on the embedding resistance length direction, and etching a resistance layer to obtain molded embedded resistance according to the correctional molded dimension on the embedding resistance length direction. The technical scheme of the invention firstly etches the molded dimension on the embedding resistance length direction and the interconnecting circuits in the non embedded resistance zone and then errors which are produced by etching the molded dimension on the embedding resistance length direction are corrected through etching the molded dimension on the embedding resistance length direction, which is beneficial for increasing the resistance precision of the embedding resistance which is finally molded and enables an embedding resistance producing technique to be controlled easier.
Description
Technical field
The present invention relates to electronic device field, particularly a kind of method and device of realizing high-precision buried resistance.
Background technology
It is to adopt conventional printed board subtractive process production technology that the resistance technology is buried on the plane, and resistance is integrated in the multilayer printed board.The resistance technology is buried on the plane becomes in the circuit design mature technique the most with its high-performance, low cost and long-term stability.The plane is buried resistance technology utilization and is had following advantage: electric property is good, bury resistance density higher, bury the resistance better reliability and cost lower.Burying the resistance structure chart is made of trilaminate material as shown in Figure 1: copper foil layer 1 (also can be other conductor layer), nickel-phosphorus alloy firm 2 (also can be other resistive layer) and insulating substrate 3.
Prior art provides a kind of method of utilizing the processing of conventional P WB (Printed Wire Board, printed substrate) exposure etch process to bury resistance, and the idiographic flow of this method is as follows:
The first, coat photoresist 4 at copper foil layer 1, utilize exposure and developing technique to obtain composite diagram, as shown in Figure 2.
The second, the copper foil layer 1 beyond the etching compound pattern, the nickel-phosphorus alloy firm 2 beyond the etching compound pattern cleans photoresist 4 then, obtains burying the forming dimension of resistance Width, successively as Fig. 3, Fig. 4 and shown in Figure 5.
Four, will bury resistance length mask 5 covers on the compound pattern, as shown in Figure 6.
The 5th, the unwanted copper foil layer 1 of etching cleans and buries resistance length mask 5, obtains burying the forming dimension of resistance length direction, thereby obtains the final resistance of burying, as shown in Figure 7 and Figure 8.
In realizing process of the present invention, the inventor finds that there are the following problems at least in the prior art:
The first, existing burying in the resistance work flow, no matter be the forming dimension of the etching length direction that buries resistance or the forming dimension that the resistance Width is buried in etching, the copper foil layer thickness that need etch away is bigger, when the etching copper foil layer, can produce trapezium effect, thereby the precision that directly causes the lateral etch size to be shaped is relatively poor, the final resistance accuracy that buries resistance that is shaped of influence.
The second, existing burying in the resistance work flow need the thickness of strict control copper foil layer, but the copper foil layer of etching different-thickness needs different technological parameters, and this can cause the technology controlling and process more complicated.
Summary of the invention
Bury the easier control of resistance processing technology in order to improve the resistance accuracy that buries resistance of final shaping, to make, the embodiment of the invention provides a kind of method and device of realizing high-precision buried resistance.Described technical scheme is as follows:
Etch preset is buried resistance figure splicing ear and the non-resistance regional interconnection circuit conductor layer in addition that buries, and obtains burying the forming dimension and the non-resistance regional interconnection circuit that buries of resistance length direction;
Measure the described forming dimension that buries the resistance length direction;
The forming dimension that buries the resistance length direction according to described measurement calculates the forming dimension of revising that buries the resistance Width;
According to the forming dimension that buries the resistance Width of described correction, the etching resistive layer, what obtain being shaped buries resistance.
A kind of device of realizing high-precision buried resistance, described device comprises:
Bury resistance length direction forming dimension acquisition module, be used for etch preset and bury resistance figure splicing ear and the non-resistance regional interconnection circuit conductor layer in addition that buries, obtain burying the forming dimension and the non-resistance regional interconnection circuit that buries of resistance length direction;
Measurement module is used to measure the described forming dimension that buries the resistance length direction that obtains;
Bury resistance Width forming dimension computing module, be used for calculating the forming dimension of revising that buries the resistance Width according to the forming dimension that buries the resistance length direction of described measurement;
Bury resistance Width forming dimension acquisition module, be used for the forming dimension that buries the resistance Width according to described correction, the etching resistive layer, what obtain being shaped buries resistance.
Technical scheme of the present invention is buried resistance figure splicing ear and the non-resistance regional interconnection line pattern conductor layer in addition that buries by etch preset, obtains burying the forming dimension and the non-resistance regional interconnection circuit that buries of resistance length direction; Measure the forming dimension that buries the resistance length direction again, according to the forming dimension of measuring that buries the resistance length direction forming dimension that buries the resistance Width is revised, and according to the forming dimension etching resistive layer of revising that buries the resistance Width, the trapezium effect that can partly avoid etching and brought, thereby help to improve the resistance accuracy that buries resistance of final shaping, make and bury the easier control of resistance processing technology.
Description of drawings
Fig. 1 is that the resistance material that buries that prior art provides is formed structure chart;
Fig. 2 is that obtaining of providing of prior art buried the schematic diagram that resistance meets figure;
Fig. 3, Fig. 4 and Fig. 5 are the schematic diagrames that obtains burying resistance Width forming dimension that prior art provides;
Fig. 6 is that the resistance width mask that buries that prior art provides covers schematic diagram on the compound pattern;
Fig. 7, Fig. 8 are the schematic diagrames that the forming dimension of resistance length direction is buried in etching that prior art provides;
Fig. 9 is a kind of method that realizes high-precision buried resistance that the embodiment of the invention provides;
Figure 10, Figure 11 are the schematic diagrames that the forming dimension of resistance length direction is buried in etching that the embodiment of the invention provides;
Figure 12 be the embodiment of the invention provide bury resistance zone and the non-schematic diagram that buries resistance regional interconnection circuit;
Figure 13 and Figure 14 are the schematic diagrames that the forming dimension of resistance Width is buried in etching that the embodiment of the invention provides;
Figure 15 is a kind of composition schematic diagram of realizing the device of high-precision buried resistance that the embodiment of the invention provides.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, embodiment of the present invention is described further in detail below in conjunction with accompanying drawing.
The embodiment of the invention provides a kind of method that realizes high-precision buried resistance, and this method is buried resistance figure splicing ear and the non-resistance regional interconnection circuit copper foil layer in addition that buries by etch preset, obtains burying the forming dimension and the non-resistance regional interconnection circuit that buries of resistance length direction; Measure the forming dimension that buries the resistance length direction again, computing formula according to the resistance of burying resistance, the forming dimension that buries the resistance Width is revised, according to the forming dimension etching nickel-phosphorus alloy firm of revising that buries the resistance Width, the trapezium effect that can partly avoid etching and brought, thereby help to improve the resistance accuracy that buries resistance of final shaping, make and bury the easier control of resistance processing technology.Referring to Fig. 9, the concrete steps of the embodiment of the invention are as follows:
Step 101: etch preset is buried resistance figure splicing ear and the non-resistance regional interconnection circuit copper foil layer in addition that buries, and obtains burying the forming dimension and the non-resistance regional interconnection circuit that buries of resistance length direction, and idiographic flow as shown in Figure 10 and Figure 11.
Earlier coat photoresist at copper foil layer, utilize exposure and developing technique to obtain the default photoresist mask that hinders figure splicing ear correspondence that buries burying the resistance zone again, at the non-regional photoresist mask that obtains the interconnection line correspondence of resistance that buries, the etching copper foil layer cleans forming dimension and the non-resistance regional interconnection circuit that buries that the photoresist mask obtains burying the resistance length direction at last then.Wherein, bury the resistance zone and be meant the zones of burying resistance 6 and splicing ear 8 common coverings, be meant with default and bury the circuit that resistance figure splicing ear links to each other that splicing ear 8 is meant to realize burying and hinders the conductor structure that is connected with other interconnection line but not bury resistance regional interconnection circuit 7, specifically as shown in figure 12.
Need to prove, when the forming dimension of resistance length direction is buried in etching, can adopt alkali etching technology in this step, can't damage nickel-phosphorus alloy firm like this.In the present embodiment, nickel-phosphorus alloy firm is as resistive layer, but is not limited to nickel-phosphorus alloy firm in the practical application; Get copper foil layer as conductor material, but conductor material is not limited to copper foil layer in actual applications.
Step 102: measure the forming dimension that buries the resistance length direction.
In step 101, owing to have trapezium effect during the etching copper foil layer, cause the bad control of size of the nickel-phosphorus alloy firm that comes out, the error of the forming dimension that buries the resistance length direction that etches like this is bigger.In this step, bury the forming dimension of resistance length direction by measurement, that learns the forming dimension that buries the resistance length direction exists error, in order to guarantee to bury the resistance accuracy of resistance, need hinder the width mask to burying of definition and revise, bury the error that the forming dimension of resistance length direction causes to compensate etching.
Step 103: calculate the forming dimension of revising that buries the resistance Width according to the forming dimension of measuring that buries the resistance length direction.
The resistance of burying resistance equals to bury the square resistance of resistance material and buries the product (square resistance is a constant) of resistance length-width ratio.According to the resistance computing formula of burying resistance, can learn, there is error if bury the forming dimension of resistance length direction, can bury the forming dimension that hinders Width by adjustment and make the length-width ratio of burying resistance remain unchanged, the resistance of promptly burying resistance remains unchanged.For example, needing etched length-width ratio of burying resistance is 1: 1, and find that through measuring there is error in the forming dimension that buries the resistance length direction that step 101 etches, than ten of original pre-set length long hundred branch, if the not whole forming dimension that buries the resistance Width, then might make the final length-width ratio of burying resistance is 1.1: 1, constant in order to keep burying the resistance length-width ratio, need revise the forming dimension that buries the resistance Width, the forming dimension that buries the resistance Width that makes correction is than ten of the default forming dimension long hundred branch that buries the resistance Width, the length-width ratio of burying resistance like this can remain unchanged, and still is 1: 1.
Step 104: according to the forming dimension etching nickel-phosphorus alloy firm 5 that buries the resistance Width of described correction, what obtain being shaped buries resistance, idiographic flow such as Figure 13 and shown in Figure 14.
There is error in the forming dimension that buries the resistance length direction owing to etching in step 101, and can learn and to revise the forming dimension that buries the resistance Width by step 102 and step 103, and the data of revising also can be calculated, therefore the resistance width mask 5 that buries that will revise in this step covers that to bury resistance regional, (copper-bath of 1% concentration is higher to the reactivity of nickel-phosphorus alloy firm to use the copper-bath of 1% concentration then, reactivity to copper foil layer is not high, but be not limited to the copper-bath of this concentration in actual applications, also be not limited to copper-bath, it is higher to the reactivity of resistive layer selecting the standard of etch process, reactivity to conductor layer is not high) etching nickel-phosphorus alloy firm 2, wash again and bury resistance width mask 5, promptly finally obtain the resistance of burying that is shaped.
In addition, because the thickness of nickel-phosphorus alloy firm is very little, be easy to etchedly in 1% copper-bath, and 1% copper-bath is not obvious to the etch effect of copper foil layer, and the therefore default outer interconnection line of resistance figure that buries does not need to use mask protection.
Need to prove, obtain among Figure 13 bury the resistance figure be one of the embodiment of the invention for example, also different to the shape need that buries the resistance figure as required in the practical application, but the described technical scheme of the basic principle and the embodiment of the invention is similar, repeats no more.
Etch preset is buried resistance figure splicing ear and the non-resistance regional interconnection circuit copper foil layer in addition that buries in the step 101 of present embodiment, obtain burying the forming dimension and the non-resistance regional interconnection circuit that buries of resistance length direction, therefore only need be in step 102 according to the unwanted nickel-phosphorus alloy firm of revising of forming dimension etching that buries the resistance Width, what then can obtain being shaped buries resistance.And the thickness of nickel-phosphorus alloy firm is very little, is generally the sub-micron rank, and the trapezium effect that the etching nickel-phosphorus alloy firm is produced can be ignored, and etched precision is very high.Simultaneously, in the present embodiment, can learn that by measuring etching buries the error of the forming dimension of resistance length direction, according to the resistance computing formula of burying resistance, can bury the forming dimension that hinders Width by adjustment this error is made correction, thereby help to improve the resistance accuracy that buries resistance.
In addition, because the precision of etching nickel-phosphorus alloy firm is very high separately, and the forming dimension that can bury the resistance Width by adjustment buries the error that the forming dimension of resistance length direction occurs to etching and makes correction, therefore the thickness for the etching copper foil layer there is no specific (special) requirements, the easier control of processing technology.
The embodiment of the invention also provides a kind of device of realizing high-precision buried resistance, and as shown in figure 15, this device comprises:
Bury resistance length direction forming dimension acquisition module, be used for etch preset and bury resistance figure splicing ear and the non-resistance regional interconnection circuit conductor layer in addition that buries, obtain burying the forming dimension and the non-resistance regional interconnection circuit that buries of resistance length direction;
Measurement module, the forming dimension that buries the resistance length direction that is used to measure;
Bury resistance Width forming dimension computing module, be used for calculating the forming dimension of revising that buries the resistance Width according to the forming dimension of measuring that buries the resistance length direction;
Bury resistance Width forming dimension acquisition module, be used for according to the forming dimension of revising that buries the resistance Width, the etching resistive layer, what obtain being shaped buries resistance.
Wherein, burying resistance length direction forming dimension acquisition module comprises:
Coated elements is used for coating photoresist at conductor layer;
The mask acquiring unit is used to utilize exposure and developing technique to obtain the default photoresist mask that buries resistance figure splicing ear correspondence burying the resistance zone, at the non-regional photoresist mask that obtains the interconnection line correspondence of resistance that buries;
Conductor layer etching unit is used for the etched conductors layer;
Cleaning unit is used to clean the photoresist mask, obtains burying the forming dimension and the non-resistance regional interconnection circuit that buries of resistance length direction.
Wherein, burying resistance Width forming dimension acquisition module comprises:
Capping unit, the resistance width mask that buries that is used for revising covers and buries the resistance zone;
Conductor layer etching unit is used for the resistive layer beyond the resistance width mask of burying of etching correction, and what obtain being shaped buries resistance.
The described technical scheme of the embodiment of the invention is buried resistance figure splicing ear and the non-resistance regional interconnection circuit copper foil layer in addition that buries by etch preset, obtains burying the forming dimension and the non-resistance regional interconnection circuit that buries of resistance length direction; Measure the forming dimension that buries the resistance length direction again, computing formula according to the resistance of burying resistance, the forming dimension that buries the resistance Width is revised, according to the forming dimension etching nickel-phosphorus alloy firm of revising that buries the resistance Width, the trapezium effect that can partly avoid etching and brought, thereby help to improve the resistance accuracy that buries resistance of final shaping, make and bury the easier control of resistance processing technology.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1. a method that realizes high-precision buried resistance is characterized in that, described method comprises:
Etch preset is buried resistance figure splicing ear and the non-resistance regional interconnection circuit conductor layer in addition that buries, and obtains burying the forming dimension and the non-resistance regional interconnection circuit that buries of resistance length direction;
Measure the described forming dimension that buries the resistance length direction;
The forming dimension that buries the resistance length direction according to described measurement calculates the forming dimension of revising that buries the resistance Width;
According to the forming dimension that buries the resistance Width of described correction, the etching resistive layer, what obtain being shaped buries resistance.
2. the method for realization high-precision buried resistance as claimed in claim 1, it is characterized in that, described etch preset is buried resistance figure splicing ear and the non-resistance regional interconnection circuit conductor layer in addition that buries, and obtains burying the forming dimension and the non-step of burying resistance regional interconnection circuit that hinder length direction and specifically comprises:
Coat photoresist at conductor layer;
Utilize exposure and developing technique to obtain the described default photoresist mask that buries resistance figure splicing ear correspondence burying the resistance zone, at the non-regional photoresist mask that obtains described interconnection line correspondence of resistance that buries;
The etched conductors layer;
Clean described photoresist mask, obtain described forming dimension and the described non-resistance regional interconnection circuit that buries that buries the resistance length direction.
3. the method for realization high-precision buried resistance as claimed in claim 1 is characterized in that, the step that the described forming dimension that buries the resistance length direction according to described measurement calculates the forming dimension of revising that buries the resistance Width is specially:
The forming dimension that buries the resistance length direction that the forming dimension that buries the resistance Width of described correction equals described measurement multiply by square resistance again divided by the resistance of burying resistance.
4. the method for realization high-precision buried resistance as claimed in claim 1 is characterized in that, the described forming dimension that buries the resistance Width according to described correction, and the etching resistive layer, the step of burying resistance that obtains being shaped specifically comprises:
The resistance width mask of revising that buries is covered and buries the resistance zone, the described correction of etching bury resistive layer beyond the resistance width mask, obtain the resistance of burying of described shaping.
5. a device of realizing high-precision buried resistance is characterized in that, described device comprises:
Bury resistance length direction forming dimension acquisition module, be used for etch preset and bury resistance figure splicing ear and the non-resistance regional interconnection circuit conductor layer in addition that buries, obtain burying the forming dimension and the non-resistance regional interconnection circuit that buries of resistance length direction;
Measurement module is used to measure the described forming dimension that buries the resistance length direction that obtains;
Bury resistance Width forming dimension computing module, be used for calculating the forming dimension of revising that buries the resistance Width according to the forming dimension that buries the resistance length direction of described measurement;
Bury resistance Width forming dimension acquisition module, be used for the forming dimension that buries the resistance Width according to described correction, the etching resistive layer, what obtain being shaped buries resistance.
6. the device of realization high-precision buried resistance as claimed in claim 5 is characterized in that, the described resistance length direction forming dimension acquisition module that buries comprises:
Coated elements is used for coating photoresist at conductor layer;
The mask acquiring unit is used to utilize exposure and developing technique to obtain the described default photoresist mask that buries resistance figure splicing ear correspondence burying the resistance zone, at the non-regional photoresist mask that obtains described interconnection line correspondence of resistance that buries:
Conductor layer etching unit is used for the etched conductors layer;
Cleaning unit is used to clean described photoresist mask, obtains described forming dimension and the described non-resistance regional interconnection circuit that buries that buries the resistance length direction.
7. the device of realization high-precision buried resistance as claimed in claim 5 is characterized in that, the described resistance Width forming dimension acquisition module that buries comprises:
Capping unit, the resistance width mask that buries that is used for revising covers and buries the resistance zone;
Conductor layer etching unit is used for burying of the described correction of etching and hinders width mask resistive layer in addition, obtains the resistance of burying of described shaping.
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| CN2008100575624A CN101227800B (en) | 2008-02-03 | 2008-02-03 | Apparatus and method for implementing high-precision buried resistance |
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| CN2008100575624A CN101227800B (en) | 2008-02-03 | 2008-02-03 | Apparatus and method for implementing high-precision buried resistance |
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| CN101227800A true CN101227800A (en) | 2008-07-23 |
| CN101227800B CN101227800B (en) | 2011-05-04 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103068175A (en) * | 2012-11-08 | 2013-04-24 | 东莞生益电子有限公司 | Method of improving buried resistance printed wire board resistance precision |
| CN103338592A (en) * | 2013-06-06 | 2013-10-02 | 苏州市三生电子有限公司 | Buried resistor and manufacture process thereof |
| CN104427762A (en) * | 2013-09-02 | 2015-03-18 | 深圳崇达多层线路板有限公司 | Buried resistance printed board and manufacturing method thereof |
| CN105097593A (en) * | 2015-07-08 | 2015-11-25 | 深圳市盛德金科技有限公司 | Production control method, device and system of thin-film electronic device |
| WO2018233271A1 (en) * | 2017-06-20 | 2018-12-27 | 广州兴森快捷电路科技有限公司 | Printed circuit board and fabrication method therefor |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6232042B1 (en) * | 1998-07-07 | 2001-05-15 | Motorola, Inc. | Method for manufacturing an integral thin-film metal resistor |
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2008
- 2008-02-03 CN CN2008100575624A patent/CN101227800B/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103068175A (en) * | 2012-11-08 | 2013-04-24 | 东莞生益电子有限公司 | Method of improving buried resistance printed wire board resistance precision |
| CN103338592A (en) * | 2013-06-06 | 2013-10-02 | 苏州市三生电子有限公司 | Buried resistor and manufacture process thereof |
| CN103338592B (en) * | 2013-06-06 | 2016-07-06 | 苏州市三生电子有限公司 | A kind of buried resistor and processing technology thereof |
| CN104427762A (en) * | 2013-09-02 | 2015-03-18 | 深圳崇达多层线路板有限公司 | Buried resistance printed board and manufacturing method thereof |
| CN104427762B (en) * | 2013-09-02 | 2017-12-15 | 深圳崇达多层线路板有限公司 | Bury resistance printed board and preparation method thereof |
| CN105097593A (en) * | 2015-07-08 | 2015-11-25 | 深圳市盛德金科技有限公司 | Production control method, device and system of thin-film electronic device |
| CN105097593B (en) * | 2015-07-08 | 2018-06-19 | 深圳市盛德金科技有限公司 | A kind of production control method of thin film electronic device, apparatus and system |
| WO2018233271A1 (en) * | 2017-06-20 | 2018-12-27 | 广州兴森快捷电路科技有限公司 | Printed circuit board and fabrication method therefor |
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Effective date of registration: 20171107 Address after: Metro Songshan Lake high tech Industrial Development Zone, Guangdong Province, Dongguan City Road 523808 No. 2 South Factory (1) project B2 -5 production workshop Patentee after: HUAWEI terminal (Dongguan) Co., Ltd. Address before: 518129 Longgang District, Guangdong, Bantian HUAWEI base B District, building 2, building No. Patentee before: Huawei Device Co., Ltd. |
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Address after: 523808 Southern Factory Building (Phase I) Project B2 Production Plant-5, New Town Avenue, Songshan Lake High-tech Industrial Development Zone, Dongguan City, Guangdong Province Patentee after: Huawei Device Co., Ltd. Address before: 523808 Southern Factory Building (Phase I) Project B2 Production Plant-5, New Town Avenue, Songshan Lake High-tech Industrial Development Zone, Dongguan City, Guangdong Province Patentee before: HUAWEI terminal (Dongguan) Co., Ltd. |