CN104281008A - Exposure image compensation method - Google Patents
Exposure image compensation method Download PDFInfo
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- CN104281008A CN104281008A CN201310273126.1A CN201310273126A CN104281008A CN 104281008 A CN104281008 A CN 104281008A CN 201310273126 A CN201310273126 A CN 201310273126A CN 104281008 A CN104281008 A CN 104281008A
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- exposure image
- conductor layer
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Abstract
A disclosed exposure image compensation method comprises: compensating an original exposure image according to multiple etching factors, and then preparing a patterned photoresist layer according to the compensated exposure image; patterning a conductor layer on a circuit board by combining wet type etching and the patterned photoresist layer, so as to form a conductor line; using a measured linewidth error of the conductor line to represent a result caused by unconsidered etching factors; when the measured linewidth exceeds a preset scope, concluding influence of unconsidered factors on the etching result, calculating an error value, introducing the error value and again calculating out compensating data of all points on the circuit board and corresponding to the conductor layer, and again preparing a patterned photoresist layer and a corresponding conductor line according to the compensating data; and when a measured linewidth is in the preset scope, taking the current compensating data as optimal compensating data.
Description
Technical field
The present invention relates to a kind of circuit board production techniques, and particularly relate to a kind of exposure image compensation method, its can improve circuit board with subtractive process (substractive process) the precision of formation conductor line (conductive circuit).
Background technology
Along with the high development of electronic technology, the circuit precision of circuit board and density more and more higher, the manufacturing technology of circuit board is also constantly promoted.A kind of normal method making conductor line is on circuit boards a subtractive to method, its by Wet-type etching (wet etching) remove conductor layer (such as layers of copper) on circuit board the part that exposes by etching mask (the photoresist oxidant layer be namely patterned through overexposure (exposure) and development (development)), so that conductor layer patterning is formed conductor line.
Wet-type etching is a kind of isotropic etching (isotropic etching), so carrying out in the process of Wet-type etching to conductor layer, etching liquid will carry out longitudinal direction etching and lateral etches to conductor layer simultaneously, and wherein lateral etches can cause so-called undercut phenomenon (undercut) to conductor layer.Therefore, when carrying out patterning conductor layer by Wet-type etching collocation patterning photoresist oxidant layer, both made original circuit image (circuit image) accurately be transferred to patterning photoresist oxidant layer via exposure and development, the undercut phenomenon of Wet-type etching may cause the circuit image be transferred in patterning photoresist oxidant layer accurately cannot be transferred to conductor layer.
In order to improve the precision of exposure, develop the exposure machine of laser direct imaging (Laser Direct Imaging, LDI) at present.The exposure function of laser direct imaging type according to inputted circuit image mobile laser head in photoresist oxidant layer, and produces the wish exposure area of laser beam direct irradiation photoresist oxidant layer by laser head.The exposure machine of current laser direct imaging type can accept the circuit image of digital format, and automatically can produce the mobile route of laser head, to be transferred in photoresist oxidant layer by circuit image by computational scheme image.
Undercut phenomenon in order to avoid Wet-type etching affects the precision of conductor line, and current laser direct imaging type exposure machine more can revise circuit image to compensate according to inputted conductor layer thickness specification and live width specification automatically.Current laser direct imaging type exposure machine more can revise circuit image to compensate according to inputted conductor layer thickness specification and live width specification automatically.
Summary of the invention
The object of the present invention is to provide a kind of exposure image compensation method, be applicable to process for manufacturing circuit board, in order to improve circuit board with subtractive process form the precision of conductor line.
A kind of exposure image compensation method of the present invention, comprise the following steps: that (a) carrys out the offset data of the corresponding each point on circuit boards of calculating conductor layer to compensate original exposure image according to multiple etching factor, wherein those etching factors comprise the one selecting to form from the thickness of the corresponding each point on circuit boards of conductor layer, face time, photoresist layer thickness and line width, circuit density degree, line construction form and contour of track institute group and combine; B () is according to the photoresist oxidant layer exposure image compensated conductor layer on circuit boards being formed patterning; C () carrys out the part that photoresist oxidant layer that etched conductors layer is patterned exposes, with patterning conductor layer by the photoresist oxidant layer of patterning as etching mask; And whether the live width of the conductor layer of (d) survey sheet patterning is within the scope of the live width preset.
When measured live width is not within the scope of the live width preset, an error amount is calculated after the impact conclusion of the factor pair etching result it be not taken into account, recalculate the offset data of the corresponding each point on circuit boards of conductor layer after being brought into by error amount, and repeat step (b)-(d).On the contrary, when measured live width is within the scope of the live width preset, adopt the offset data of offset data as the best of the corresponding each point on circuit boards of current conductor layer.
Based on above-mentioned, in the present invention, first according to multiple etching factor, original exposure image is compensated, then carry out fabricating patterned photoresist oxidant layer according to the exposing patterns that this has compensated.Then, this patterning photoresist oxidant layer is coordinated to carry out patterning conductor layer on circuit boards to form conductor line by Wet-type etching.The linewidth error of measured conductor line represents the result that its etching factor be not taken into account causes.When measured live width exceeds preset range, an error amount is calculated after the impact of the factor pair etching result be not taken into account being concluded, the offset data of the corresponding each point on circuit boards of conductor layer is recalculated after being brought into by error amount, and the conductor line of offset data fabricating patterned photoresist oxidant layer and correspondence again according to this.When measured live width falls into preset range, current offset data is best offset data.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate appended accompanying drawing to be described in detail below.
Accompanying drawing explanation
Fig. 1 is the process flow diagram of the exposure image compensation method of one embodiment of the invention.
Symbol description
S110-S210: step
Embodiment
Exposure image compensation method of the present invention is applicable to improve circuit board with the precision of the circuit produced by subtractive process.In subtractive process, by Wet-type etching by the conductor layer (such as layers of copper) on circuit board the part that exposes by etching mask (such as through the photoresist oxidant layer of overexposure and development) remove, form conductor line with patterning conductor layer.In order to obtain the less conductor layer of thickness, by plating form conductor layer on circuit boards, and can after plating optionally microetch conductor layer surface.
Fig. 1 is the process flow diagram of the exposure image compensation method of one embodiment of the invention.Please refer to Fig. 1, in step s 110, carry out the offset data of the corresponding each point on circuit boards of calculating conductor layer according to multiple etching factor.In the present embodiment, the arithmetic element by exposure machine carrys out calculation compensation data.The definition of compensation here refers to that the pattern boundaries of photoresist oxidant layer exceeds the width size of the pattern boundaries of place conductor layer scheduled circuit, and compensating the pattern boundaries representing greatly photoresist oxidant layer, to exceed the width of the pattern boundaries of conductor layer scheduled circuit large.
These above-mentioned etching factors can comprise the thickness of the corresponding each point on circuit boards of conductor layer, face time (i.e. upper face or lower face), photoresist layer thickness and line width, circuit density degree, line construction form and contour of track etc.
For the etching factor of " thickness of the corresponding each point on circuit boards of conductor layer ", the thickness of the corresponding each point on circuit boards of conductor layer can be measured after conductor layer is formed by plating.Be different from and existingly only compensate for the average thickness of conductor layer, in the present embodiment, contribute to calculating using the thickness of the corresponding each point on circuit boards of conductor layer as etching factor and compensate more accurately, thus improve circuit precision.In the present embodiment, the thickness of conductor layer is larger needs less compensation, in high negative correlation between the etching factor of " thickness of the corresponding each point on circuit boards of conductor layer " and compensation.
For the etching factor of " face time (upper face or lower face) ", when circuit board carries out Wet-type etching in a horizontal manner, upper face at circuit board is produced pond phenomenon by etching liquid, thus etch-rate is slowed down, so according to the upper face of circuit board and the difference of lower face, exposure image needs different compensation.In the present embodiment, for the upper face of circuit board, the corresponding position of exposure image needs less compensation compared to the lower face of circuit board, thus the etching factor in " face time " and between compensating in low negative correlation.
For the etching factor of " photoresist layer thickness ", the speed that the thickness effect due to photoresist oxidant layer etches, so add different compensation according to the thickness size of photoresist oxidant layer.In the present embodiment, for the photoresist oxidant layer that thickness is less, the corresponding position of exposing patterns needs less compensation, so in low positive correlation between the etching factor of " photoresist layer thickness " and compensation.
For the etching factor of " line width ", due to the etching speed that line width impact is local, so add different compensation according to different line width.In the present embodiment, for less line width, the corresponding position of exposing patterns needs larger compensation, so in low negative correlation between the etching factor of " line width " and compensation.
For the etching factor of " circuit density degree ", circuit density degree refers to the evacuation of circuit or intensive degree, so add different compensation according to different circuit density degree.In the present embodiment, for comparatively intensive circuit, the corresponding position of exposing patterns needs less compensation, so in high negative correlation between the etching factor of " circuit density degree " and compensation.
For the etching factor of " line construction form ", line construction form refers to the entity area of circuit, and wherein the entity area of circuit is such as conducting plane and connection pad etc.In the present embodiment, line construction form refers to that the entity area of circuit is larger needs less compensation, so in low negative correlation between the etching factor of " line construction form " and compensation.
For the etching factor of " conductor layer profile ", conductor layer profile refers to the roughness at the interface between conductor layer and place dielectric layer.In the present embodiment, the compensation that the larger needs of roughness at the interface between conductor layer and place dielectric layer are larger, so the etching factor of " conductor layer profile " and between compensating in high-positive correlation.
In the step s 120, original exposure image is compensated according to calculated offset data.In the present embodiment, the arithmetic element by exposure machine compensates original exposure image according to calculated offset data (as step S110).
In step S130 below, S140 and S150, will illustrate how according to the photoresist oxidant layer exposure image compensated conductor layer on circuit boards being formed patterning.
In step s 130, which, conductor layer on circuit boards forms photoresist oxidant layer.In the present embodiment, the mode forming photoresist oxidant layer can comprise the pressing of photoresist dry film.
In step S140, expose photoresist oxidant layer according to the exposure image compensated (as step S120).In the present embodiment, photoresist oxidant layer is exposed by the exposing unit of exposure machine according to the exposure image compensated.
In step S150, the photoresist oxidant layer exposed of developing, with patterning photoresist oxidant layer, makes the exposure image compensated be transferred to the photoresist oxidant layer of patterning.
In step S160, carry out the part that photoresist oxidant layer that etched conductors layer is patterned exposes, with patterning conductor layer by the photoresist oxidant layer of patterning as etching mask.
In step S190, judge that the live width of the conductor layer (i.e. conductor line) of measured patterning is whether within the scope of default live width.In the present embodiment, after step 160 and before S190, more can comprise step S170 and S180.In step S170, remove the photoresist oxidant layer of patterning, to expose the conductor layer of patterning.In step S180, the live width of the conductor layer (i.e. conductor line) of survey sheet patterning.
In the present embodiment, self-operated measuring unit is adopted to carry out the live width of the conductor layer (i.e. conductor line) of survey sheet patterning.When measured live width is not within the scope of the live width preset, perform step S200, an error amount is calculated after the impact of the factor pair etching result be not taken into account being concluded, recalculate the offset data of the corresponding each point on circuit boards of conductor layer after being brought into by error amount, and repeat step S120 to step S190.On the contrary, when measured live width is within the scope of the live width preset, perform step S210, adopt the offset data of offset data as the best of the corresponding each point on circuit boards of current conductor layer, in order to compensate original exposure image to produce best exposure image.
Carrying out in the process of volume production according to identical process for manufacturing circuit board and identical etching factor, exposure machine can directly adopt the exposure image of the best produced to expose photoresist oxidant layer, and the photoresist oxidant layer that exposed of then developing is with patterning photoresist oxidant layer.Therefore, the photoresist oxidant layer of patterning has best etching pattern, thus improves the circuit precision of the conductor line coordinating the photoresist oxidant layer of patterning to be formed as etching mask by etching.
In sum, in the present invention, first according to multiple etching factor, original exposure image is compensated, then carry out fabricating patterned photoresist oxidant layer according to the exposing patterns that this has compensated.Then, this patterning photoresist oxidant layer is coordinated to carry out patterning conductor layer on circuit boards to form conductor line by Wet-type etching.The linewidth error of measured conductor line represents the result that its etching factor be not taken into account causes.When measured live width exceeds preset range, an error amount is calculated after the impact of the factor pair etching result be not taken into account being concluded, the offset data of the corresponding each point on circuit boards of conductor layer is recalculated after being brought into by error amount, and the conductor line of offset data fabricating patterned photoresist oxidant layer and correspondence again according to this.When measured live width falls into preset range, current offset data is best offset data.
Although disclose the present invention in conjunction with above embodiment; but itself and be not used to limit the present invention; this operator is familiar with in any art; without departing from the spirit and scope of the present invention; a little change and retouching can be done, therefore being as the criterion of should defining with the claim of enclosing of protection scope of the present invention.
Claims (10)
1. an exposure image compensation method, comprises the following steps:
A () carrys out the offset data of the corresponding each point on circuit boards of calculating conductor layer to compensate original exposure image according to multiple etching factor, wherein those etching factors comprise the one selecting to form from the thickness of the corresponding each point on circuit boards of conductor layer, face time, photoresist layer thickness and line width, circuit density degree, line construction form and contour of track institute group and combine;
B () is according to the photoresist oxidant layer exposure image compensated conductor layer on circuit boards being formed patterning;
C () carrys out the part that photoresist oxidant layer that etched conductors layer is patterned exposes, with patterning conductor layer by the photoresist oxidant layer of patterning as etching mask; And
D () judges that the live width of the conductor layer of measured patterning is whether within the scope of the live width preset, when measured live width is not within the scope of the live width preset, an error amount is calculated after the impact of the factor pair etching result be not taken into account being concluded, the offset data of the corresponding each point on circuit boards of conductor layer is recalculated after being brought into by error amount, and repeat step (b)-(d), when measured live width is within the scope of the live width preset, adopt the offset data of offset data as the best of the corresponding each point on circuit boards of current conductor layer.
2. exposure image compensation method as claimed in claim 1, wherein carrys out calculation compensation data by the arithmetic element of exposure machine.
3. exposure image compensation method as claimed in claim 2, wherein compensates original exposure image by the arithmetic element of exposure machine according to calculated offset data.
4. exposure image compensation method as claimed in claim 1, wherein the thickness of the etching factor definition conductor layer of the thickness of the corresponding each point on circuit boards of this conductor layer is larger needs less compensation.
5. exposure image compensation method as claimed in claim 1, wherein the upper face of the etching factor definition circuit plate in this face time needs less compensation compared to the lower face of circuit board.
6. exposure image compensation method as claimed in claim 1, the compensation that wherein the larger needs of thickness of the etching factor definition photoresist oxidant layer of the thickness of this photoresist oxidant layer are larger.
7. exposure image compensation method as claimed in claim 1, the compensation that wherein the larger needs of width of the etching factor definition circuit of this line width are larger.
8. exposure image compensation method as claimed in claim 1, wherein the density of the etching factor definition circuit of this circuit density degree is higher needs less compensation.
9. exposure image compensation method as claimed in claim 1, wherein the entity area of the etching factor definition circuit of this line construction form is larger needs less compensation.
10. exposure image compensation method as claimed in claim 1, wherein the etching factor of this conductor layer profile defines the larger compensation of the larger needs of roughness at the interface between this conductor layer and place dielectric layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310273126.1A CN104281008B (en) | 2013-07-02 | 2013-07-02 | exposure image compensation method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310273126.1A CN104281008B (en) | 2013-07-02 | 2013-07-02 | exposure image compensation method |
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| CN104281008A true CN104281008A (en) | 2015-01-14 |
| CN104281008B CN104281008B (en) | 2016-08-31 |
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| CN201310273126.1A Active CN104281008B (en) | 2013-07-02 | 2013-07-02 | exposure image compensation method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110191596A (en) * | 2019-04-18 | 2019-08-30 | 奥士康精密电路（惠州）有限公司 | A kind of PCB production method of BGA welding roundlet PAD |
| CN114786347A (en) * | 2022-03-02 | 2022-07-22 | 深南电路股份有限公司 | Processing method of circuit board |
| CN115052422A (en) * | 2022-05-16 | 2022-09-13 | 珠海方正科技高密电子有限公司 | Method for establishing circuit board impedance line compensation model, compensation method and device |
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| CN110191596A (en) * | 2019-04-18 | 2019-08-30 | 奥士康精密电路（惠州）有限公司 | A kind of PCB production method of BGA welding roundlet PAD |
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| CN115052422A (en) * | 2022-05-16 | 2022-09-13 | 珠海方正科技高密电子有限公司 | Method for establishing circuit board impedance line compensation model, compensation method and device |
| CN115052422B (en) * | 2022-05-16 | 2024-03-01 | 珠海方正科技高密电子有限公司 | Method for establishing circuit board impedance line compensation model, compensation method and device |
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| CN104281008B (en) | 2016-08-31 |
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