CN101226881A - Method for manufacturing dent source leakage field effect transistor - Google Patents
Method for manufacturing dent source leakage field effect transistor Download PDFInfo
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- CN101226881A CN101226881A CNA2007100006826A CN200710000682A CN101226881A CN 101226881 A CN101226881 A CN 101226881A CN A2007100006826 A CNA2007100006826 A CN A2007100006826A CN 200710000682 A CN200710000682 A CN 200710000682A CN 101226881 A CN101226881 A CN 101226881A
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 230000005669 field effect Effects 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 238000002360 preparation method Methods 0.000 claims description 11
- 239000002210 silicon-based material Substances 0.000 claims description 9
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 3
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 239000000956 alloy Substances 0.000 claims description 2
- 238000000137 annealing Methods 0.000 claims description 2
- 238000002156 mixing Methods 0.000 claims description 2
- 230000002349 favourable effect Effects 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 18
- 229910052710 silicon Inorganic materials 0.000 description 17
- 239000010703 silicon Substances 0.000 description 17
- 230000000694 effects Effects 0.000 description 7
- 230000003071 parasitic effect Effects 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000011031 large-scale manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 239000012190 activator Substances 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
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Abstract
The invention provides a process for preparing transistors of recessed source-drain field effect, belonging to the field of ultra large scale integrated circuit technique (ULSI). The method introduces epitaxial process and employs the method of sacrificial layers, and two 'L' shaped buried oxide structures are introduced in substrates. By employing the process, processing parameter and physical parameter of devices can be well controlled, such as parameters of reverse doping concentration and depth, junction depth, depth of recessed source-drain, thickness of buried oxide layers and the like. The method is quite strong in controllability and compatible with the existing technique, and is favorable for application in mass production.
Description
Technical field
The invention belongs to very large scale integration technology (ULSI) field, relate in particular to a kind of method for preparing dent source leakage field effect transistor.
Background technology
Along with the development of microelectric technique, the characteristic size of device enters deep-submicron (＜0.1um) scope.At this moment, the field-effect transistor of traditional CMOS body silicon technology preparation owing to be subjected to the serious short channel effect and the influence of other ghost effect, is very restricted in application facet.SOI (the silicon on insulator) device of employing SOI silicon substrate preparation is the full-exhaustion SOI device especially, can well suppress short channel effect, obtains less threshold voltage fluctuation and approaching desirable sub-threshold slope; Simultaneously, with element manufacturing at SiO
2On, can reduce parasitic junction capacitance, thereby improve the speed of device.But, adopt the cost of soi wafer very high.Simultaneously, the SOI device can be subjected to the restriction of heat dissipation problem: because the thermal conductivity of oxygen buried layer smaller (only be about silicon materials 0.01), the heat that produces during device work can not in time distribute, cause the accumulation of heat in device, thereby cause the lattice temperature of device to raise, the degeneration of mobility, thus cause such as problems such as drive current decline, working point instabilities, the output result who influences circuit is bad even cause logic error, Here it is so-called self-heating effect.Adopt the field-effect transistor of dent source leakage as shown in Figure 1, the oxidized layer of its source-drain area overwhelming majority medium surrounds, and links to each other by silicon between channel region and the substrate, can avoid above-mentioned problem significantly.The advantage of this structure is: (1) source-drain area helps reducing parasitic junction capacitance on silicon oxide layer, has turn-offed the leakage current path between source-drain area and the substrate zone simultaneously; (2) adopt dent source leakage can reduce the influence that living resistance is omitted in the source, simultaneously than adopting the lifting source drain region to reduce the method for resistance, its parasitic grid source, gate leakage capacitance are also little, also just help the application aspect high frequency; (3) channel region directly links to each other with substrate, and heat can effectively solve the self-heating effect in the soi structure by very fast the distributing of silicon substrate; (4) raceway groove links to each other with substrate, also for follow-up raceway groove engineering provides the aspect, such as adopting channel doping to adjust threshold voltage, adopting reverse doping (retrograde) structure to improve short channel effect inhibition ability etc.; (5) than body silicon structure and soi structure, this structure has better short ditch characteristic; (6) adopt conventional body silicon substrate, the cost cost is low, or the like.
Although said structure has a lot of good performances, in realizing, actual process still has a lot of difficulties.Main challenge is: (1) needs to realize that the leakage of monocrystalline silicon source is to reduce dead resistance; (2) need full dent source leakage district to reduce parasitic capacitance; (3) how to introduce the overwhelming majority that silicon oxide layer surrounds source-drain area, can not introduce stress simultaneously; (4) controllability of technology realization (as accurate control) or the like to junction depth, lifting source leakage height etc.At present, adopt prior preparation method not address these problems fully.
Summary of the invention
The purpose of this invention is to provide a kind of method that on body silicon silicon chip, prepares above-mentioned dent source leakage field effect transistor, this method can overcome existing technical problem, leak in the source of realizing full depression, and guarantee that source-drain area is a mono-crystalline structures, and, help being applied in the large-scale production with the existing processes compatibility.
Above-mentioned purpose of the present invention is achieved by the following technical solutions:
A kind of preparation method of dent source leakage field effect transistor, its step comprises:
(1) adopt body silicon silicon chip as substrate, photoetching and etching obtain the monocrystalline silicon platform, and it highly is H
1
(2) epitaxial growth one sacrifice layer and a single crystal silicon material layer successively on substrate, its thickness is respectively H
2And H
3, and H
2+ H
3＞H
1
(3) adopt the upper surface planarization of chemico-mechanical polishing, and etching exposes the upper surface of monocrystalline silicon platform with structure;
(4) epitaxial growth one deck monocrystalline silicon layer again, its thickness is t
Si, this layer thickness will determine the junction depth in the field-effect transistor;
(5) protect the active area single-crystal surface after, form deep trouth in place perforate and etching, expose the sacrifice layer in the structure, sacrifice layer is fallen in the wet method selective etching, forms the cavity;
(6) in cavity and deep trouth, fill up silica material, and adopt chemico-mechanical polishing to make it planarization, form an oxide layer of surrounding source-drain area;
(7) ensuing technology and conventional single grid technique are identical, define grid region, source-drain area injection, annealing, silication, deposited oxide layer, etching fairlead, alloy, passivation, electrode successively and draw.
In step 1, the injection of can mixing before etching single crystal silicon platform forms high-doped zone.
In step 2, sacrifice layer can adopt germanium silicon material, its thickness H
2Be less than the thickness H of monocrystalline silicon platform
1
Monocrystalline silicon platform height H
1Scope can be between 10 nanometer to 200 nanometers.
Sacrificial layer thickness H
2Scope can be between 10 nanometer to 100 nanometers.
Single crystal silicon material layer H
3The scope of thickness can be between 10 nanometer to 100 nanometers.
Single crystal silicon material layer T
SiThe scope of thickness can be between 1 nanometer to 50 nanometer.
Technique effect of the present invention and advantage:
Adopt said method can realize dent source leakage field effect transistor shown in Figure 1.The present invention compares with traditional single grid technique, in the optimizing process of incipient stage to substrate zone, the degree of depth of device technology parameter and physical parameter such as the reverse doping content and the degree of depth, junction depth, dent source leakage, the parameters such as thickness of oxygen buried layer can both better controlled, and controllability is very strong.This method can realize the source leakage of full depression, and guarantees that source-drain area is a mono-crystalline structures; Simultaneously, this method can be well to being optimized of the dent source leakage field effect transistor that will realize, help obtaining optimum device performance; The overwhelming majority of this implementation method all with the existing processes compatibility, help being applied in the large-scale production.
Description of drawings
Below in conjunction with accompanying drawing, the present invention is made detailed description.
Fig. 1 is the structural representation of dent source leakage field effect transistor.
Fig. 2 realizes the process flow diagram of dent source leakage field effect transistor.Wherein:
Fig. 2-a etch silicon platform; Fig. 2-b epitaxy single-crystal germanium silicon layer; Fig. 2-c epitaxy single-crystal silicon layer; Fig. 2-d planarization multilayer single crystalline layer; Fig. 2-e extension second layer monocrystalline silicon; Fig. 2-f protects the district of having chance with, and the place deep etching exposes and buries the germanium silicon layer at the old end; Fig. 2-g selective etching germanium silicon layer fills silica and planarization in the deep trouth; Fig. 2-h forms gate medium, the deposit grid material, and low-doped injection is leaked in definition grid region, source; Fig. 2-i forms oxide layer side wall, and source-drain area injects.
Among the figure, 1-body silicon substrate; The 2-sacrifice layer; The epitaxially grown monocrystalline silicon of 3-; 4-is the monocrystalline silicon of extension for the second time; The 5-hard mask layer; The 6-silica; The 7-gate medium; The 8-grid material; Light doping section is leaked in the 9-source; The 10-monox lateral wall; Heavily doped region is leaked in the 11-source; The 12-deep trouth.
Embodiment
Below we will introduce the realization flow that adopts the present invention to prepare dent source leakage field effect transistor in detail.
(1) cleans the body silicon chip;
(2) the hard mask of deposit, silicon chip surface mix and inject the heavily doped region that forms reverse doping; Remove hard mask again;
(3) deposit photoresist, adopting the domain of grid line bar is mask, lithographic definition silicon platform, dry etching obtain highly being H
1The silicon platform, remove photoresist, obtain structure, H as Fig. 2-a
1Number range can be between 10 nanometer to 200 nanometers;
(4) clean, go natural oxidizing layer, at silicon face epitaxial growth Ge-Si (GeSi) material, epitaxial thickness is H
2, H
2＜H
1As Fig. 2-b, the number range of H2 can be between 10 nanometer to 100 nanometers;
(5) clean, go natural oxidizing layer, epitaxial growth monocrystalline silicon (Si) material on the GeSi material, epitaxial thickness is H
3Require H
3+ H
2＞H
1, and make the surperficial extreme lower position of the superiors' silicon also can be higher than the silicon platform; As Fig. 2-c, H
3The scope of thickness can be between 10 nanometer to 100 nanometers;
(6) chemico-mechanical polishing (CMP), planarization single crystal Si layer and GeSi layer form single-crystal surface smooth shown in Fig. 2-d;
(7) clean, go natural oxidizing layer, at silicon face epitaxial growth monocrystalline silicon (Si) material, epitaxial thickness is T again
Si, this thickness has determined that basically source-and-drain junction is dark; As Fig. 2-e, T
SiThe scope of thickness can be between 1 nanometer to 50 nanometer;
(8) silicon chip surface deposit SiO successively
2/ Si
3N
4Layer is as hard mask, photoetching active area; The place deep etching, promptly hard mask of etching and Si/GeSi district successively expose " L " the type GeSi layer that buries; As Fig. 2-f;
(9) selective etching GeSi material again forms the cavity; Fill the SiO2 material to cavity and deep trouth are filled up fully; CMP forms STI to be isolated; As Fig. 2-g;
(10) remove hard mask layer;
(11) oxidation forms grid oxygen, and raceway groove injects adjusts threshold voltage;
(12) deposit grid material, as polysilicon, and heavy doping, the lithographic definition grid are long again;
(13) the shallow injection of source-drain area forms shallow doped region, as Fig. 2-h;
(14) low-pressure chemical vapor phase deposition (LPCVD) SiO
2Material and etching form side wall;
(15) source-drain area heavy doping; As Fig. 2-i;
(16) rapid thermal annealing activator impurity;
(17) depositing metal forms silicided source drain region and grid region;
(18) deposited oxide layer, lithography fair lead
(19) depositing metal, the photoetching lead-in wire
(20) alloying;
(21) deposit passivation layer
(22) perforate forms electrode.
Claims (7)
1. the preparation method of a dent source leakage field effect transistor, its step comprises:
(1) adopt body silicon silicon chip as substrate, photoetching and etching obtain the monocrystalline silicon platform, and it highly is H
1
(2) epitaxial growth one sacrifice layer and a single crystal silicon material layer successively on substrate, its thickness is respectively H
2And H
3, and H
2+ H
3＞H
1
(3) adopt the upper surface planarization of chemico-mechanical polishing, and etching exposes the upper surface of monocrystalline silicon platform with structure;
(4) epitaxial growth one deck monocrystalline silicon layer again, its thickness is T
Si, this layer thickness will determine the junction depth in the field-effect transistor;
(5) protect the active area single-crystal surface after, form deep trouth in place perforate and etching, expose the sacrifice layer in the structure, sacrifice layer is fallen in the wet method selective etching, forms the cavity;
(6) in cavity and deep trouth, fill up silica material, and adopt chemico-mechanical polishing to make it planarization, form an oxide layer of surrounding source-drain area;
(7) ensuing technology and conventional single grid technique are identical, define grid region, source-drain area injection, annealing, silication, deposited oxide layer, etching fairlead, alloy, passivation, electrode successively and draw.
2. the preparation method of dent source leakage field effect transistor as claimed in claim 1 is characterized in that: in step 1, the injection of mixing before etching single crystal silicon platform forms high-doped zone.
3. the preparation method of dent source leakage field effect transistor as claimed in claim 1 is characterized in that: in step 2, sacrifice layer adopts germanium silicon material, its thickness H
2Be less than the thickness H of monocrystalline silicon platform
1
4. the preparation method of dent source leakage field effect transistor as claimed in claim 1 or 2 is characterized in that: monocrystalline silicon platform height H
1Scope be between 10 nanometer to 200 nanometers.
5. as the preparation method of claim 1 or 3 described dent source leakage field effect transistors, it is characterized in that: sacrificial layer thickness H
2Scope be between 10 nanometer to 100 nanometers.
6. the preparation method of dent source leakage field effect transistor as claimed in claim 1 is characterized in that: single crystal silicon material layer H
3The scope of thickness is between 10 nanometer to 100 nanometers.
7. the preparation method of dent source leakage field effect transistor as claimed in claim 1 is characterized in that: single crystal silicon material layer T
SiThe scope of thickness is between 1 nanometer to 50 nanometer.
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|---|---|---|---|
| CN2007100006826A CN101226881B (en) | 2007-01-16 | 2007-01-16 | Method for manufacturing dent source leakage field effect transistor |
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|---|---|---|---|
| CN2007100006826A CN101226881B (en) | 2007-01-16 | 2007-01-16 | Method for manufacturing dent source leakage field effect transistor |
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|---|---|
| CN101226881A true CN101226881A (en) | 2008-07-23 |
| CN101226881B CN101226881B (en) | 2010-09-15 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102856207A (en) * | 2011-06-30 | 2013-01-02 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN101673673B (en) * | 2009-09-22 | 2013-02-27 | 上海宏力半导体制造有限公司 | Method for forming epitaxial wafer and epitaxial wafer formed by using same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102842493A (en) * | 2011-06-20 | 2012-12-26 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1182585C (en) * | 2003-05-16 | 2004-12-29 | 北京大学 | Field effect transistor adapted for extra-dup submicrometer field and preparation process thereof |
| US6808994B1 (en) * | 2003-06-17 | 2004-10-26 | Micron Technology, Inc. | Transistor structures and processes for forming same |
| CN1303656C (en) * | 2004-06-18 | 2007-03-07 | 北京大学 | A method for preparing quasi SOI field effect transistor device |
| CN1314089C (en) * | 2004-12-21 | 2007-05-02 | 北京大学 | Method for preparing field effect transistor |
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2007
- 2007-01-16 CN CN2007100006826A patent/CN101226881B/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101673673B (en) * | 2009-09-22 | 2013-02-27 | 上海宏力半导体制造有限公司 | Method for forming epitaxial wafer and epitaxial wafer formed by using same |
| CN102856207A (en) * | 2011-06-30 | 2013-01-02 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN102856207B (en) * | 2011-06-30 | 2015-02-18 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
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