CN114121677B - Channel manufacturing process optimization method of FDSOI device - Google Patents
Channel manufacturing process optimization method of FDSOI device Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Abstract
The invention discloses a channel manufacturing process optimization method of an FDSOI device, which can thin a channel to meet the requirements of shortening the length of a grid electrode and controlling a good short channel effect, and can avoid the problems of increased resistance value of a source electrode and a drain electrode, epitaxial growth source electrode and drain electrode defects and the like caused by thinning the channel, and the channel manufacturing process optimization method comprises the following steps: growing a substrate on a wafer, and sequentially preparing an isolation groove, a channel layer, a gate layer and a source drain region on the substrate; selectively etching the gate layer to expose the channel layer below the gate layer; selectively oxidizing the exposed channel layer to obtain first channel region silicon oxide, wherein the thickness of the first channel region silicon oxide is a first preset thickness; etching to remove the silicon oxide in the first channel region to obtain a second etching groove; and oxidizing and growing second channel region silicon oxide in the second etching groove, wherein the thickness of the second channel region silicon oxide is a second preset thickness.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a channel manufacturing process optimization method of an FDSOI device.
Background
The channel refers to the pipe-shaped atomic structure along the main crystal axis direction in the single crystal material, the channel effect exists in the ion injection in the single crystal material, and when the channel length of the metal oxide semiconductor field effect transistor is reduced to a few nanometers, a series of short channel effects such as threshold reduction, leakage induced barrier reduction, carrier surface scattering, velocity saturation, ionization, hot electron effect and the like occur in the transistor.
In the manufacturing process of a semiconductor device, along with the shortening of the gate length, in order to obtain good short channel effect control, a channel of a fully depleted SOI (i.e., FDSOI device) needs to be thinned, a currently common channel thinning mode is to thin the whole channel layer, and although the process of the whole thinning mode is simple, the following problems are also brought along with the gradual thinning of the whole channel: (1) the resistance value of a source electrode and a drain electrode in the device is increased, so that the performance of the device is degraded; (2) the thickness of the channel layer used for the epitaxial growth source drain region is not consistent or not enough, and the epitaxial growth window is reduced, so that the defect of incomplete growth or poor consistency exists in the epitaxial growth source drain region, and the performance of the device is further reduced; (3) the difficulty of the channel manufacturing process is increased, and the thickness of the channel needs to be optimized by inputting more etching materials and process steps, so that the input cost is increased. These limit further reduction in gate length and chip area scaling.
Disclosure of Invention
Aiming at the problems that the whole channel layer is thinned in the prior art, the process difficulty is high, and the problems of shortened grid length and good short channel effect control effect are caused due to the fact that the grid resistance value is increased and the source and drain defects are grown epitaxially, so that the performance of a device is degraded.
In order to achieve the purpose, the invention adopts the following technical scheme:
a channel manufacturing process optimization method of an FDSOI device comprises a wafer substrate, wherein an oxygen buried layer, a bulk silicon layer, a channel layer, a grid layer and a source drain region are distributed on the wafer substrate, the oxygen buried layer and the bulk silicon layer are sequentially distributed from bottom to top, the channel layer is positioned in the middle of the bulk silicon layer, the grid layer is positioned in the middle of the top end of the channel layer, and the source drain region is positioned above the channel layer on two sides of the grid layer; it is characterized in that the preparation method is characterized in that,
the optimization method of the channel manufacturing process comprises the following steps: s1, growing a substrate on the wafer, and sequentially preparing a buried oxide layer, a silicon layer, a channel layer and a source drain region on the substrate;
s2, selectively etching the grid layer to expose the channel layer below the grid layer;
s3, selectively oxidizing the exposed channel layer to obtain first channel region silicon oxide, wherein the thickness of the first channel region silicon oxide is a first preset thickness;
s4, etching to remove the first channel region silicon oxide to obtain a second etching groove;
and S5, oxidizing and growing second channel region silicon oxide in the second etching groove, wherein the second channel region silicon oxide covers the inner end face of the second etching groove, and the thickness of the second channel region silicon oxide is a second preset thickness.
It is further characterized in that it comprises,
in step S1, the specific steps of sequentially preparing the buried oxide layer, the bulk silicon layer, the channel layer, the gate layer, and the source/drain regions on the substrate include: s11, manufacturing a buried oxide layer and a bulk silicon layer on the substrate, wherein the thickness of the bulk silicon layer is 10 nm-50 nm;
s12, performing photo-etching on the bulk silicon layer to form the channel layer and isolation grooves on two sides of the channel layer;
s13, manufacturing the grid layer above the channel layer;
s14, epitaxially growing a source and drain region and injecting ions into the source and drain region;
s15, depositing an etching stop layer and an interlayer dielectric layer (ILD) on the outer surfaces of the source drain region, the grid layer and the isolation groove in sequence;
s16, sequentially grinding the interlayer dielectric layer and the etching stop layer by adopting a chemical mechanical grinding process to expose the top end of the gate layer;
the gate layer comprises a side wall, a silicon oxide gate dielectric and a polysilicon gate layer, wherein the silicon oxide gate dielectric is positioned in the side wall, and the silicon oxide gate dielectric is positioned below the polysilicon gate layer;
in step S13, when the gate layer is fabricated, the method includes the following steps: s131, growing a silicon oxide gate medium; s132, depositing a polysilicon gate layer on the upper surface of the silicon oxide gate medium; s133, etching the polysilicon gate layer and the silicon oxide gate medium by adopting a photoetching process; s134, depositing dielectric layers (the dielectric layers are stacked of one or more of silicon oxide, silicon nitride and silicon carbide nitride) on the surfaces of the etched silicon oxide gate dielectric layer, the polysilicon gate electrode layer and the mask layer; s135, etching the dielectric layer by adopting an anisotropic etching method to obtain a side wall;
in step S2, selectively etching the gate layer, the specific steps include: sequentially etching the polysilicon gate layer and the silicon oxide gate medium to expose the channel layer below the polysilicon gate layer and the silicon oxide gate medium, and obtaining a first etching groove;
in step S3, the first channel region silicon oxide is located below the first etching trench;
the first predetermined thickness is 1 nm-40 nm;
the second predetermined thickness is 0.5 nm-2 nm, and preferably 1 nm.
A metal gate manufacturing method is characterized by comprising the steps of S1-S5, and further comprising the following steps of: s6, depositing a high-dielectric-constant gate dielectric (high-K gate dielectric) in the second etching groove, wherein the high-dielectric-constant gate dielectric covers the inner end faces of the second etching groove and the first etching groove;
s7, depositing a metal gate dielectric into the second etching groove, and covering the metal gate dielectric on the surface of the high-dielectric-constant gate dielectric to obtain a metal gate.
By adopting the structure of the invention, the following beneficial effects can be achieved: in the channel manufacturing process optimization method of the FDSOI device, the following steps are adopted in sequence: the middle part of the channel layer is thinned by the way of selectively oxidizing the exposed channel layer to obtain the first channel region silicon oxide, etching to remove the first channel region silicon oxide to obtain the second etching groove and oxidizing and growing the second channel region silicon oxide in the second etching groove, so that the channel thinning is realized, and the requirements of shortening the length of a grid electrode and good short channel effect control are met. The channel layer thinning area is a channel layer below the grid layer, and the channel layers on two sides for growing the source and drain regions are not thinned, so that the channel with enough thickness is ensured to be used for growing the source and drain regions, the problems of source and drain resistance value increase, epitaxial growth source and drain defects and the like caused by channel thinning are avoided, and the performance degradation of the device is prevented.
Drawings
FIG. 1 is a flow chart of a method for optimizing a channel fabrication process according to the present invention;
FIG. 2 is a schematic view of a structure of a buried oxide layer, an isolation trench, a channel layer, and a gate layer distributed on a substrate;
FIG. 3 is a schematic view of a structure of a substrate with a buried oxide layer, an isolation trench, a channel layer, a gate layer, and a source/drain region;
FIG. 4 is a schematic view of a front view structure formed by sequentially depositing an etching stop layer and an interlayer dielectric layer on the outer surfaces of a source/drain region, a gate layer and an isolation trench;
FIG. 5 is a schematic view of a polysilicon gate layer and a silicon oxide gate after etching;
fig. 6 is a schematic structural view of a front view after a first channel region is obtained by selectively oxidizing the exposed channel layer;
FIG. 7 is a schematic structural diagram of a front view after etching the first channel region;
fig. 8 is a schematic structural diagram of a front view after a second channel region of silicon oxide is grown by oxidation and a high-k gate dielectric is deposited.
Detailed Description
The following provides different embodiments or examples for implementing different configurations of the present invention. To simplify the disclosure of the present invention, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
Referring to fig. 1 and 2, the FDSOI device comprises a wafer substrate 1, wherein an oxygen buried layer 2, an isolation groove 3, a channel layer 4, a gate layer 5 and a source drain region 6 are distributed on the substrate 1, the oxygen buried layer 2 and the isolation groove 3 are sequentially distributed from bottom to top, the channel layer 4 is positioned in the middle of the isolation groove 3, the gate layer 5 is positioned in the middle of the top end of the channel layer 4, and the source drain region 6 is positioned above the channel layer 4 on two sides of the gate layer 5.
The channel manufacturing process optimization method comprises the following steps: s1, growing a substrate on the wafer or selecting an SOI wafer with thicker bulk silicon thickness and thickness of 10 nm-50 nm, sequentially preparing an isolation groove, a channel layer, a gate layer and a source drain region on the substrate, wherein the specific preparation steps of the isolation groove, the channel layer, the gate layer and the source drain region comprise: s11, manufacturing an oxygen buried layer and a bulk silicon layer on the substrate, wherein the thickness of the bulk silicon layer is 10 nm-50 nm;
s12, photoetching, namely photoetching and etching the bulk silicon layer to form a channel layer, wherein the thickness of the channel layer is 10 nm-50 nm, and preferably 20nm in the embodiment;
s13, manufacturing a gate layer above the channel layer, wherein the gate layer comprises a side wall 51, a silicon oxide gate dielectric 52 positioned in the side wall 51 and a polysilicon gate layer 53, and the silicon oxide gate dielectric 52 is positioned below the polysilicon gate layer 53; the manufacturing steps of the gate layer comprise: s131, growing a silicon oxide gate medium; s132, depositing a polysilicon gate layer on the upper surface of the silicon oxide gate medium; s133, etching the polysilicon gate layer and the silicon oxide gate dielectric by adopting a photoetching process to form a gate dielectric and a polysilicon gate electrode; s134, depositing a dielectric layer 54 on the surfaces of the etched silicon oxide gate dielectric layer and the etched polysilicon gate layer, wherein the dielectric layer is a laminated structure of at least one or more of silicon oxide, silicon nitride and silicon carbonitride; s135, etching the dielectric layer by adopting an anisotropic etching method to obtain a side wall;
s14, respectively epitaxially growing raised source and drain regions on two sides of the gate layer by adopting a selective epitaxial growth process, and doping the source and drain regions, wherein the PMOS doping elements comprise boron (B) and the like, and the NMOS doping elements comprise phosphorus (P), arsenic (As) and the like, As shown in figure 3;
s15, sequentially depositing an etching stop layer 61 and an interlayer dielectric layer (ILD) 62 on the outer surfaces of the source drain region, the gate layer and the isolation groove, as shown in FIG. 4;
and S16, sequentially grinding the interlayer dielectric layer and the etching stop layer by adopting a chemical mechanical grinding process to expose the top end of the gate layer.
S2, selectively etching the grid layer to expose the channel layer below the grid layer, the specific steps include: sequentially etching the polysilicon gate layer and the silicon oxide gate medium to expose the channel layer below the polysilicon gate layer and the silicon oxide gate medium and obtain a first etched groove, as shown in fig. 5;
s3, selectively oxidizing the exposed channel layer to obtain a first channel region silicon oxide, where the first channel region silicon oxide is located below the first etching groove 71, and the first channel region silicon oxide has a first predetermined thickness of 1nm to 40nm, preferably 10nm in this embodiment, as shown in fig. 6;
s4, etching to remove the first channel region silicon oxide 81 and obtain a second etching groove 72, as shown in FIG. 7;
in steps S3 and S4, the channel layer to be etched is oxidized, and then a suitable etching liquid or etching gas is selected to etch the oxidized portion, where the etching liquid or etching gas is a gas or a solution containing fluorine (F), in this embodiment, a DHF solution is preferred.
S5, growing a second channel region silicon oxide 82 in the second etching groove 72 by oxidation, as shown in fig. 8, where the second channel region silicon oxide covers the inner end surface of the second etching groove 72, the second channel region silicon oxide has a second predetermined thickness, and the second predetermined thickness is smaller than the first predetermined thickness, where the second predetermined thickness is 0.5nm to 2nm in the present application, and is preferably 1nm in this embodiment; and the second predetermined thickness is less than the maximum thickness of the channel layer;
the channel manufacturing process optimization method is applied to manufacturing of metal gates of FDSOI devices, and comprises the steps of S1-S5, and the method further comprises the following steps: s6, growing a high-dielectric-constant gate dielectric 9 in the second etching groove, wherein the high-dielectric-constant gate dielectric 9 covers the inner end faces of the second etching groove 71 and the first etching groove 72, as shown in FIG. 8;
and S7, depositing a metal gate dielectric into the second etching groove, and covering the metal gate dielectric on the surface of the high-dielectric-constant gate dielectric to obtain the metal gate.
When the FDSOI device with the advanced node with the thickness of the channel layer being thicker (the thickness of the channel layer is about 10 nm-50 nm) and less than 22nm is prepared, the thickness of the channel layer is thinned by adopting the optimization method of the channel manufacturing process. According to the optimization method for the channel manufacturing process, the selective thinning of the channel region of the FDSOI device is realized by sequentially oxidizing and etching the partial region of the channel layer, the thinned region is the channel region below the gate layer, the channel layers on two sides of the gate layer, which are used for growing the source and drain regions, are not thinned, the fact that monocrystalline silicon with enough thickness is used for growing the source and drain regions is ensured, the process window and manufacturability are improved, the problems that the resistance value of the source and drain is increased, the defects of the epitaxial growth source and drain and the like caused by the thinning of the channel are avoided, other processes are not needed to be adopted for optimizing the source and drain regions in the follow-up process, the process is simplified, and meanwhile, the performance degradation of the device is prevented. After the polysilicon gate layer and the silicon oxide gate medium are removed, the channel layer is selectively oxidized, the self-alignment purpose is achieved, effective removal of silicon oxide in the first channel region is facilitated, thinning precision of the channel layer is improved, balance between SCE control (namely electrical performance control) and device driving capability is well considered, great advantages are achieved at advanced nodes of 22nm and below, in addition, compared with a mode of integral thinning of the channel layer, the manufacturing process of the whole FDSOI device is optimized by the mode of selective thinning, and manufacturing cost of the FDSOI device is saved.
The above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiments. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.
Claims (4)
1. A channel manufacturing process optimization method of an FDSOI device comprises a wafer substrate, wherein a buried oxide layer, an isolation groove, a channel layer, a grid layer and a source drain region are distributed on the wafer substrate, the buried oxide layer and the isolation groove are sequentially distributed from bottom to top, the channel layer is positioned in the middle of the isolation groove, the grid layer is positioned in the middle of the top end of the channel layer, and the source drain region is positioned above the channel layer on two sides of the grid layer; it is characterized in that the preparation method is characterized in that,
the channel manufacturing process optimization method comprises the following steps: s1, growing a substrate on the wafer, and sequentially preparing an isolation groove, a channel layer, a grid layer and a source-drain region on the substrate, wherein the method specifically comprises the following steps: s11, manufacturing a buried oxide layer and a bulk silicon layer on the substrate, wherein the thickness of the bulk silicon layer is 10 nm-50 nm;
s12, carrying out photoetching on the bulk silicon layer to form the channel layer and isolation grooves on two sides of the channel layer;
s13, manufacturing the grid layer above the channel layer; when the grid layer is manufactured, the method specifically comprises the following steps: s131, growing a silicon oxide gate medium; s132, depositing polycrystalline silicon on the upper surface of the silicon oxide gate dielectric; s133, etching the polysilicon and the silicon oxide gate dielectric by adopting a photoetching process to form a gate dielectric and a polysilicon gate electrode; s134, depositing dielectric layers on the surfaces of the etched silicon oxide gate dielectric and the etched polysilicon gate electrode; s135, etching the dielectric layer by adopting an anisotropic etching method to obtain a side wall;
s14, epitaxially growing a source and drain region and injecting ions into the source and drain region;
s15, depositing an etching stop layer and an interlayer dielectric layer on the outer surfaces of the source drain region, the gate layer and the isolation groove in sequence;
s16, sequentially grinding the interlayer dielectric layer and the etching stop layer by adopting a chemical mechanical grinding process to expose the top end of the gate layer;
s2, selectively etching the grid layer to expose the channel layer below the grid layer;
s3, selectively oxidizing the exposed channel layer to obtain first channel region silicon oxide, wherein the thickness of the first channel region silicon oxide is a first preset thickness, and the first preset thickness is 1 nm-40 nm;
s4, etching to remove the silicon oxide in the first channel region to obtain a second etching groove;
s5, oxidizing and growing second channel region silicon oxide in the second etching groove, wherein the second channel region silicon oxide covers the inner end face of the second etching groove, and the thickness of the second channel region silicon oxide is a second preset thickness;
the method for optimizing the channel manufacturing process of the FDSOI device is used for manufacturing the metal gate, and further comprises the following steps: s6, depositing a high-dielectric-constant gate dielectric in the second etching groove, wherein the high-dielectric-constant gate dielectric covers the inner end faces of the second etching groove and the first etching groove, and is located on the upper surface of the second channel region silicon oxide;
and S7, depositing a metal gate electrode in the second etching groove, and covering the metal gate electrode on the surface of the high-dielectric-constant gate dielectric to obtain a metal gate.
2. The method as claimed in claim 1, wherein the gate layer comprises a sidewall, a silicon oxide gate dielectric within the sidewall, and a polysilicon gate layer, and the silicon oxide gate dielectric is located below the polysilicon gate layer.
3. The method as claimed in claim 2, wherein in step S2, the gate layer is selectively etched, and the method comprises the following steps: and sequentially etching the polysilicon gate electrode and the silicon oxide gate medium to expose the channel layer below the polysilicon gate electrode and the silicon oxide gate medium, thereby obtaining a first etching groove.
4. The method as claimed in claim 3, wherein the second predetermined thickness is 0.5nm to 2 nm.
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| US5814544A (en) * | 1994-07-14 | 1998-09-29 | Vlsi Technology, Inc. | Forming a MOS transistor with a recessed channel |
| CN102117750A (en) * | 2009-12-30 | 2011-07-06 | 中国科学院微电子研究所 | Metal-oxide-semiconductor field effect transistor (MOSFET) structure and manufacturing method thereof |
| CN102263132A (en) * | 2010-05-26 | 2011-11-30 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN106601617A (en) * | 2015-10-16 | 2017-04-26 | 中国科学院微电子研究所 | Manufacture method of semiconductor device |
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| US6660598B2 (en) * | 2002-02-26 | 2003-12-09 | International Business Machines Corporation | Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5814544A (en) * | 1994-07-14 | 1998-09-29 | Vlsi Technology, Inc. | Forming a MOS transistor with a recessed channel |
| CN102117750A (en) * | 2009-12-30 | 2011-07-06 | 中国科学院微电子研究所 | Metal-oxide-semiconductor field effect transistor (MOSFET) structure and manufacturing method thereof |
| CN102263132A (en) * | 2010-05-26 | 2011-11-30 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN106601617A (en) * | 2015-10-16 | 2017-04-26 | 中国科学院微电子研究所 | Manufacture method of semiconductor device |
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