CN1182585C - Field effect transistor adapted for extra-dup submicrometer field and preparation process thereof - Google Patents
Field effect transistor adapted for extra-dup submicrometer field and preparation process thereof Download PDFInfo
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- CN1182585C CN1182585C CNB031310443A CN03131044A CN1182585C CN 1182585 C CN1182585 C CN 1182585C CN B031310443 A CNB031310443 A CN B031310443A CN 03131044 A CN03131044 A CN 03131044A CN 1182585 C CN1182585 C CN 1182585C
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Abstract
The present invention provides a field effect transistor suitable for an extra-deep submicron field and a preparation method thereof. The field effect transistor comprises a source drain, a grid medium, a grid electrode, a channel and a substrate, wherein a first medium isolating layer in a direction perpendicular to the channel is arranged between the source drain and the substrate, and the connecting part of the source drain and the channel is arranged between the top end of the first medium isolating layer and the channel surface; a second medium isolating layer in a direction parallel to the channel is arranged between the bottom of the source drain and the substrate, and the second medium layer and the first medium isolating layer are connected into an 'L' shape. The preparation of the field effect transistor firstly uses selective epitaxial technology for preparing the first medium isolating layer, and technology for forming a concealed hollow layer by the combination injection of hydrogen and helium is used for preparing the second medium isolating layer. The field effect transistor of the present invention can use a structure that the source drain is wrapped by the medium isolating layer for controlling short channel effect.
Description
Technical field
The structure and manufacture method technical field, the especially characteristic size that the invention belongs to the field-effect transistor (Metal-Oxide-Silicon Field Effect Transistor) in the cmos vlsi (ULSI) are the field-effect transistor structure and the manufacture method thereof of the following scope of 100 nanometers.
Background technology
Along with the cmos vlsi technology enters inferior 0.1 micron field, serious short-channel effect (short channel effect) appears in the field-effect transistor in the circuit, showing as threshold voltage (threshold voltage) reduces with channel length and descends, threshold voltage increases with drain terminal voltage and descends, and the source is leaked under direct break-through (punch-through) or the OFF state source and sewed leakage current (off-state drain leakage current) and increase.Short-channel effect will cause field-effect transistor completely or partially can not work, thereby cause circuit malfunction.Therefore controlling short-channel effect is most important problem in the present cmos vlsi technical field.
At present, in order to control short-channel effect, the general employing improved the tagma doping content, introduces the pocket structure at channel region, and light dope expansion area methods such as (light doped source/drain extension) is leaked in the increase source.In the soi structure field-effect transistor, can also adopt ultra-thin body (ultra thin body) design to suppress short-channel effect.
Improve the channel doping level and be equal to the raising threshold voltage, because therefore subthreshold electric current and threshold voltage exponentially inverse relation will reduce along with the increase of mixing.But the electric current that field-effect transistor is operated under the opening (on state) has reduced too, and the ability of overdriving (over-driving capability) reduces.And,, heavy doping cause circuit to become unreliable owing to will causing the threshold fluctuations phenomenon along with raceway groove becomes shorter (such as near 10 nanometers).
Lightly-doped source leak that the expansion area can reduce that the source is leaked and the tagma between electric charge share (charge share), reach the purpose that reduces short-channel effect, but the resistance of light doping section is bigger, will make characteristic variation under the big current work state.
Introduce the doping content that the pocket structure can increase raceway groove equally at channel region, ON state current therefore also can occur and descend phenomenons such as threshold fluctuations.
The ultra-thin body soi structure can obtain the subthreshold value amplitude of oscillation (sub threshold swing) of approximate ideal, therefore can obtain minimum subthreshold electric current.But, because reducing, the mobility that interface scattering causes make the ability of overdriving of field-effect transistor reduce greatly simultaneously because the existence of ultra-thin body causes source-drain series resistance to increase.Its raceway groove self-heating effect (self-heating effect) has further weakened its ability of overdriving.
Above the whole bag of tricks all can not be overdrived in off-state leakage current and ON state and be reached well compromise (trade-off) between the ability.
Summary of the invention
The purpose of this invention is to provide a kind of novel field-effect transistor structure, the field-effect transistor of this kind structure can be overdrived and suppress off-state leakage current effectively in the ability not weakening ON state, can also effectively reduce the parasitic capacitance between source leakage and the substrate, weaken electronics in the raceway groove from thermal phenomenon, reduce source-drain series resistance simultaneously.
Another object of the present invention provides the preparation method of described field-effect transistor.
Technical scheme of the present invention is as follows:
A kind of field-effect transistor that is applicable to the sub-micro field, comprise source leakage, gate medium, gate electrode, raceway groove and substrate, described source leak near raceway groove on one side the side and substrate between first buffer layer perpendicular to channel direction is arranged, be the connecting portion of source leakage and raceway groove between this first buffer layer top and the channel surface; Between leakage bottom, described source and substrate second buffer layer that is parallel to channel direction is arranged, this second dielectric layer and described first buffer layer connect into " L " shape.
Above-mentioned field-effect transistor, the spacing of described first buffer layer and channel surface is 0.003～0.04 micron.
Above-mentioned field-effect transistor, described first buffer layer is a silicon nitride, second buffer layer is the cavity layer.
The preparation method of above-mentioned field-effect transistor at first adopts the selective epitaxial technology to prepare first buffer layer, and the technology of further utilizing hydrogen helium to unite the buried cavity of injection formation layer prepares second buffer layer, thereby forms " L " shape buffer layer.Specifically may further comprise the steps:
1. adopt common process to form grid, side wall, lightly-doped source leakage;
2. doing mask autoregistration etching source with side wall and grid leaks;
3. deposit silicon dioxide is made resilient coating, deposit silicon nitride;
4. utilize the anisotropic etching technology to form first buffer layer;
5. utilize the selective epitaxial technology to leak in the formation source again;
6. autoregistration is injected and is formed the heavy-doped source leakage;
7. unite to inject hydrogen helium and at high temperature anneal and form the cavity layer as second buffer layer.
Fig. 1 has provided the schematic diagram of field-effect transistor structure of the present invention.In field-effect transistor structure of the present invention, most important parts are first buffer layer and second buffer layer.First buffer layer is between source leakage and the tagma, perpendicular to channel direction.Second buffer layer is positioned under the leakage of source, is parallel to channel direction.The two connects into " L " shape." L " and silicon chip surface have certain spacing, are the connecting portion of source leakage and raceway groove.The structure of being wrapped up by buffer layer is leaked in field-effect transistor employing of the present invention source, can overdrive and suppress off-state leakage current effectively in the ability not weakening ON state.In addition effectively the reduction source leak and substrate between parasitic capacitance, the electronics of raceway groove reduces source-drain series resistance from thermal phenomenon.
The field-effect transistor operation principle of this structure can be explained as follows:
One, first buffer layer mainly plays the effect of getting in touch between leakage of isolation source and the tagma.At first the p-n junction depletion region (depletion region) between source leakage and the tagma is limited in the zone between first buffer layer and the silicon face, the generation recombination current in reverse biased p-n junction district (generation-recombination current) will be limited widely like this, is directly proportional with the area in interface basically because produce recombination current.Secondly, the electric field between leak in the source mainly concentrates in the spacer medium layer of drain terminal, makes the drain terminal electric field reduce the influence of source end electromotive force, has promptly weakened to leak to cause potential barrier reduction effect.From the viewpoint of thermionic emission, its consequence is exactly to cross the number of electrons that source end potential barrier enters raceway groove and become the subthreshold electric current under the OFF state to be under control.Such first buffer layer is the key factor that suppresses short-channel effect in field-effect transistor structure of the present invention.
Three, the existence of first buffer layer does not reduce the electric current of overdriving under the ON state.Reason is after field-effect transistor is opened, the surface, tagma has formed inversion layer, it is so-called raceway groove, the thickness of this inversion layer is generally less than 100 dusts, therefore the spacing between first buffer layer and the silicon face enough allows whole inversion layer electric currents pass through, and makes that the ability of overdriving under the ON state does not significantly reduce.
Three, second buffer layer plays the effect of leakage of isolation source and substrate, and effectively living electric capacity is omitted in the reduction source, and has suppressed to leak the interband tunnelling current between the body fully.
Four, the structure that is connected with substrate of channel region has guaranteed that the lattice heat that produces under the ON state operating state scatters and disappears soon, and the mobility that is unlikely electronics impacts, and has guaranteed the ability of overdriving under the ON state.
Be described further below in conjunction with the performance of numerical result field-effect transistor of the present invention, and and the ultra-thin body soi structure, part depletion (partial depletion) soi structure, the performance of body silicon LDD (light doped drain) structure field-effect transistor compares.All analog results all are to obtain at n type field-effect transistor on 6.0 editions analog platforms of ISE (Integrated SystemEngineer).
Fig. 1 is the result schematic diagram of various field-effect transistors in the simulation.Fig. 1 (a) is a field-effect transistor of the present invention; Fig. 1 (b) is the partial depletion SOI field-effect transistor; Fig. 1 (c) is a ultra-thin body SOI field-effect transistor;
Fig. 1 (d) is a body silicon LDD field-effect transistor.The grid length of each field-effect transistor is 0.1 micron among the figure, and other structural parameters are listed in table 1.
| Field-effect transistor types | Channel doping (every cm cubes) | X j(micron) | Leakage causes potential barrier and reduces (millivolt/volt) | Off-state current (receive peace/micron) | ON state current (milliampere/micron) | Mutual conductance (Siemens/rice) |
| The present invention | 6e17 | 0.05 (h1：0.005) | 79 | 0.98 | 0.547 | 577 |
| Partial depletion SOI | 1.745e18 | 0.05 | 370 | 14.3 | 0.332 | 331 |
| Ultra-thin body SOI | 3.85e18 | 0.005 | 56 | 26.8 | 0.278 | 254 |
| Body silicon LDD | 5.59e17 (LDD：1e19) | 0.1 (XLDD：0.03) | 78 | 2.60 | 0.433 | 435 |
Table 1
Fig. 2 is that field-effect transistor of the present invention and conventional field-effect transistor are 0 volt at gate voltage, when drain voltage is respectively 0.0 volt and 1.5 volts along the static potential energy distribution contrast figure of channel surface.Transistorized grid length is 0.1 micron among the figure.Solid line is the analog result of field-effect transistor structure of the present invention, and dotted line is the analog result of conventional field-effect transistor structure.As can be seen from the figure because drain terminal voltage increases by 1.4 volts, and the source end potential barrier of field-effect transistor of the present invention has reduced by 0.062 electron-volt, the source end potential barrier of conventional field-effect transistor has then reduced by 0.1 electron-volt.Clearly, because the structure that the present invention proposes, leakage causes potential barrier reduction effect and has obtained good restraining.
The lattice temperature that Fig. 3 is field-effect transistor of the present invention and partial depletion SOI field-effect transistor under ON state operating state (being that gate voltage is that 1.5 volts, drain terminal voltage are 1.5 volts) the contrast figure that distributes.Wherein (a) is the partial depletion SOI field-effect transistor, (b) is field-effect transistor of the present invention.As can be seen from the figure, field-effect transistor of the present invention has good performance of heat dissipation, compares the partial SOI field-effect transistor, and is much lower in the lattice temperature of channel region.
Fig. 4 is operated under the ON state condition (being that gate voltage is that 1.5 volts, drain terminal voltage are 1.5 volts) for field-effect transistor of the present invention and partial depletion SOI field-effect transistor electron mobility contrasts along the distribution curve of channel direction to be schemed.Among the figure, solid line is a field-effect transistor of the present invention, and dotted line is the partial depletion SOI field-effect transistor.As can be seen from the figure, the electron mobility of partial depletion SOI field-effect transistor low than field-effect transistor of the present invention.Its reason seriously causes carrier scattering just because of its channel area lattice temperature height.
Fig. 5 has provided the comparison of the transfer characteristic of four kinds of field-effect transistors shown in Figure 1, and Fig. 6 has provided the transconductance value that curve obtains from Fig. 5, and the output characteristic that Fig. 7 has provided four kinds of field-effect transistors shown in Figure 1 compares.Among Fig. 5, Fig. 6, Fig. 7, the corresponding field-effect transistor of the present invention of solid line, dotted line counterpart depletion SOI field-effect transistor, the corresponding ultra-thin body SOI of dotted lines field-effect transistor, the corresponding body silicon of chain-dotted line LDD field-effect transistor.The threshold voltage of all field-effect transistors all is adjusted to identical value among Fig. 5, and as can be seen from Figure 5, field-effect transistor of the present invention has minimum off-state leakage current and the maximum ON state electric current of overdriving.As can be seen from Figure 6, field-effect transistor of the present invention possesses maximum mutual conductance, therefore occupies advantage on enlarging function.As can be seen from Figure 7, field-effect transistor of the present invention has the saturation current (saturation current) above other structures, and driving force is strong.
The structural parameters of the field-effect transistor of the present invention that provides at Fig. 1 and table 1, we give the optimization result.Fig. 8 is the off-state leakage current of field-effect transistor of the present invention, and ON state current and on-off ratio (switching ratio) are with the variation of h1 (spacing of first buffer layer and silicon face).Horizontal line among the figure represents that respectively ITRS (InternationalTechnology Roadmap For Semiconductors) is about the OFF state of 100 nanometer technologies and the ON state current predicted value in the low-power consumption application.As can be seen from the figure, h1 can both satisfy the requirement of ITRS between 0.003 micron and 0.04 micron.
Comprehensive above-mentioned analog computation presentation of results, field-effect transistor of the present invention has possessed various good characteristics, can effectively suppress size and dwindle the short-channel effect that brings, and it is little mainly to show as off-state leakage current, and the current capacity of overdriving is strong.Therefore, field-effect transistor of the present invention is a kind of possible alternative structure of existing field-effect transistor structure.
Description of drawings:
Fig. 1 is for field-effect transistor of the present invention and be used for ultra-thin body SOI, the partial depletion SOI of comparison, the structural representation of body silicon LDD field-effect transistor:
Fig. 1 (a) is a field-effect transistor structure schematic diagram of the present invention, among the figure:
The 11-grid; The 12-source; 13-leaks; The 14-gate oxide; The 15-side wall; 16-first buffer layer; 17-second buffer layer; The 18-substrate; H1 is the spacing between first buffer layer and the silicon face, X
jFor leaking the doping junction depth in the source.
Fig. 1 (b) ultra-thin body SOI field-effect transistor structure schematic diagram, among the figure:
The 21-grid; The 22-source; 23-leaks; The 24-gate oxide; The 25-side wall; 26-buries oxide layer; The 27-substrate; X
j-silicon film thickness, the actual junction depth of representative source leakage simultaneously;
Fig. 1 (c) partial depletion SOI field-effect transistor structure schematic diagram, among the figure:
The 31-grid; The 32-source; 33-leaks; The 34-gate oxide; The 35-side wall; 36-buries oxide layer; The 37-substrate; X
j-silicon film thickness, the actual junction depth of representative source leakage simultaneously;
Fig. 1 (d) body silicon LDD field-effect transistor structure schematic diagram, among the figure:
The 41-grid; The 42-source; 43-leaks; The 44-gate oxide; The 45-side wall; 46-lightly-doped source expansion area; 47-lightly doped drain expansion area; The 48-substrate; X
LDD-lightly-doped source leaks the junction depth of expansion area; X
jThe junction depth of heavily doped region is leaked in-source;
Fig. 2 is 0 volt for field-effect transistor of the present invention at gate voltage, and the electronics static potential energy when drain voltage is respectively 0.0 volt and 1.5 volts is along the distribution map of channel direction.
The lattice temperature that Fig. 3 is field-effect transistor of the present invention and partial depletion SOI field-effect transistor under ON state operating state (being that gate voltage is that 1.5 volts, drain terminal voltage are 1.5 volts) the contrast figure that distributes.Fig. 3 (a) is the partial depletion SOI field-effect transistor, and Fig. 3 (b) is a field-effect transistor of the present invention.
(a) in: the 311-source, 312-leaks, the 313-side wall, the 314-raceway groove, the 315-substrate,
(b) in: the 411-source, 412-leaks, the 413-side wall, the 414-raceway groove, the 415-substrate,
Fig. 4 is operated under the ON state condition (being that gate voltage is that 1.5 volts, drain terminal voltage are 1.5 volts) for field-effect transistor of the present invention and partial depletion SOI field-effect transistor electron mobility contrasts along the distribution curve of channel direction to be schemed.
Fig. 5 is the transfer characteristic curve of four kinds of field-effect transistors shown in Figure 1 when drain terminal voltage is 1.5 volts.
Fig. 6 is the transconductance characteristic curve of four kinds of field-effect transistors shown in Figure 1 when drain terminal voltage is 1.5 volts.
Fig. 7 is the output characteristic curve of four kinds of field-effect transistors shown in Figure 1 when gate voltage is respectively 0.5,1.0,1.5 volt.
Among Fig. 4, Fig. 5, Fig. 6, Fig. 7, solid line is represented field-effect transistor of the present invention, and dotted line is represented the partial depletion SOI field-effect transistor, and dotted lines is represented ultra-thin body SOI field-effect transistor, and chain-dotted line is represented body silicon LDD field-effect transistor.
Fig. 8 is the off-state current of field-effect transistor of the present invention and ON state current and on-off ratio (ON state current is than the off-state current) relation with h1 (spacing of first buffer layer and silicon face).Horizontal dotted line is represented the prediction of ITRS to off-state current higher limit and ON state current lower limit respectively among the figure.
Fig. 9 is preparation method's schematic flow sheet of field-effect transistor of the present invention.Each shadow region among the figure is expressed as follows implication: 91-monocrystalline silicon; 92-silicon dioxide; The 93-silicon nitride; The 94-polysilicon; 95-SiON; The 96-light doping section; The 97-heavily doped region;
Embodiment:
Shown in Fig. 1 (a), be the schematic diagram of field-effect transistor structure of the present invention.In this field-effect transistor structure, most important parts are first buffer layer and second buffer layer.First buffer layer is between source leakage and the tagma, perpendicular to channel direction.Second buffer layer is positioned under the leakage of source, is parallel to channel direction.The two connects into " L " shape." L " and silicon chip surface have certain spacing, are the connecting portion of source leakage and raceway groove.Vertically first buffer layer of part is formed by silicon nitride, and second buffer layer of horizontal component is then formed by the cavity layer.
Above-mentioned field-effect transistor utilizes following method to make:
L type dielectric layer in this transistor arrangement can be divided into two parts, and a part is first buffer layer of vertical part, and another part is second buffer layer of horizontal direction.At document [M.Jurczak, T.Skotnicki, R.Gwoziecki, M.Paoli, etc., " Dielectric Pockets-A New Concept of the Junctions for Deca-Nanometric CMOS Devices ", IEEE Trans.Electron Devices, Vol.48, pp.1770-1774, (2001)] in by the agency of employing selective epitaxial technology (Selective Epitaxy) successfully prepare the method for first buffer layer.The present invention further utilizes hydrogen helium to unite the buried empty layer technology of injection formation and implements to form " L " shape buffer layer that the present invention proposes on this basis.The implementation method of an exemplary as shown in Figure 9.Be elaborated below:
1. conventional bulk silicon technological forms well region, and LOCOS isolates, and mixes to channel region and adjusts threshold value, forms the structure among Fig. 9 (a);
2. thermal oxidation grid oxygen is as Fig. 9 (b);
3. the deposit polysilicon is followed deposit one deck SiON block layer, as Fig. 9 (c) as grid material;
4. photoetching grid line bar utilizes induction coupling ion etching technology etch polysilicon to add SiON, keeps the grid oxygen of source-drain area, forms the grid structure, as Fig. 9 (d);
5. LDD is injected in autoregistration, as Fig. 9 (e);
6. deposit silicon nitride utilizes reactive ion etching technology to form side wall (spacer), as Fig. 9 (f);
7. remove the silicon dioxide that leak in the source, then with the thick oxide layer in silicon nitride side wall and SiON block floor and the LOCOS district as mask, utilize anisotropic plasma etch technology etching source-drain area, the degree of depth is by the height decision of first buffer layer, as Fig. 9 (g);
8.PECVD the deposit layer of silicon dioxide is as resilient coating, deposit one deck silicon nitride then is as Fig. 9 (h);
9. utilize the anisotropic etching technology to form first buffer layer afterwards once more, accurately control the over etching rate, make the spacing of win buffer layer and channel surface reach design load, guarantee that LDD is connected with heavily doped region in the future, wet etching falls the silicon dioxide of PECVD deposit then, as Fig. 9 (i);
10. part that LDD is exposed and source water clock erosion depressed area utilizes the selective epitaxial technology that groove is leaked in the source that is etched and fills upward silicon, and be connected with LDD, as Fig. 9 (j) as the extension seed;
11. the heavy-doped source drain region is injected in autoregistration, as Fig. 9 (k);
12. hydrogen helium is injected in autoregistration, dosage is greater than the formation threshold value in cavity;
13. annealing is 30 seconds under at least 1100 ℃ of following high temperature, forms the cavity layer, activates all impurity simultaneously, forms final " L " type structure, as Fig. 9 (l).
" L " type buffer layer of this method preparation is made of two kinds of different materials, and vertically first buffer layer of part is formed by silicon nitride, and second buffer layer of horizontal component is then formed by the cavity layer.
Claims (4)
1. field-effect transistor that is applicable to the sub-micro field, comprise source leakage, gate medium, gate electrode, raceway groove and substrate, it is characterized in that, described source leak near raceway groove on one side the side and substrate between first buffer layer perpendicular to channel direction is arranged, be the connecting portion of source leakage and raceway groove between this first buffer layer top and the channel surface; Between leakage bottom, described source and substrate second buffer layer that is parallel to channel direction is arranged, this second dielectric layer and described first buffer layer connect into " L " shape.
2. field-effect transistor as claimed in claim 1 is characterized in that, the spacing between described first buffer layer top and the channel surface is 0.003～0.04 micron.
3. field-effect transistor as claimed in claim 1 or 2 is characterized in that, described first buffer layer is a silicon nitride, and described second buffer layer is the cavity layer.
4. preparation method who is applicable to the field-effect transistor in sub-micro field may further comprise the steps:
(1) adopt common process to form grid, side wall, lightly-doped source leakage;
(2) doing mask autoregistration etching source with side wall and grid leaks;
(3) deposit silicon dioxide is made resilient coating, deposit silicon nitride;
(4) utilize the anisotropic etching technology to form first buffer layer;
(5) utilize the selective epitaxial technology to leak in the formation source again;
(6) autoregistration is injected and is formed the heavy-doped source leakage;
(7) unite injection hydrogen helium and annealing at high temperature and form empty layer as second buffer layer.
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| CN1303656C (en) * | 2004-06-18 | 2007-03-07 | 北京大学 | A method for preparing quasi SOI field effect transistor device |
| CN101226881B (en) * | 2007-01-16 | 2010-09-15 | 北京大学 | Method for manufacturing dent source leakage field effect transistor |
| CN102487033B (en) * | 2010-12-03 | 2014-04-02 | 中芯国际集成电路制造(北京)有限公司 | Method for forming standard SOI (Silicon On Insulator) structure |
| CN102543826B (en) * | 2010-12-31 | 2014-12-24 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of quasi silicon-on-insulator (SOI) structure |
| CN103390555B (en) * | 2012-05-08 | 2015-12-09 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of metal oxide semiconductor transistor |
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