CN102751316A - Transverse signal operation instruction (SOI) power device - Google Patents
Transverse signal operation instruction (SOI) power device Download PDFInfo
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- CN102751316A CN102751316A CN2012102710580A CN201210271058A CN102751316A CN 102751316 A CN102751316 A CN 102751316A CN 2012102710580 A CN2012102710580 A CN 2012102710580A CN 201210271058 A CN201210271058 A CN 201210271058A CN 102751316 A CN102751316 A CN 102751316A
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Abstract
The invention discloses a transverse signal operation instruction (SOI) power device. The transverse SOI power device comprises a semiconductor substrate, an insulating medium layer and a semiconductor active layer, wherein a body region and a drain region are arranged on the surface of the semiconductor active layer, an interval exists between the body region and the drain region to form a drift region of the device, a body contact region and a source region are sequentially formed on the surface of the body region, a silicon window is arranged on the insulating medium layer, the bottom of the body region is located in the silicon window or enters into the semiconductor substrate through the silicon window, the bottom of the body contact region enters into the silicon window, and a common leading-out end of the source region and the body contact region serves as a source electrode. The transverse SOI power device has the advantages that the body region is effectively led out, floating body effects of a Kink effect, a parasitic triode effect, memory effect and the like are eliminated, the off state withstand voltage and gate control capacity are improved, simultaneously the puncture voltage in an on state is boosted, characteristics of the SOI device are improved, and the possibility of a partial appendage effect appearing in a T-shaped gate structure and a base transceiver station (BTS) structure is eliminated.
Description
Technical field
The present invention relates to soi semiconductor power device and SOI smart-power IC technical field.
Background technology
Between the active layer and substrate of SOI circuit, high pressure separate fully through insulating barrier between the low voltage unit, and the active layer of silica-based circuit and substrate directly are electrically connected, the isolation between the high-low pressure unit, between active layer and the substrate layer is accomplished through anti-PN junction partially.Compare with the body silicon technology, the SOI technology has high speed, low-power consumption, high integration and is convenient to advantage such as isolation, and has weakened latch up effect and possessed very strong anti-irradiation ability, and the reliability of SOI integrated circuit and anti-soft failure ability are improved greatly.
Smart-power IC (SPIC) is owing to adopt single-chip integrated, and SPIC reduces former number of packages, interconnecting number and the solder joint number in the system, has not only improved reliability, the stability of system, and has reduced power consumption, volume, weight and the cost of system.Than the body silicon technology, the advantage that the SOI technology has will make its utilization widely of arriving at smart-power IC.
In order to obtain the excellent specific property of SOI device, SOI will have thin top layer silicon, but the tagma of SOI cmos device is difficult to the method for body silicon device the tagma drawn like this, and this will cause SOI cmos device tagma floating empty.The floating sky in tagma brings harmful effect to device, such as floater effect (comprising Kink effect, parasitic triode effect, memory effect, single tube breech lock), self-heating effect or the like.These shortcomings bring obstruction for the popularization of SOI technology.Power device and conventional device integrate in smart-power IC; So the top layer silicon thickness of power device and the top layer silicon of SOI cmos device are of uniform thickness; Power device will run into the problem the same with the SOI cmos device, and the withstand voltage power device field that is reduced in that floater effect causes becomes matter of utmost importance.
For the problem of the degradation of the SOI device that solves the floating blanking bar in tagma, traditional SOI tagma outbound course is to utilize T type grid that the tagma of SOI MOS device is drawn from channel width dimension, and is as shown in Figure 1.This device architecture makes gate capacitance increase because grid increase the active area area coverage.B.W. Min for this reason; L. people such as Kang is at document [Reduction of Hysteretic Propagation Delay with Less Performance Degradation by Novel Body Contact in PD SOI Application]---and ([the body contact of the novelty that under the prerequisite that guarantees device performance, reduces sluggish propagation delay that adopts in a kind of full-exhaustion SOI utilization]; In the international SOI meeting of holding in U.S. Williamsburg 7 days to No. 10 October in 2002 of IEEE, deliver; The page number: propose a kind of T type grid structure 169-170), this structure is through below grid, growth one bed thickness grid oxygen reduces gate capacitance above the body contact path.T type grid structure is applicable to the device that channel width is little, and this is because of the increase along with channel width, and far away more to the body contact zone away from the tagma of body contact zone, dead resistance is big more, can produce local floater effect, causes the body contact to be lost efficacy.In order to satisfy the big current capacity of power device, power device has very big channel width, so T type grid structure is not suitable for power device.Industry has proposed H type grid structure for this reason, and H type grid structure can appropriateness alleviation channel width increase the floater effect that causes the part, but still can't effectively suppress local floater effect for the so long channel device H type grid structure of power device.
Can adopt source body interconnection (BTS) structure to realize that as shown in Figure 2, draw in the tagma is with the metal interconnected P that contacts simultaneously at the big SOI MOS device of channel width
+Body contact zone and N
+Accomplish in the source region.Reasonably design P
+The spacing of body contact zone can effectively suppress local floater effect.This structure can be used for the body contact of power device; Steven L. is at his U.S. Pat 005767547A; (denomination of invention: HIGH VOLTAGE THIN FILM TRANSISTOR HAVING A LINEAR DOPING PROFILE)---(high voltage thin film transistor with linear doping) adopted this body contact structure, effectively suppressed floater effect.But the BTS structure also has shortcoming: in order effectively to suppress local floater effect, suitable raising P
+The density of body contact zone, but along with P
+The raising P of the density of body contact zone
+The body contact zone takies N
+The area in source region is also big more, causes the effective width of raceway groove to reduce, the contact resistance of source end increases, and causes the decline of current capacity of the power device of same channel width.
Summary of the invention
For solving existing technical problem in the above-mentioned prior art; The present invention proposes a kind of horizontal SOI power device; Adopt the present invention; On the one hand, solved that the OFF state that the floater effect of the floating empty horizontal SOI LDMOS in conventional tagma causes is withstand voltage, the problem of the puncture voltage decline when grid-control system ability, ON state, improved the SOI Devices Characteristics; On the other hand, solved the problem of the local appendage effect that T type grid structures occurs when the device channel width is big; On the one hand, solved BTS structure P again
+The body contact zone takies N
+The source region the raceway groove effective width that causes of area reduce the problem that increases with the source electrode contact resistance, and the BTS structure is at P
+The problem of local appendage effect appears in body contact zone spacing when wide.
The present invention realizes through adopting following technical proposals:
A kind of horizontal SOI power device; Comprise Semiconductor substrate, the insulating medium layer that is provided with on the Semiconductor substrate be positioned at insulating medium layer above semiconductor active layer, have tagma and drain region on the semiconductor active layer surface; Between said tagma and the drain region spacing is arranged; Form the drift region of device, on surface, said tagma organizator contact zone and source region successively, it is characterized in that: said insulating medium layer is provided with the silicon window; The bottom in said tagma gets into Semiconductor substrate in the silicon window or through the silicon window, the bottom of said body contact zone gets into the silicon window;
On the semiconductor active layer surface between said source region and the drift region is planar gate structure, and the common exit of said source region and body contact zone is the source electrode, and said drain region exit is a drain electrode, and the planar gate exit is a gate electrode.
The bottom of body contact zone gets into the silicon window, does not so just have the junction depth restriction, and conventional energy just can realize that the body contact zone injects, and does not need low-yield implanter, and dark tagma junction depth can guarantee that the dead resistance in the tagma below the source region is less.
When Semiconductor substrate is identical with the drift region conduction type, said silicon window near the border of drain terminal between the interface of the interface in tagma and source region and tagma and drift region.Because drift region and substrate are conduction types of the same race, be in order to prevent drift region and substrate short circuit to the restriction of silicon window.
When Semiconductor substrate was identical with the drift region conduction type, the silicon window equaled the length of half gate medium near the distance of border end to the source of drain terminal.
When Semiconductor substrate and drift region conduction type are inequality, said silicon window near the border of drain terminal between the boundary of the boundary in tagma and source region and drain terminal and drift region.
Preferably, the thickness of said semiconductor active layer is less than 0.5 μ m.Deep-submicron SOI CMOS has a lot of ghost effects: short-channel effect, narrow-channel effect, ultra-thin semiconductor active layer help suppressing the characteristic that these effects improve deep-submicron SOI cmos device.For can better with the ultra-thin SOI CMOS process compatible of deep-submicron, the thickness of the semiconductor active layer of power device is less than 0.5 μ m.
End adopts the varying doping technology to form to drain terminal to the employing of described drift region from the source.Described from the source end to drain terminal adopt doping that the varying doping technology is meant the drift region near tagma one end to the doping techniques that increases gradually near drain region one end, belong to prior art.
Super-junction structure is adopted in described drift region.Described super-junction structure is meant that the drift region is made up of respectively at drain region and the contacted P arranged side by side in tagma, N bar two ends, belongs to prior art.
Described horizontal SOI power device adopts the structure of back of the body etching.The structure of described back of the body etching is meant that from the Semiconductor substrate bottom upwards the Semiconductor substrate of below, etched features drift region belongs to prior art until the structure that insulating medium layer forms.
Described horizontal SOI power device applications is on the semiconductor power device of MOS control.As LDMOS (Lateral Double diffusion Metal Oxide Semiconductor), LIGBT ((Lateral Insulated Gate Bipolar Transistor), MCT (Mos Controlled Thyristors), GTO (Gate Turn-off Thyristors), thus alleviate the contradictory relation between withstand voltage, conducting resistance and the switching loss.
Described Semiconductor substrate, insulating medium layer, semiconductor active layer constitute the SOI material, and the SOI material preparation method includes but not limited to SDB (Silicon Direct Bonding), ZMR (Zone Melting Recrystallization), SIMOX (Separation by IMplanted Oxygen), SMART CUT technology.
Described silicon window can from its surface beginning etched portions semiconductor active layer and insulating medium layer, finish up to Semiconductor substrate through existing SOI material, and epitaxially grown silicon forms the silicon window then.Also can before making the SOI material, form the silicon window.
Compared with prior art, beneficial effect of the present invention shows:
One, among the present invention; Adopt " said insulating medium layer is provided with the silicon window; the bottom in said tagma gets into Semiconductor substrate in the silicon window or through the silicon window, and the bottom of said body contact zone gets into the silicon window, and the common exit of said source region and body contact zone is the source electrode " such frame mode; Thereby just make the present invention form the horizontal SOI power unit structure that draw through the silicon window in the tagma, thus following technique effect had:
1, adopt new tagma outbound course, effectively suppressed floater effect: improved the puncture voltage of OFF state, and the puncture voltage when improving ON state.
2, adopt new tagma outbound course, the tagma does not change along with the variation of channel width to the distance of body contact zone, just needn't consider how to design P
+The spacing of body contact zone prevents local floater effect, and P
+The body contact zone does not take N
+The source region area, raceway groove effective width and source electrode contact resistance can not receive P
+The influence of body contact zone.
3, with conventional tagma floating empty horizontal SOI power device (like Fig. 3) compare, the present invention has heightened that OFF state is withstand voltage, the puncture voltage when grid-control system ability, ON state; Compare with T type grid structures (Fig. 1), the invention solves the problem of the local appendage effect that when the device channel width is big, occurs; With the first ratio of BTS structure (Fig. 2), there is not P in the present invention
+The body contact zone takies N
+The source region the problem that the raceway groove effective width that causes of area reduces and the source electrode contact resistance increases and the problem of local appendage effect.
Two, with reference to embodiment 1 and checking embodiment, adopt as structure of the present invention, also have following technique effect:
1, with FOM=BV
2/ R
ON, SPBe optimisation criteria, the floating empty structure in the present invention and tagma is compared and has withstand voltagely been improved 35%, and conduction resistance has reduced by 20%;
2, during ON state, identical (
V GS -V TH ) slope of output characteristic curve of the present invention in the saturation region is significantly less than the floating hollow structure in tagma, the enhancing of grid-control system drain current ability under the condition;
3, the puncture voltage of the present invention when ON state also obviously improves, (
V GS -V TH The present invention compares withstand voltage raising 25% with the floating empty structure in tagma during)=4V;
4, effectively eliminated the Kink effect;
5, the silicon window is of value to heat radiation, alleviates the self-heating effect of SOI device;
6, and the isolation technology between the conventional cmos device simple, be easy to integrated;
7, in a word, the present invention effectively draws the tagma, has eliminated floater effects such as Kink effect, parasitic triode effect, memory effect; It is withstand voltage to improve OFF state, improves grid-control system ability, the puncture voltage when improving ON state simultaneously; Improved the SOI Devices Characteristics, and P
+The body contact zone does not take N
+The source region area, raceway groove effective width and source electrode contact resistance can not receive P
+The possibility that local appendage effect appears in T type grid structure and BTS structure has also been eliminated in the influence of body contact zone.
Three, among the present invention; The present invention adopt " when Semiconductor substrate is identical with the drift region conduction type; said silicon window near the border of drain terminal between the interface of the interface in tagma and source region and tagma and drift region " structure; Like this, when drift region and substrate are conduction types of the same race, just can prevent drift region and substrate short circuit.
Four, among the present invention; The structure of preferred employing " when Semiconductor substrate was identical with the drift region conduction type, the silicon window equaled the length of half gate medium near the distance of border end to the source of drain terminal " is that the isolation effect of drift region and substrate is best because when Semiconductor substrate is identical with the drift region conduction type; Can prevent break-through in advance between drift region and the substrate; On the other hand, the tagma can effectively be drawn, and eliminates floater effect.
Five, among the present invention, the thickness of said semiconductor active layer is less than 0.5 μ m, so just can better with the ultra-thin SOI CMOS process compatible of deep-submicron.
Six, among the present invention; The drift region adopts horizontal varying doping technology to form; Horizontal super-junction structure is adopted in the drift region, and laterally the SOI power device adopts these modes of structure of carrying on the back etching, can both effectively suppress substrate-assisted depletion effect; Improved horizontal and vertical withstand voltagely, realized on thin top layer silicon, the thin SOI material that buries dielectric layer, to make the technique effect of high tension apparatus.
Description of drawings
To combine Figure of description and embodiment that the present invention is done further detailed description below, wherein:
Fig. 1 is T type grid structural representations (vertical view);
Fig. 2 is source body interconnection (BTS) SOI device architecture sketch map (vertical view);
Fig. 3 be conventional tagma floating empty horizontal SOI LDMOS structural profile sketch map;
Fig. 4 is the tagma horizontal N channel SOI LDMOS generalized section of drawing through the silicon window according to an embodiment of the invention;
Fig. 5 is the generalized section of the tagma horizontal P channel SOI of drawing through the silicon window according to an embodiment of the invention;
Fig. 6 is the tagma horizontal N channel SOI LIGBT structural profile sketch map of drawing through the silicon window according to an embodiment of the invention;
Fig. 7 is the tagma horizontal N channel SOI super junction LDMOS structure sketch map of drawing through the silicon window according to an embodiment of the invention, and wherein, Fig. 7 a is the device vertical view, and Fig. 7 b is an A-A ' profile among Fig. 7 a, and Fig. 7 c is a B-B ' profile among Fig. 7 a;
Fig. 8 is the LDMOS structural profile sketch map that the SOI material of the tagma horizontal N raceway groove of drawing through the silicon window according to an embodiment of the invention adopts back of the body etching;
Fig. 9 is the floating empty SOI LDMOS drift region in the present invention and tagma relation between puncture voltage and the doping slope when adopting linear doping;
Figure 10 is the output characteristic curve of the horizontal N channel SOI LDMOS that draws through the silicon window of horizontal SOI LDMOS and the tagma of the floating empty N raceway groove in conventional tagma;
Figure 11 tagma floating empty the forward conduction of horizontal SOI LDMOS of N raceway groove the time main current diagram.
The integrated sketch map of Figure 12 high tension apparatus and low-voltage device.
Mark among the figure:
1 represents Semiconductor substrate, and 2 represent insulating medium layer, 3 representative tagmas, and 4 representative drift regions, 5 represent the body contact zone; 6 representative source regions, 7 representative drain regions, 8 represent an oxygen layer, and 9 represent gate dielectric layer, and 10 represent metal level; 11 represent polysilicon layer, and 12 represent carrying out local oxide isolation (LOCOS), and 13 represent the silicon window, and 14, low-voltage ic, 15, high tension apparatus; S, source electrode, D, drain electrode, G, gate electrode, Substrate, underlayer electrode.
Embodiment
< embodiment 1 >
Fig. 3 is as the floating empty horizontal SOI LDMOS structure chart in conventional n type tagma relatively;
Fig. 4 is that the present invention proposes, the horizontal N channel SOI LDMOS structural representation that draw through the silicon window in the tagma.
The horizontal N channel SOI LDMOS structure that draw through the silicon window in the tagma among Fig. 4 comprises: Semiconductor substrate 1, the insulating medium layer that is provided with on the Semiconductor substrate 12 be positioned at insulating medium layer 2 above semiconductor active layer.Described Semiconductor substrate 1, insulating medium layer 2, semiconductor active layer constitute the SOI material, at said insulating medium layer 2 silicon window 13 are set.
Have P type tagma and N on described semiconductor active layer surface
+The drain region, said P type tagma and N
+Spacing is arranged between the drain region, form the N type drift region of device; Form P successively on surface, said P type tagma
+Body contact zone, N
+The source region; Bottom, said P type tagma gets into Semiconductor substrate 1 in silicon window 13 or through silicon window 13; Said P
+The bottom of body contact zone gets into silicon window 13.
At said N
+On the semiconductor active layer surface between source region and the N type drift region is planar gate structure; Said N
+Source region and P
+The common exit of body contact zone is source electrode S, said P
+The drain region exit is drain electrode D, and the planar gate exit is gate electrode G.
Described Semiconductor substrate 1 is identical with described drift region conduction type, said silicon window 13 near the border of drain terminal at P type tagma and N
+Between the interface of the interface in source region and P type tagma and N type drift region.Because N type drift region and Semiconductor substrate 1 are conduction types of the same race, be in order to prevent N type drift region and Semiconductor substrate 1 short circuit to the restriction of silicon window 13.Preferred silicon window 13 is near N
+The border of drain terminal is to N
+The distance of source end equals the length of half gate dielectric layer 9.
The thickness of semiconductor active layer is less than 0.5 μ m.Between the power device in the semiconductor active layer and selective oxidation between the conventional device (LOCOS) isolation technology isolate.
The raising device withstand voltage method that said device adopts includes but not limited to adopt sj structure, the sectional doped technology in employing drift region, adopts drift region linear doping technology, the structure that adopts back of the body etching, the trapezoidal grid field plate techniques of employing.The doping that described horizontal varying doping technology is meant the drift region near tagma one end to the doping techniques that increases gradually near drain region one end.Described SOI material adopts the structure of back of the body etching, and the structure of described back of the body etching is meant the structure that the Semiconductor substrate 1 of the below, etched features drift region that makes progress from Semiconductor substrate 1 bottom forms until insulating medium layer 2.
The P type tagma of N raceway groove includes but not limited to SDB, ZMR, SIMOX, SMART CUT technology through the SOI material preparation method of the horizontal SOI power unit structure that silicon window 13 is drawn.On the SOI material for preparing, begin local etching from top layer silicon and wear insulating medium layer 2 up to quarter, epitaxially grown silicon forms silicon window 13 then.
< embodiment 2 >
The horizontal SOI LDMOS structure of drawing through the silicon window with the tagma of N raceway groove above is the structure that example has been explained semiconductor device of the present invention, and structure of the present invention is equally applicable to P channel laterally SOI LDMOS.Horizontal SOI LDMOS as shown in Figure 5 is corresponding with the structure of the horizontal SOI LDMOS of Fig. 4; Just the N channel SOI LDMOS by Fig. 4 becomes P channel SOI LDMOS; So corresponding change of the conduction type of each semiconductor regions; In order to form current path between source of preventing and the substrate, can only adopt P type substrate.P channel SOI LDMOS but of the present invention is not suitable for low pressure SOI cmos device integrated.
< embodiment 3 >
The horizontal SOI LDMOS structure of drawing through the silicon window with the tagma above is the structure that example has been explained semiconductor device of the present invention, and structure of the present invention is equally applicable to horizontal SOI LIGBT structure.Horizontal SOI IGBT structure as shown in Figure 6 is corresponding with the structure of the horizontal SOI LDMOS of Fig. 4, and just the N channel SOI LDMOS by Fig. 4 becomes N channel SOI LIGBT, so 7 the corresponding change of conduction type of draining.N channel SOI LIGBT of the present invention can well be integrated on the same chip with N channel SOI LDMOS and low pressure SOI cmos device.P channel SOI IGBT is the same with P channel SOI LDMOS be not suitable for low pressure SOI cmos device integrated.
< embodiment 4 >
Horizontal super-junction structure is adopted in the drift region in the present embodiment.Horizontal N channel SOI super junction LDMOS structure as shown in Figure 7 is corresponding with the structure of the horizontal SOI LDMOS of Fig. 4, and the drift region of different is horizontal N channel SOI super junction LDMOS structure is a super-junction structure.The P of described super-junction structure, N bar are non-equilibrium structures.
< embodiment 5 >
The SOI material of the present embodiment horizontal N raceway groove that to be the tagma draw through the silicon window adopts the LDMOS structure of back of the body etching.The SOI material of horizontal N raceway groove as shown in Figure 8 adopts the LDMOS structure of back of the body etching corresponding with the structure of the horizontal SOI LDMOS of Fig. 4; Different is, and the SOI material adopts the structure of back of the body etching, and the structure of described back of the body etching is meant the structure that the Semiconductor substrate 1 of the below, etched features drift region that makes progress from Semiconductor substrate 1 bottom forms until insulating medium layer 2.
The structure of the invention described above significantly improves the characteristic of SOI power device, has effectively suppressed floater effect, for example with FOM=BV
2/ R
ON, SPBe optimisation criteria, the floating empty structure in the present invention and tagma is compared and has withstand voltagely been improved 35%, and conduction resistance has reduced by 20%, and grid are to the control ability of drain current when having improved forward conduction, and the floating empty structure in the withstand voltage and tagma under the ON state is compared withstand voltage raising 25%.
< embodiment 6 >-checking example
Compare through the floating empty conventional SOI LDMOS structure of semiconductor device of the present invention among Fig. 4 and the tagma among Fig. 3 below and further specify advantage of the present invention, wherein the drift region all adopts linear doping to suppress the influence that the substrate-assisted depletion effect brings:
1. device property analysis
1) close step response:
As shown in Figure 9, SOI LDMOS structure of the present invention is along with the influence of the increase substrate-assisted depletion of linear doping slope weakens withstand voltage also raising thereupon; The drift region doping content is too high greater than certain value the time when causing puncturing that the drift region fails all to exhaust when it along with slope continue to increase, and device withstand voltage will increase and reduces with slope at this moment.
The tagma effectively picks out its withstand voltage parasitic triode that is equivalent to of LDMOS
BV CBO , empty LDMOS is equivalent to a base open circuit under off state NPN pipe is floated in the tagma, and it is withstand voltage that its withstand voltage NPN that is to open a way in the base manages
BV CEO ,
So the floating sky in tagma can cause the withstand voltage decline of device.The criterion that we will puncture through the parasitic triode of open base
Explain the reason of the withstand voltage decline of LDMOS of the floating sky in tagma, wherein
It is emitter injection efficiency
It is the few sub-transport coefficient in base
MMultiplication constant.The few sub-transport coefficient in base
Size with do not exhaust base width (
W B -
W D ) and minority carrierdiffusion length
L p It is relevant,
It is the main cause of device breakdown that the low substrate-assisted depletion of doping of drain terminal is leaned in floating empty LDMOS drift region when the linear doping slope is little, tagma because substrate-assisted depletion makes the main expansion toward the drift region of depletion region, do not exhaust base width (
W B -
W D ) almost constant when little linear doping slope
Almost constant, so the floating empty LDMOS withstand voltage rate of descent when the linear doping slope is little in tagma is about the same.So work as drift region doping slope less than 1.4E+20cm
-4The time, floating empty the withstand voltage of LDMOS in tagma increases along with the increase of drift region doping slope, and the floating empty withstand voltage increase with drift region doping slope of LDMOS in tagma as shown in Figure 8 has the process of a rising.
Along with the influence of the increase substrate-assisted depletion of linear doping slope is eliminated gradually, at this moment the drift region more is to lean on horizontal pn to tie to exhaust, and along with the increase drift region concentration of linear doping slope increases, the ratio of depletion region expansion toward the tagma also increases thereupon.Under same drain voltage, with the linear doping slope of drift region be 1.4E+20cm
-4Comparing slope is 2.2E+20cm
-4The time depletion region toward base diffusion at most
Greatly, and the depletion widths in the drift region reduce to cause electric field to increase
MAlso increase, then thereupon
Drain voltage littler reaches 1, so work as drift region linear doping slope greater than 1.4E+20cm
-4The puncture voltage of the LDMOS that Shi Tiqu is floating empty can descend thereupon the increase of the slope that mixes, and is as shown in Figure 8.
By Fig. 7 can find out since the present invention with the effective short circuit of parasitic triode emitter junction, so the parasitic triode effect effectively suppressed, with FOM=BV
2/ R
ON, SPBe optimisation criteria, the floating empty structure in the present invention and tagma is compared and has withstand voltagely been improved 35%.
2) ON state output characteristic:
With FOM=BV
2/ R
ON, SPBe optimisation criteria, the floating empty SOI LDMOS structure in the present invention and the tagma conduction resistance of the present invention of comparing has reduced by 20%.This be since drift region doping slope big the time parasitic triode effect obvious, cause withstand voltagely significantly reducing, like this with FOM=BV
2/ R
ON, SPTo obtain the corresponding drift region concentration ratio the present invention of the floating empty SOI LDMOS optimal value in tagma low for optimisation criteria, so conducting resistance of the present invention reduces.
The output characteristic of the floating empty SOI LDMOS in the present invention and tagma can know that the output characteristic of the floating empty SOI LDMOS in tagma is precipitous and puncture voltage is little among contrast Figure 10, and this is still to work because of parasitic triode under situation about exhausting entirely.
Main current diagram when Figure 11 is the forward conduction of horizontal SOI LDMOS of the floating empty N raceway groove in tagma.Under certain grid voltage, along with leaking the increase of pressing, output characteristic curve gets into the saturation region, according to the output characteristic curve of saturation region
, in the saturation region output current along with
V DS Increase and linear increasing.But by Figure 10 can find out curve of output along with the increase of leak pressing warpage upwards, this is because along with the electric field in the increase drift region of drain voltage increases wherein multiplication constant
MIncrease the hole current that ionization by collision produces
(formula 1) also increases thereupon, wherein
I CH Be channel current,
I BI It is the parasitic triode collector current.When hole current inflow tagma is the base of parasitic triode; Hole current is exaggerated;
(formula 2) makes more electronics arrive the drift region through parasitic triode; The hole that makes the collision electric current produce in the drift region from the parasitic triode injected electrons increases, and forms positive feedback.Along with drain current increases the influence increase that ionization by collision produces; Consider that the ionization by collision drain current is rewritten as
(formula 3), thus the amplification hole current effect of ionization by collision and parasitic triode be cause curve of output along with the increase of leak pressing the reason of warpage upwards.The present invention has effectively suppressed the parasitic triode effect; That considers the figure ionization by collision influences drain current
; This also is the reason of output characteristic curve of the present invention off-straight in the saturation region, shown in Figure 10.The output characteristic that compares the SOI LDMOS of the floating sky of the present invention and tagma in 10, output characteristic curve of the present invention more near straight line, so structure of the present invention effectively suppresses the parasitic triode effect, improve the control ability of grid to leakage current in the saturation region.
Can find out that from the simulation work of front the present invention effectively draws the tagma, eliminate floater effects such as Kink effect, parasitic triode effect, memory effect; It is withstand voltage to improve OFF state, improves grid-control system ability, the puncture voltage when improving ON state simultaneously; Improved the SOI Devices Characteristics, and P
+The body contact zone does not take N
+The source region area, raceway groove effective width and source electrode contact resistance can not receive P
+The possibility that local appendage effect appears in T type grid structure and BTS structure has also been eliminated in the influence of body contact zone.
Figure 12 is high tension apparatus of the present invention and the integrated sketch map of low-voltage device, and the isolation technology of the SOI cmos device of available routine realizes between the high-low voltage device, for example selective oxidation (LOCOS) isolation technology, shallow grooved-isolation technique etc.It is thus clear that high tension apparatus of the present invention and low-voltage device isolation technology are simple, be easy to and the integrated smart-power IC of doing of low-voltage device.And the advantage that the SOI technology has will make the present invention that very big development space is arranged aspect smart-power IC.
Claims (9)
1. horizontal SOI power device; Comprise Semiconductor substrate (1); Insulating medium layer (2) that is provided with in Semiconductor substrate (1) top and the semiconductor active layer that is positioned at the top of insulating medium layer (2); Have tagma (3) and drain region (7) on the semiconductor active layer surface, between said tagma (3) and drain region (7) spacing is arranged, form the drift region (4) of device; On surface, said tagma (3) organizator contact zone (5) and source region (6) successively; It is characterized in that: be provided with silicon window (13) at said insulating medium layer (2), the bottom of said tagma (3) gets into Semiconductor substrate (1) in silicon window (13) or through silicon window (13), and the bottom of said body contact zone (5) gets into silicon window (13);
On the semiconductor active layer surface between said source region (6) and drift region (4) is planar gate structure; The common exit of said source region (6) and body contact zone (5) is the source electrode; Said drain region (7) exit is a drain electrode, and the planar gate exit is a gate electrode.
2. a kind of horizontal SOI power device according to claim 1; It is characterized in that: when Semiconductor substrate (1) and drift region (4) when conduction type is identical, said silicon window (13) near the border of drain terminal between the interface of the interface of tagma (3) and source region (6) and tagma (3) and drift region (4).
3. a kind of horizontal SOI power device according to claim 2 is characterized in that: when Semiconductor substrate (1) and drift region (4) when conduction type is identical, silicon window (13) equals the length of half gate medium near the distance of border end to the source of drain terminal.
4. a kind of horizontal SOI power device according to claim 1; It is characterized in that: when Semiconductor substrate (1) and drift region (4) when conduction type is inequality, said silicon window (13) near the border of drain terminal between the boundary of the boundary of tagma (3) and source region (6) and drain region (7) and drift region (4).
5. a kind of horizontal SOI power device according to claim 1, it is characterized in that: the thickness of said semiconductor active layer is less than 0.5 μ m.
6. a kind of horizontal SOI power device according to claim 1 is characterized in that: described drift region (4) end adopts the varying doping technology to form to drain terminal from the source.
7. a kind of horizontal SOI power device according to claim 1 is characterized in that: super-junction structure is adopted in described drift region (4).
8. a kind of horizontal SOI power device according to claim 1 is characterized in that: described horizontal SOI power device adopts the structure of back of the body etching.
9. a kind of horizontal SOI power device according to claim 1 is characterized in that: described horizontal SOI power device applications is on the semiconductor power device of MOS control.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103021864A (en) * | 2012-12-11 | 2013-04-03 | 中国科学院上海微系统与信息技术研究所 | Silicon On Insulator (SOI) Reduced Surface Field (RESURF) superjunction device structure and production method thereof |
| CN106024873A (en) * | 2016-05-20 | 2016-10-12 | 电子科技大学 | Transverse IGBT |
| CN109801962A (en) * | 2019-01-23 | 2019-05-24 | 电子科技大学 | A kind of double grid control Sampling device based on LIGBT |
| CN111370310A (en) * | 2018-12-26 | 2020-07-03 | 中芯集成电路（宁波）有限公司 | Semiconductor structure and forming method thereof |
| CN111952368A (en) * | 2019-05-17 | 2020-11-17 | 宁波宝芯源功率半导体有限公司 | SOI (silicon on insulator) transverse LDMOS (laterally diffused metal oxide semiconductor) device with super junction structure and manufacturing method |
| CN111952351A (en) * | 2019-05-17 | 2020-11-17 | 宁波宝芯源功率半导体有限公司 | SOI (silicon on insulator) transverse LDMOS (laterally diffused metal oxide semiconductor) device with super junction structure and manufacturing method |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6566176B1 (en) * | 2001-01-31 | 2003-05-20 | Advanced Micro Devices, Inc. | SOI device with wrap-around contact to underside of body, and method of making |
| US20080224214A1 (en) * | 2007-02-15 | 2008-09-18 | Fuji Electric Holdings Co., Ltd. | Semiconductor device and fabrication method |
| CN101533854A (en) * | 2009-04-23 | 2009-09-16 | 哈尔滨工程大学 | SOILDMOS transistor with changeover body connection |
| CN102130012A (en) * | 2010-12-31 | 2011-07-20 | 中国科学院上海微系统与信息技术研究所 | LDD, LDS and buffer layer integrated manufacturing method for SOI super-junction LDMOS device |
-
2012
- 2012-07-31 CN CN2012102710580A patent/CN102751316A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6566176B1 (en) * | 2001-01-31 | 2003-05-20 | Advanced Micro Devices, Inc. | SOI device with wrap-around contact to underside of body, and method of making |
| US20080224214A1 (en) * | 2007-02-15 | 2008-09-18 | Fuji Electric Holdings Co., Ltd. | Semiconductor device and fabrication method |
| CN101533854A (en) * | 2009-04-23 | 2009-09-16 | 哈尔滨工程大学 | SOILDMOS transistor with changeover body connection |
| CN102130012A (en) * | 2010-12-31 | 2011-07-20 | 中国科学院上海微系统与信息技术研究所 | LDD, LDS and buffer layer integrated manufacturing method for SOI super-junction LDMOS device |
Cited By (12)
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|---|---|---|---|---|
| CN103021864A (en) * | 2012-12-11 | 2013-04-03 | 中国科学院上海微系统与信息技术研究所 | Silicon On Insulator (SOI) Reduced Surface Field (RESURF) superjunction device structure and production method thereof |
| CN103021864B (en) * | 2012-12-11 | 2015-07-01 | 中国科学院上海微系统与信息技术研究所 | Silicon On Insulator (SOI) Reduced Surface Field (RESURF) superjunction device structure and production method thereof |
| CN106024873A (en) * | 2016-05-20 | 2016-10-12 | 电子科技大学 | Transverse IGBT |
| CN106024873B (en) * | 2016-05-20 | 2018-10-26 | 电子科技大学 | A kind of transversal I GBT |
| CN111370310A (en) * | 2018-12-26 | 2020-07-03 | 中芯集成电路（宁波）有限公司 | Semiconductor structure and forming method thereof |
| CN111370310B (en) * | 2018-12-26 | 2022-10-18 | 中芯集成电路（宁波）有限公司 | Semiconductor structure and forming method thereof |
| CN109801962A (en) * | 2019-01-23 | 2019-05-24 | 电子科技大学 | A kind of double grid control Sampling device based on LIGBT |
| CN109801962B (en) * | 2019-01-23 | 2020-11-13 | 电子科技大学 | Double-gate control sampling device based on LIGBT |
| CN111952368A (en) * | 2019-05-17 | 2020-11-17 | 宁波宝芯源功率半导体有限公司 | SOI (silicon on insulator) transverse LDMOS (laterally diffused metal oxide semiconductor) device with super junction structure and manufacturing method |
| CN111952351A (en) * | 2019-05-17 | 2020-11-17 | 宁波宝芯源功率半导体有限公司 | SOI (silicon on insulator) transverse LDMOS (laterally diffused metal oxide semiconductor) device with super junction structure and manufacturing method |
| CN113823694A (en) * | 2021-08-19 | 2021-12-21 | 电子科技大学 | Integrated submicron super junction lateral power semiconductor device and manufacturing method thereof |
| CN113823694B (en) * | 2021-08-19 | 2023-10-31 | 电子科技大学 | Lateral power semiconductor device integrated with submicron super junction and manufacturing method thereof |
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