CN111952351A - SOI (silicon on insulator) transverse LDMOS (laterally diffused metal oxide semiconductor) device with super junction structure and manufacturing method - Google Patents
SOI (silicon on insulator) transverse LDMOS (laterally diffused metal oxide semiconductor) device with super junction structure and manufacturing method Download PDFInfo
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- 229910044991 metal oxide Inorganic materials 0.000 title description 3
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- 238000000034 method Methods 0.000 claims description 22
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 11
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 10
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Abstract
The invention provides an SOI transverse LDMOS device with a super junction structure and a manufacturing method thereof, wherein the device comprises: a graphic SOI substrate, wherein an insulating layer of the graphic SOI substrate is provided with a window, and an N-type epitaxial layer and an N-type connecting region are arranged in the window; an N-type body region; the super-junction structure is arranged on one side and is transversely connected with the N-type body region, and the super-junction structure comprises a stacked N-type super-junction body region and a stacked P-type super-junction body region; the P-type body region is connected to the other side of the super junction structure; a P-type source region; an N-type heavily doped substrate contact region; the P-type drain region is formed in the P-type body region; a field oxide layer formed in the P-type super junction body region; the gate oxide layer spans between the P-type source region and the P-type super-junction body region; and the gate electrode layer is formed on the gate oxide layer. The super junction structure can effectively reduce the on-resistance of the device and reduce the surface electric field of the device. The field oxide layer can enable the breakdown voltage of the device to be located in the substrate, and the breakdown voltage reduction caused by overlarge surface electric field of the device is prevented.
Description
Technical Field
The invention belongs to the field of semiconductor integrated circuit manufacturing, and particularly relates to an SOI (silicon on insulator) transverse LDMOS (laterally diffused metal oxide semiconductor) device with a super junction structure and a manufacturing method thereof.
Background
Compared with the conventional LDMOS, the SOI technology has the advantages of high speed, low power consumption, high integration, extremely small parasitic effect, good isolation characteristic and the like, weakens the latch-up effect, has strong radiation resistance, greatly improves the reliability and soft error resistance of the integrated circuit, and gradually becomes the mainstream technology for manufacturing the integrated circuit with high speed, low power consumption, high integration and high reliability.
According to the general theory of SOI Dielectric Field enhancement (EPDIF for short), the adoption of the ultrathin top silicon layer can improve the longitudinal withstand voltage of an SOI device, but also leads to larger specific on-resistance.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an SOI lateral LDMOS device with a super junction structure and a manufacturing method thereof, so as to reduce the specific on-resistance of the device while maintaining a higher breakdown voltage of the device.
To achieve the above and other related objects, the present invention provides an SOI lateral LDMOS device having a super junction structure, the device comprising: the pattern SOI substrate comprises a P-type silicon substrate, an insulating layer and a top silicon layer which are sequentially stacked, wherein a window is arranged in the insulating layer, an N-type connecting area is formed in the P-type silicon substrate at the bottom of the window, an N-type epitaxial layer is filled in the window, and the N-type epitaxial layer is connected with the P-type silicon substrate and the top silicon layer; the N-type body region is formed in the top silicon layer on the N-type epitaxial layer; the super junction structure is formed in the top silicon layer, one side of the super junction structure is transversely connected with the N-type body region, and the super junction structure comprises an N-type super junction body region and a P-type super junction body region which are stacked; the P-type body region is formed in the top silicon layer and connected to the other side of the super junction structure; the P-type source region is formed in the N-type body region; an N-type heavily doped substrate contact region formed in the N-type body region; the P-type drain region is formed in the P-type body region; a field oxide layer formed in the P-type super junction body region; the gate oxide layer spans between the P-type source region and the P-type super junction body region; and the gate electrode layer is formed on the gate oxide layer.
Optionally, the gate oxide layer further spans over the field oxide layer to form an overlapping region with the field oxide layer, and the width of the overlapping region is between 1/4-3/4 of the width of the field oxide layer.
Optionally, the thickness of the field oxide layer is smaller than the depth of the P-type super junction region, the field oxide layer comprises a locos field oxide layer or an STI field oxide layer, the thickness range of the field oxide layer is 3000 angstroms to 5000 angstroms, and the width of the field oxide layer is 1 micron to 2 microns.
Optionally, the implanted ions of the N-type super junction region comprise phosphorus, and the ion implantation dosage is 1-5E 13/cm2The implanted ions of the P-type super junction region comprise boron, and the ion implantation dosage is 1-3E 13/cm2。
Optionally, the withstand voltage of the device is between 50V and 300V, and the on-resistance is not more than 200mohm mm2。
The invention also provides a manufacturing method of the SOI transverse LDMOS device with the super junction structure, which comprises the following steps: 1) providing a P-type silicon substrate, and forming an insulating layer on the P-type silicon substrate; 2) etching a window in the insulating layer; 3) forming an N-type connecting region in the P-type substrate at the bottom of the window, forming a P-type epitaxial layer in the window, and forming a top silicon layer on the insulating layer; 4) forming a field oxide layer in the top silicon layer; 5) enabling the P-type epitaxial layer to be inverted into an N-type epitaxial layer through a photoetching process and an ion implantation process, and respectively forming an N-type body region, a super-junction structure and a P-type body region in the top silicon layer, wherein the N-type body region is formed on the N-type epitaxial layer, the N-type body region is transversely connected with one side of the super-junction structure, the other side of the super-junction structure is connected with the P-type body region, and the super-junction structure comprises the stacked N-type super-junction body region and the stacked P-type super-junction body region; 6) forming a gate oxide layer and a gate layer, wherein the gate oxide layer spans between the N-type body region and the P-type super-junction body region, and the gate layer is positioned on the gate oxide layer; 7) and forming a P-type source region, a P-type drain region and an N-type heavily doped substrate contact region, wherein the P-type source region is formed in the N-type body region, the P-type drain region is formed in the P-type body region, and the N-type heavily doped substrate contact region is formed in the N-type body region.
Optionally, in the step 1), an insulating layer is formed on the N-type substrate by using a thermal oxidation process, the thickness of the insulating layer is between 0.5 and 2 micrometers, the thickness of the top silicon layer formed in the step 3) is between 3 and 10 micrometers, and the top silicon layer is doped in an N-type manner.
Optionally, the thickness of the field oxide layer is smaller than the depth of the P-type super junction region, the field oxide layer comprises a locos field oxide layer or an STI field oxide layer, the thickness range of the field oxide layer is 3000 angstroms to 5000 angstroms, and the width of the field oxide layer is 1 micron to 2 microns.
Optionally, the implanted ions of the N-type super junction region comprise phosphorus, the ion implantation energy is between 1000ev and 3000ev, and the ion implantation dosage is between 1 and 5E13cm2The implanted ions of the P-type super junction zone comprise boron, the ion implantation energy is between 200keV and 500keV, and the ion implantation dosage is between 1 and 3E13/cm2In the meantime.
Optionally, the gate oxide layer further spans over the field oxide layer to form an overlapping region with the field oxide layer, and the width of the overlapping region is between 1/4-3/4 of the width of the field oxide layer.
Optionally, the withstand voltage of the device is between 50V and 300V, and the on-resistance is not more than 200mohm mm2。
As described above, the SOI lateral LDMOS device with a super junction structure and the manufacturing method of the present invention have the following beneficial effects:
according to the invention, the super junction structure is formed on the SOI substrate, and the super junction structure can improve the doping concentration of the P-type super junction body region (as a drift region of the LDMOS), so that the on-resistance of the device can be effectively reduced, and the surface electric field of the device can be effectively reduced through the charge balance of the N-type super junction body region.
The field oxide layer is arranged at the drain end, so that the breakdown voltage of the device can be positioned in the substrate by the field oxide layer, and the reduction of the breakdown voltage caused by the overlarge electric field on the surface of the device is prevented.
The invention can effectively reduce the on-resistance of the device and solve the contradiction between the on-resistance and the breakdown voltage of the traditional SOI device.
Drawings
Fig. 1 to 9 show structural schematic diagrams presented in steps of a method for manufacturing an SOI lateral LDMOS device having a super junction structure according to an embodiment of the present invention, where fig. 9 shows a structural schematic diagram of an SOI lateral LDMOS device having a super junction structure according to an embodiment of the present invention.
Description of the element reference numerals
101P type silicon substrate
102 insulating layer
103 window
104N type epitaxial layer
105 top silicon layer
106 field oxide layer
107N type body region
108N type super junction body region
109P-type super junction body region
110P type body region
111 gate oxide layer
112 gate layer
113P type source region
114N type heavily doped substrate contact region
115P-type drain region
116 source contact electrode
117 body contact electrode
118 drain contact electrode
119 gate contact electrode
120N type connection region
121N type epitaxial layer
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 8, the present embodiment provides an SOI lateral LDMOS high-voltage device having a super junction structure, the high-voltage device including: the structure comprises a patterned SOI substrate, an N-type body region 107, a super junction structure, a P-type body region 110, a P-type source region 113, an N-type heavily doped substrate contact region 114, a P-type drain region 115, a field oxide layer 106, a gate oxide layer 111, a gate layer 112 and the like.
The graphic SOI substrate comprises a P-type silicon substrate 101, an insulating layer 102 and a top silicon layer 105 which are sequentially stacked, wherein a window 103 is arranged in the insulating layer 102, an N-type connecting region is formed in the P-type silicon substrate at the bottom of the window 103, an N-type epitaxial layer 104 is filled in the window 103, and the N-type epitaxial layer 104 is connected with the P-type silicon substrate 101 and the top silicon layer 105, so that the occurrence of a floating body effect and the like of the SOI substrate can be avoided, and the parasitic capacitance and the electric leakage of a device are reduced.
The N-type body regions 107 are formed in the top silicon layer on the N-type epitaxial layer 104. The implanted ions of the N-type body region 107 comprise phosphorus with an implant dose of 1-3E 12/cm2In the meantime.
The super junction structure is formed in the top silicon layer, one side of the super junction structure is transversely connected with the N-type body region 107, and the super junction structure comprises an N-type super junction body region 108 and a P-type super junction body region 109 which are arranged in an up-and-down stacked mode. The implanted ions of the N-type super junction region 108 comprise phosphorus, and the ion implantation dosage is 1-5E 13/cm2The implanted ions of the P-type super junction region 109 comprise boron, and the ion implantation dosage is 1-3E 13/cm2. According to the invention, the super junction structure is formed on the SOI substrate, and the super junction structure can improve the doping concentration of the P-type super junction body region 109 (as a drift region of the LDMOS), so that the on-resistance of the device can be effectively reduced, and the surface electric field of the device can be effectively reduced.
The P-type body region 110 is formed in the top silicon layer and connected to the other side of the super junction structure. The implanted ions of the P-type body region 110 can be boron, and the ion implantation dosage can be 1-5E 13/cm2In the meantime.
The P-type source regions 113 are formed in the N-type body region 107. The implanted ions of the P-type source region 113 may be boron, and the ion implantation dose may be 4-6E 15/cm2In the meantime.
The N-type heavily doped substrate contact region 114 is formed in the N-type body region 107. The implanted ions in the N-type heavily doped substrate contact region 114 may be arsenic, and the ion implantation dose may be 1-5E 15/cm2And the like.
The P-type drain region 115 is formed in the P-type body region 110. The implanted ions of the P-type drain region 115 can be boron, and the ion implantation dosage can be 4-6E 15/cm2In the meantime.
The field oxide layer 106 is formed in the P-type super junction body region 109 with a space to the N-type body region 107. The thickness of field oxide 106 is less than the depth of P type super junction region 109, for example, the thickness of field oxide 106 can be between 1/2 ~ 3/4 of the depth of P type super junction region 109, in this embodiment, field oxide 106 can be locos field oxide 106 or STI field oxide 106, locos field oxide 106 passes through the local oxidation formation of silicon, STI field oxide 106 can form the slot earlier, then adopts HDP deposition technology to fill silicon dioxide layer and forms, the thickness range of field oxide 106 is between 3000 angstroms ~ 5000 angstroms, and the width is between 1 micron ~ 2 microns. The field oxide layer 106 is arranged at the drain end, and the field oxide layer 106 can enable the breakdown voltage of the device to be located in the substrate, so that the breakdown voltage reduction caused by the overlarge electric field on the surface of the device is prevented.
The gate oxide layer 111 spans between the P-type source region 113 and the P-type super junction region 109, and the gate layer 112 is formed on the gate oxide layer 111. As shown in fig. 8, the gate oxide layer 111 further spans over the field oxide layer 106 to have an overlapping region with the field oxide layer 106, the width of the overlapping region is between 1/4-3/4 of the width of the field oxide layer 106, for example, the width of the overlapping region may be 1/2 of the width of the field oxide layer 106.
As shown in fig. 8, the SOI lateral LDMOS high voltage device with the super junction structure further includes an isolation layer (not shown) covering the device surface, and a body contact hole and body contact electrode 117, a source contact hole and source contact electrode 116, a gate contact hole and gate contact electrode 119, and a drain contact hole and drain contact electrode 118 formed in the isolation layer, wherein the body contact electrode 117 is connected to the N-type heavily doped substrate contact region 114, the source contact electrode 116 is connected to the P-type source region 113, the gate contact electrode 119 is connected to the gate layer 112, and the drain contact electrode 118 is connected to the P-type drain region 115.
The voltage resistance of the SOI transverse LDMOS high-voltage device with the super junction structure is between 50V and 300V, and the on-resistance is not more than200mohm*mm2The LDMOS device has ultralow on-resistance under the condition of the same breakdown voltage, is compatible with the traditional CMOS process, and has the on-resistance of about 900mohm mm as the same 60V device2The on-resistance of the device is only 80mohm mm2。
As shown in fig. 1 to fig. 8, this embodiment further provides a method for manufacturing an SOI lateral LDMOS high-voltage device with a super junction structure, where the method includes the steps of:
as shown in fig. 1, step 1) is performed to provide a P-type silicon substrate 101, and an insulating layer 102 is formed on the P-type silicon substrate 101.
For example, a thermal oxidation process may be used to form the insulating layer 102 on the N-type substrate, the material of the insulating layer 102 is silicon dioxide, the thickness of the insulating layer 102 is between 0.5 microns and 2 microns,
as shown in fig. 2, step 2) is then performed, a window 103 is etched in the insulating layer 102 by using a photolithography process and a dry etching process, and the window 103 penetrates through the insulating layer 102.
As shown in fig. 3 to 4, step 3) is performed to form an N-type connection region 120 in the P-type substrate at the bottom of the window 103, form a P-type epitaxial layer 104 in the window 103, and form a top silicon layer 105 on the insulating layer 102.
For example, the N-type connection region 120 can be formed in the P-type substrate at the bottom of the window 103 by photolithography and ion implantation, wherein the implanted ions can be phosphorus, the implantation energy can be 700keV to 1000keV, and the implantation dose can be 1 to 3E12/cm2And then removing the photoresist and then carrying out rapid annealing to activate doping, wherein the annealing temperature can be 900-1000 ℃, and the annealing time can be 8-12 seconds.
An epitaxial growth process may be employed to form a P-type epitaxial layer 104 in the window 103, and form a top silicon layer 105 on the insulating layer 102, where the thickness of the formed top silicon layer 105 is between 3 micrometers and 10 micrometers, and the top silicon layer 105 is P-type doped.
As shown in fig. 5, step 4) is performed to form a field oxide layer 106 in the top silicon layer 105.
The thickness of field oxide 106 is less than the depth of P type super junction region 109, for example, the thickness of field oxide 106 can be between 1/2 ~ 3/4 of the depth of P type super junction region 109, in this embodiment, field oxide 106 can be locos field oxide 106 or STI field oxide 106, locos field oxide 106 passes through the local oxidation formation of silicon, STI field oxide 106 can form the slot earlier, then adopts HDP deposition technology to fill silicon dioxide layer and forms, the thickness range of field oxide 106 is between 3000 angstroms ~ 5000 angstroms, and the width is between 1 micron ~ 2 microns.
The field oxide layer 106 is arranged at the drain end, and the field oxide layer 106 can enable the breakdown voltage of the device to be located in the substrate, so that the breakdown voltage reduction caused by the overlarge electric field on the surface of the device is prevented.
As shown in fig. 6, step 5) is performed, the P-type epitaxial layer 104 is inverted into an N-type epitaxial layer 121 through a photolithography process and an ion implantation process, and an N-type body region 107, a super junction structure and a P-type body region 110 are respectively formed in the top silicon layer 105, wherein the N-type body region 107 is formed on the N-type epitaxial layer 104, the N-type body region 107 is laterally connected to one side of the super junction structure, and the P-type body region 110 is connected to the other side of the super junction structure, and the super junction structure includes an N-type super junction body region 108 and a P-type super junction body region 109 which are stacked.
The implanted ions of the N-type super junction region 108 comprise phosphorus, the ion implantation energy is between 1000ev and 3000ev, and the ion implantation dosage is between 1E 13cm and 5E13cm2The implanted ions of the P-type super junction region 109 comprise boron, the ion implantation energy is 200 keV-500 keV, and the ion implantation dosage is 1-3E 13/cm2In the meantime.
The implanted ions of the N-type body region 107 comprise phosphorus, the ion implantation energy is 500eV to 1500eV, and the implantation dosage is 1E 12/cm to 3E12/cm2Meanwhile, the P-type epitaxial layer 104 is inverted into an N-type epitaxial layer 121.
The implanted ions of the P-type body region 110 may be boron, the ion implantation energy may be 1500keV to 2500keV, and the ion implantation dose may be1～5E13/cm2In the meantime.
In this embodiment, a window 103 is formed in the insulating layer 102, the window 103 is filled with an N-type epitaxial layer 121, and the N-type epitaxial layer 104 is connected to the P-type silicon substrate 101 and the top silicon layer 105 through the N-type connection region 120, so that a floating body effect of an SOI substrate can be avoided, and parasitic capacitance and leakage of a device can be reduced.
According to the invention, the super junction structure is formed on the SOI substrate, and the super junction structure can improve the doping concentration of the P-type super junction body region 109 (as a drift region of the LDMOS), so that the on-resistance of the device can be effectively reduced, and the surface electric field of the device can be effectively reduced.
As shown in fig. 7, step 6) is then performed, a gate oxide layer 111 is formed by a thermal oxidation process or the like, and a gate layer 112 is formed by a deposition process or the like, the gate oxide layer 111 straddling between the N-type body region 107 and the P-type super junction body region 109, and the gate layer 112 is located on the gate oxide layer 111.
The thickness of the gate oxide layer 111 can be 100-200 angstroms, the gate layer 112 can be P-type polysilicon, and the thickness of the gate layer 112 can be 2000-3000 angstroms.
As shown in fig. 8, step 7) is performed to form a P-type source region 113, a P-type drain region 115 and an N-type heavily doped substrate contact region 114, wherein the P-type source region 113 is formed in the N-type body region 107, the P-type drain region 115 is formed in the P-type body region 110, and the N-type heavily doped substrate contact region 114 is formed in the N-type body region 107.
The P-type source regions 113 are formed in the N-type body region 107. The implanted ions of the P-type source region 113 may be boron, the ion implantation energy may be 5keV to 10keV, and the ion implantation dose may be 4 to 6E15/cm2In the meantime.
The N-type heavily doped substrate contact region 114 is formedIn the N-type body region 107. The implanted ions in the N-type heavily doped substrate contact region 114 can be arsenic, the ion implantation energy is 60keV, and the ion implantation dosage can be 1-5E 15/cm2And the like.
The P-type drain region 115 is formed in the P-type body region 110. The implanted ions of the P-type drain region 115 can be phosphorus, the ion implantation energy can be 5keV to 10keV, and the ion implantation dosage can be 4 to 6E15/cm2In the meantime.
As shown in fig. 9, step 8) is finally performed to cover a device isolation layer (not shown) on the surface of the SOI lateral LDMOS high-voltage device with the super junction structure, and form a body contact hole and body contact electrode 117, a source contact hole and source contact electrode 116, a gate contact hole and gate contact electrode 119, and a drain contact hole and drain contact electrode 118 in the isolation layer, where the body contact electrode 117 is connected to the N-type heavily doped substrate contact region 114, the source contact electrode 116 is connected to the P-type source region 113, the gate contact electrode 119 is connected to the gate layer 112, and the drain contact electrode 118 is connected to the P-type drain region 115.
The voltage resistance of the SOI transverse LDMOS high-voltage device with the super junction structure is between 50V and 300V, and the on-resistance is not more than 200mohm mm2The LDMOS device has ultralow on-resistance under the condition of the same breakdown voltage, is compatible with the traditional CMOS process, and has the on-resistance of about 900mohm mm as the same 60V device2The on-resistance of the device is only 80mohm mm2。
As described above, the SOI lateral LDMOS high-voltage device with super junction structure and the manufacturing method of the present invention have the following features
Has the advantages that:
according to the invention, the super junction structure is formed on the SOI substrate, and the super junction structure can improve the doping concentration of the P-type super junction body region 109 (as a drift region of the LDMOS), so that the on-resistance of the device can be effectively reduced, and the surface electric field of the device can be effectively reduced through the charge balance of the N-type super junction body region.
The field oxide layer 106 is arranged at the drain end, and the field oxide layer 106 can enable the breakdown voltage of the device to be located in the substrate, so that the breakdown voltage reduction caused by the overlarge electric field on the surface of the device is prevented.
The invention can effectively reduce the on-resistance of the device and solve the contradiction between the on-resistance and the breakdown voltage of the traditional SOI device.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (11)
1. An SOI lateral LDMOS device having a super junction structure, the device comprising:
the pattern SOI substrate comprises a P-type silicon substrate, an insulating layer and a top silicon layer which are sequentially stacked, wherein a window is arranged in the insulating layer, an N-type connecting area is formed in the P-type silicon substrate at the bottom of the window, an N-type epitaxial layer is filled in the window, and the N-type epitaxial layer is connected with the P-type silicon substrate and the top silicon layer;
the N-type body region is formed in the top silicon layer on the N-type epitaxial layer;
the super junction structure is formed in the top silicon layer, one side of the super junction structure is transversely connected with the N-type body region, and the super junction structure comprises an N-type super junction body region and a P-type super junction body region which are stacked;
the P-type body region is formed in the top silicon layer and connected to the other side of the super junction structure;
the P-type source region is formed in the N-type body region;
an N-type heavily doped substrate contact region formed in the N-type body region;
the P-type drain region is formed in the P-type body region;
a field oxide layer formed in the P-type super junction body region;
the gate oxide layer spans between the P-type source region and the P-type super junction body region;
and the gate electrode layer is formed on the gate oxide layer.
2. The SOI lateral LDMOS device having a super junction structure of claim 1, wherein: the gate oxide still span on the field oxide with the field oxide has the overlap region, the width of overlap region is in between 1/4 ~ 3/4 of field oxide width.
3. The SOI lateral LDMOS device having a super junction structure of claim 1, wherein: the thickness of field oxide is less than the degree of depth in P type super junction body region, field oxide includes locos field oxide or STI field oxide, field oxide's thickness range is 3000 angstroms ~ 5000 angstroms, and the width is between 1 micron ~ 2 microns.
4. The SOI lateral LDMOS device having a super junction structure of claim 1, wherein: the implanted ions of the N-type super junction region comprise phosphorus, and the ion implantation dosage is 1-5E 13/cm2The implanted ions of the P-type super junction region comprise boron, and the ion implantation dosage is 1-3E 13/cm2。
5. The SOI lateral LDMOS device having a super junction structure of claim 1, wherein: the voltage resistance of the device is between 50V and 300V, and the on-resistance is not more than 200mohm mm2。
6. A manufacturing method of an SOI lateral LDMOS device with a super junction structure is characterized by comprising the following steps:
1) providing a P-type silicon substrate, and forming an insulating layer on the P-type silicon substrate;
2) etching a window in the insulating layer;
3) forming an N-type connecting region in the P-type substrate at the bottom of the window, forming a P-type epitaxial layer in the window, and forming a top silicon layer on the insulating layer;
4) forming a field oxide layer in the top silicon layer;
5) enabling the P-type epitaxial layer to be inverted into an N-type epitaxial layer through a photoetching process and an ion implantation process, and respectively forming an N-type body region, a super-junction structure and a P-type body region in the top silicon layer, wherein the N-type body region is formed on the N-type epitaxial layer, the N-type body region is transversely connected with one side of the super-junction structure, the other side of the super-junction structure is connected with the P-type body region, and the super-junction structure comprises the stacked N-type super-junction body region and the stacked P-type super-junction body region;
6) forming a gate oxide layer and a gate layer, wherein the gate oxide layer spans between the N-type body region and the P-type super-junction body region, and the gate layer is positioned on the gate oxide layer;
7) and forming a P-type source region, a P-type drain region and an N-type heavily doped substrate contact region, wherein the P-type source region is formed in the N-type body region, the P-type drain region is formed in the P-type body region, and the N-type heavily doped substrate contact region is formed in the N-type body region.
7. The method for manufacturing the SOI lateral LDMOS device with the super junction structure according to claim 6, wherein: step 1) forming an insulating layer on the N-type substrate by adopting a thermal oxidation process, wherein the thickness of the insulating layer is between 0.5 and 2 microns, the thickness of the top silicon layer formed in step 3) is between 3 and 10 microns, and the top silicon layer is doped in an N type.
8. The method for manufacturing the SOI lateral LDMOS device with the super junction structure according to claim 6, wherein: the thickness of field oxide is less than the degree of depth in P type super junction body region, field oxide includes locos field oxide or STI field oxide, field oxide's thickness range is 3000 angstroms ~ 5000 angstroms, and the width is between 1 micron ~ 2 microns.
9. The SOI lateral LDMOS device having a super junction structure of claim 6The manufacturing method is characterized in that: the implanted ions of the N-type super junction region comprise phosphorus, the ion implantation energy is between 1000ev and 3000ev, and the ion implantation dosage is between 1 and 5E13cm2The implanted ions of the P-type super junction zone comprise boron, the ion implantation energy is between 200keV and 500keV, and the ion implantation dosage is between 1 and 3E13/cm2In the meantime.
10. The method for manufacturing the SOI lateral LDMOS device with the super junction structure according to claim 6, wherein: the gate oxide still span on the field oxide with the field oxide has the overlap region, the width of overlap region is in between 1/4 ~ 3/4 of field oxide width.
11. The method for manufacturing the SOI lateral LDMOS device with the super junction structure according to claim 6, wherein: the voltage resistance of the device is between 50V and 300V, and the on-resistance is not more than 200mohm mm2。
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| CN104701381A (en) * | 2015-03-03 | 2015-06-10 | 南京邮电大学 | Two-dimensional SJ/RESURF LDMOS apparatus with step doping in P column region and manufacturing method thereof |
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| US20120032262A1 (en) * | 2010-08-05 | 2012-02-09 | Laas-Cnrs | Enhanced hvpmos |
| CN102751316A (en) * | 2012-07-31 | 2012-10-24 | 电子科技大学 | Transverse signal operation instruction (SOI) power device |
| CN104701381A (en) * | 2015-03-03 | 2015-06-10 | 南京邮电大学 | Two-dimensional SJ/RESURF LDMOS apparatus with step doping in P column region and manufacturing method thereof |
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