CN109801962B - A Dual-gate Controlled Sampling Device Based on LIGBT - Google Patents

Abstract

The present invention provides a dual-gate control sampling device based on LIGBT. Impurity region, first conductivity type semiconductor anode region, second metal electrode, first conductivity type semiconductor body region, oxide layer, metal gate, first conductivity type semiconductor body region, second conductivity type semiconductor cathode region, first The second conductivity type semiconductor doped region, the first conductivity type semiconductor doped region, the second second conductivity type semiconductor doped region, the first conductivity type semiconductor cathode region, the third metal electrode, the fourth metal electrode, the fifth Metal electrode, first metal electrode, the device can sample the current flowing through the device in the on state, and the anode voltage can be detected in the off transient state. The current sampling and voltage sampling are alternately performed, and the sampling accuracy is high, and the sampling ratio Controllable.

Description

A Dual-gate Controlled Sampling Device Based on LIGBT

technical field

The invention belongs to the technical field of power semiconductor devices, and relates to an LIGBT-based dual-gate control sampling device.

Background technique

In the high-voltage and power integrated circuits and systems related to power drive, it is necessary to detect the input/output performance and load conditions of the high-voltage and power integrated circuits, so as to achieve real-time protection of the circuits and systems, and meet the intelligence of the integrated circuits and systems. It can effectively ensure the normal and reliable operation of the system. Realizing the control of high voltage, power integrated circuits and their application systems is a research hotspot and a scientific difficulty at home and abroad.

Power semiconductor devices face many failure situations in practical applications, such as short-circuit events and transient current peak overshoot under inductive loads, etc. The damage of the device in a single module will directly affect the reliability and stability of the circuit system. An effective method for stability is to directly measure the voltage and current of the devices in the power module and provide feedback in time. Traditional sampling technology is mainly realized through peripheral components, such as secondary feedback sampling, resistance, current mirror sampling and other methods. These methods will bring disadvantages such as unadjustable signal sampling, insufficient sampling accuracy, increased production cost, and large application circuit volume. , At present, researchers have begun to study the sampling technology inside the chip to overcome the above shortcomings, including voltage sampling, current sampling, temperature sampling and so on.

In terms of current sampling, others have proposed the JFET sampling structure. As shown in Figure 1, the JFET sampling device has the advantages of simple structure, high sampling accuracy, and can be used as a multiplexing device for sampling and self-power supply. In low-voltage applications, JFET sampling devices with traditional structures are already competent for related applications, but in high-voltage applications, conventional JFET sampling devices are difficult to meet the application requirements. First, the device withstand voltage is not enough, considering all aspects of the design. It is difficult to design and improve the withstand voltage; secondly, the back gate of JFET is grounded or fixed potential, the depth of the sampling current drift region is determined, and it cannot be adjusted during application, that is, the sampling is uncontrollable; finally, the constant current characteristic in the saturation region is poor. , non-constant current charging will cause the self-supply voltage to be unstable, thus affecting the normal operation of the chip. However, this structure is not suitable for high pressure applications.

In view of the shortcomings of traditional JFET sampling devices, others have proposed the SenseFET structure shown in Figure 2, which has better performance in current sampling: high voltage blocking capability (can reach 700V), sampling current has a controllable The device can realize the controllability of the sampling current through the gate control during the turn-on period, and can realize the self-power supply of the chip during the turn-off period. In addition, the SenseFET has better saturation region constant current characteristics than conventional JFET sampling devices when operating in the saturation region. However, this structure cannot have the functions of current sampling and voltage sampling at the same time, and cannot fully meet the requirements of high-voltage applications.

SUMMARY OF THE INVENTION

The purpose of the present invention is to propose a dual-gate control sampling device based on LIGBT in view of the problems existing in the above-mentioned sampling inside the chip.

In order to realize the above-mentioned purpose of the invention, the technical scheme of the present invention is as follows:

A dual-gate control sampling device based on LIGBT, its cell structure includes a first conductive type semiconductor substrate 1 and a substrate metal electrode 19 located on the lower surface of the first conductive type semiconductor substrate 1; the first conductive type semiconductor substrate 1 is provided. The upper surface of the substrate 1 has an epitaxial oxide layer 2; the upper surface of the epitaxial oxide layer 2 has a second conductive type semiconductor drift region 3; the second conductive type semiconductor drift region 3 has a second conductive type semiconductor doped region 4 ; The second conductive type semiconductor doped region 4 has a first conductive type semiconductor anode region 5, and the upper surface of the first conductive type semiconductor anode region 5 has a second metal electrode 11; the second conductive type semiconductor drift The region 3 has a first conductive type semiconductor body region 13; the upper surface of the first conductive type semiconductor body region 13 has an oxide layer 12; the oxide layer 12 has a metal gate 14; the second conductive type semiconductor drift The right side of the region 3 has a first conductivity type semiconductor body region 18; the first conductivity type semiconductor body region 18 has a second conductivity type semiconductor cathode region 6, and the right side of the second conductivity type semiconductor cathode region 6 is from left to right The first second conductivity type semiconductor doped region 7, the first conductivity type semiconductor doped region 8, the second second conductivity type semiconductor doped region 7, and the first conductivity type semiconductor cathode region 9 are arranged in sequence; There is a gap between the first type semiconductor cathode region 6 and the first second conductivity type semiconductor doped region 7, the first second conductivity type semiconductor doped region 7, the first conductivity type semiconductor doped region 8, the second The second conductive type semiconductor doped regions 7 are arranged adjacent to each other, the upper surface of the second conductive type semiconductor cathode region 6 has a third metal electrode 15 ; the upper surface of the second conductive type semiconductor doped region 7 has a fourth metal electrode 15 . Metal electrode 16 ; the upper surface of the first conductive type semiconductor doped region 8 has a fifth metal electrode 17 , and the upper surface of the first conductive type semiconductor cathode region 9 has a first metal electrode 10 .

As a preferred embodiment, the first conductivity type semiconductor is a P-type semiconductor, and the second conductivity type semiconductor is an N-type semiconductor.

As a preferred embodiment, the first conductivity type semiconductor is an N-type semiconductor, and the second conductivity type semiconductor is a P-type semiconductor.

As a preferred manner, the first conductivity type semiconductor or the second conductivity type semiconductor is single crystal silicon, silicon carbide or gallium nitride.

The beneficial effects of the invention are as follows: the device can sample the current flowing through the device in the on state, the anode voltage can be detected in the off transient state, the current sampling and the voltage sampling are alternately performed, and the sampling accuracy is high, and the sampling ratio can be adjusted. control.

Description of drawings

Figure 1 is a schematic diagram of a conventional JFET sampling structure;

Figure 2 is a schematic diagram of the SenseFET sampling structure;

3 is a two-dimensional structural schematic diagram of a LIGBT-based dual-gate control sampling device of the present invention;

4 is a three-dimensional schematic diagram of a LIGBT-based dual-gate control sampling device of the present invention;

Fig. 5 is the sampling schematic diagram of two-dimensional device structure;

Fig. 6 is the variation of the electrical parameters of each electrode in the on-state and off-state transients of the device simulated and intercepted by means of the simulator;

7 is a schematic diagram of the current sampling characteristics of the LIGBT-based sampling device of the present invention;

8 is a schematic diagram of the voltage sampling characteristics of the LIGBT-based sampling device of the present invention;

1 is the first conductive type semiconductor substrate, 2 is the epitaxial oxide layer, 3 is the second conductive type semiconductor drift region, 4 is the second conductive type semiconductor doped region, 5 is the first conductive type semiconductor anode region, and 6 is the first conductive type semiconductor anode region. Two conductive type semiconductor cathode regions, 7 is the second conductive type semiconductor doped region, 8 is the first conductive type semiconductor doped region, 9 is the first conductive type semiconductor cathode region, 10 is the first metal electrode, 11 is the second conductive type Metal electrode, 12 is the oxide layer, 13 is the first conductive type semiconductor body region, 14 is the metal gate, 15 is the third metal electrode, 16 is the fourth metal electrode, 17 is the fifth metal electrode, 18 is the first conductive type semiconductor body region, 19 is the substrate metal electrode, 20 is the current sampling electrode, 21 is the second conductivity type semiconductor heavily doped region on the surface of the drift region, 22 is the first conductivity type semiconductor heavily doped region on the substrate surface, 23 is The first conductive type semiconductor body region, 24 is the first conductive type semiconductor heavily doped region, 25 is the gate metal electrode, and 26 is the polysilicon electrode.

Detailed ways

The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

An LIGBT-based dual-gate control sampling device of the present invention, as shown in FIG. 3 , has a cell structure including a first conductive type semiconductor substrate 1 and a substrate metal electrode located on the lower surface of the first conductive type semiconductor substrate 1 19; the upper surface of the first conductive type semiconductor substrate 1 has an epitaxial oxide layer 2; the upper surface of the epitaxial oxide layer 2 has a second conductive type semiconductor drift region 3; the second conductive type semiconductor drift region 3 has The second conductive type semiconductor doped region 4; the second conductive type semiconductor doped region 4 has a first conductive type semiconductor anode region 5, and the upper surface of the first conductive type semiconductor anode region 5 has a second metal electrode 11 ; The second conductive type semiconductor drift region 3 has a first conductive type semiconductor body region 13 ; the first conductive type semiconductor body region 13 has an oxide layer 12 on the upper surface; the oxide layer 12 has a metal gate 14 ; The right side of the second conductivity type semiconductor drift region 3 has a first conductivity type semiconductor body region 18; the first conductivity type semiconductor body region 18 has a second conductivity type semiconductor cathode region 6, the second conductivity type semiconductor body region 18 A first second conductivity type semiconductor doped region 7 , a first conductivity type semiconductor doped region 8 , a second second conductivity type semiconductor doped region 7 , a first conductivity type semiconductor doped region 7 and a first conductivity type semiconductor doped region 7 are arranged on the right side of the cathode region 6 in sequence from left to right. Type semiconductor cathode region 9; a gap is provided between the second conductivity type semiconductor cathode region 6 and the first second conductivity type semiconductor doped region 7, the first second conductivity type semiconductor doped region 7, the first conductivity type The semiconductor doped region 8 and the second second conductivity type semiconductor doped region 7 are arranged adjacently, and the second conductivity type semiconductor cathode region 6 has a third metal electrode 15 on the upper surface; the second conductivity type semiconductor The upper surface of the doped region 7 has a fourth metal electrode 16; the upper surface of the first conductive type semiconductor doped region 8 has a fifth metal electrode 17, and the upper surface of the first conductive type semiconductor cathode region 9 has a first metal electrode 10.

As a preferred embodiment, the first conductivity type semiconductor is a P-type semiconductor, and the second conductivity type semiconductor is an N-type semiconductor. Alternatively, the first conductivity type semiconductor is an N-type semiconductor, and the second conductivity type semiconductor is a P-type semiconductor.

As a preferred manner, the first conductivity type semiconductor or the second conductivity type semiconductor is single crystal silicon, silicon carbide or gallium nitride.

Next, take the sampling device of the P-type substrate as an example to illustrate the working principle of the present invention:

As shown in FIGS. 3 and 4 , based on the LIGBT structure, a second conductivity type semiconductor dopant is implanted between the second conductivity type semiconductor cathode region 6 and the first conductivity type semiconductor cathode region 9 in the first conductivity type semiconductor body region 18 . The impurity region 7, the second conductivity type semiconductor doped region 7 and the first conductivity type semiconductor doped region 8 at the cathode constitute a JFET structure. As shown in FIG. 5 , when the metal gate 14 is turned on, the current flows through the device from the second metal electrode 11 , the conductance modulation occurs in the second conductivity type semiconductor drift region 3 , and the current occurs in the first conductivity type semiconductor body region 18 . shunt, a part of the current flows through the cathode third metal electrode 15 and the first metal electrode 10, and a part of the current flows through the fifth metal electrode 17, so that the device can monitor the device current in the on state, when the second metal electrode 11 current When increasing, the sampling current of the fifth metal electrode 17 also increases. When a positive voltage is applied to the fourth metal electrode 16, the PN junction is reversely biased, the depletion region expands and the carrier path is narrowed, and the current value of the fifth metal electrode 17 will decrease, thereby realizing the controllability of current sampling .

When the metal gate 14 is turned off, the voltage of the second metal electrode 11 of the device rises rapidly. At this time, a large number of holes stored in the drift region 3 of the second conductivity type semiconductor during the forward conduction process will also When the metal electrode 10 and the fifth metal electrode 17 are released, the voltage of the fifth metal electrode 17 will rise for a short time, and the process of the voltage rise of the second metal electrode 11 and the voltage rise of the fifth metal electrode 17 are synchronized. Therefore, The device can monitor the voltage of the second metal electrode 11. When a positive voltage is applied to the fourth metal electrode 16, the PN junction is reversely biased, and the expansion of the depletion region causes the carrier path to narrow, and the current of the fifth metal electrode 17 value will be reduced, enabling controllability of voltage sampling.

In order to verify the beneficial results of the present invention, the device structure is simulated by Medici software, and the electrical parameters are simulated. The main parameters of the simulation are: the substrate doping concentration is 1.2e14cm ^-3 , the drift region doping concentration is 3e14cm ^-3 , the drift The region length is 60μm, the junction depth is 30μm, the doping concentration of the Pbody is 2e17cm ^-3 , and the junction depth of the shallow junction inside the Pbody is 0.5μm. The simulation results show that the new structure has high voltage blocking capability, the device breakdown voltage is 675V, and the threshold voltage is 3V. In the dynamic simulation, the voltage sampling terminal is connected to a 1Ω sampling resistor, the cathode is grounded, and the current flowing through the device is changed in the on state, and the current sampling image shown in Figure 7 is obtained. The control gate is 0V, and when the anode current increases , the sampling current of the sensing electrode also increases, and the sampling of the current changes linearly. As shown in Figure 6, the control gate is 0V. When the gate voltage drops and the device is in a turn-off transient state, the voltage of the sensing electrode will rise, and then fall back to 0V after reaching the peak value, and the process of the anode voltage rising is the same as The rising process of the sensing electrode voltage is synchronous, so the device can monitor the electrode voltage. Figure 8 shows the change image of the sensing electrode voltage following the anode voltage.

Among the structural parameters of the device, the structural parameters such as the length L, width W and doping concentration N of the P-type shallow junction will also affect the sampling voltage. The larger the sampling current and sampling voltage values are.

To sum up, the present invention provides a dual-gate control sampling device based on LIGBT. Through the built-in sampling structure of the Pbody, the device can alternately sample current and voltage, and the existence of the control gate can realize sampling voltage and current. controllability.

The above-mentioned embodiments merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed in the present invention should still be covered by the claims of the present invention.

Claims (4)

1. A double-gate control sampling device based on LIGBT comprises a first conductive type semiconductor substrate (1) and a substrate metal electrode (19) positioned on the lower surface of the first conductive type semiconductor substrate (1); the upper surface of the first conductive type semiconductor substrate (1) is provided with an epitaxial oxide layer (2); the upper surface of the epitaxial oxide layer (2) is provided with a second conductive type semiconductor drift region (3); the second conduction type semiconductor drift region (3) is provided with a second conduction type semiconductor doping region (4) on the left side and a first conduction type semiconductor body region (13) in the middle, the second conduction type semiconductor doping region (4) is provided with a first conduction type semiconductor anode region (5), and the upper surface of the first conduction type semiconductor anode region (5) is provided with a second metal electrode (11); the second conductivity type semiconductor drift region (3) has a first conductivity type semiconductor body region (13) therein; the upper surface of the first conduction type semiconductor body (13) is provided with an oxide layer (12); the oxide layer (12) is provided with a metal grid (14); the middle right side of the second conduction type semiconductor drift region (3) is provided with a second first conduction type semiconductor body region (18); the method is characterized in that: the second first conduction type semiconductor body region (18) is internally provided with a second conduction type semiconductor cathode region (6), and a first second conduction type semiconductor doped region (7), a first conduction type semiconductor doped region (8), a second conduction type semiconductor doped region (7) and a first conduction type semiconductor cathode region (9) are sequentially arranged on the right side of the second conduction type semiconductor cathode region (6) from left to right; a gap is arranged between the second conductive type semiconductor cathode region (6) and the first second conductive type semiconductor doped region (7), every two of the first second conductive type semiconductor doped region (7), the first conductive type semiconductor doped region (8), the second conductive type semiconductor doped region (7) and the first conductive type semiconductor cathode region (9) are arranged in a contact mode, and a third metal electrode (15) is arranged on the upper surface of the second conductive type semiconductor cathode region (6); the upper surfaces of the first second conduction type semiconductor doping region (7) and the second conduction type semiconductor doping region (7) are provided with a fourth metal electrode (16); the upper surface of the first conductive type semiconductor doping area (8) is provided with a fifth metal electrode (17), and the upper surface of the first conductive type semiconductor cathode area (9) is provided with a first metal electrode (10).

2. The LIGBT-based double-gate controlled sampling device of claim 1, wherein: the first conductivity type semiconductor is a P-type semiconductor and the second conductivity type semiconductor is an N-type semiconductor.

3. The LIGBT-based double-gate controlled sampling device of claim 1, wherein: the first conductivity type semiconductor is an N-type semiconductor, and the second conductivity type semiconductor is a P-type semiconductor.

4. The LIGBT-based double-gate controlled sampling device of claim 1, wherein: the first conductivity type semiconductor or the second conductivity type semiconductor is single crystal silicon, silicon carbide, or gallium nitride.

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