CN109801962B - Double-gate control sampling device based on LIGBT - Google Patents
Double-gate control sampling device based on LIGBT Download PDFInfo
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- CN109801962B CN109801962B CN201910062231.8A CN201910062231A CN109801962B CN 109801962 B CN109801962 B CN 109801962B CN 201910062231 A CN201910062231 A CN 201910062231A CN 109801962 B CN109801962 B CN 109801962B
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Abstract
The invention provides a double-gate control sampling device based on LIGBT, which comprises a first conductive type semiconductor substrate, a substrate metal electrode, an epitaxial oxide layer, a second conductive type semiconductor drift region, a second conductive type semiconductor doping region, a first conductive type semiconductor anode region, a second metal electrode, a first conductive type semiconductor body region, an oxide layer, a metal gate, a first conductive type semiconductor body region, a second conductive type semiconductor cathode region, a first second conductive type semiconductor doping region, a first conductive type semiconductor doping region, a second conductive type semiconductor doping region, a first conductive type semiconductor cathode region, a third metal electrode, a fourth metal electrode, a fifth metal electrode and a first metal electrode, wherein the device can sample the current flowing through the device in a conducting state, and can detect the anode voltage in a turn-off transient state, the current sampling and the voltage sampling are carried out alternately, the sampling precision is high, and the sampling ratio is controllable.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and relates to a double-gate control sampling device based on LIGBT.
Background
In high-voltage and power integrated circuits and systems related to power driving, the input/output performance, the load condition and the like of the high-voltage and power integrated circuits need to be detected, so that the circuits and the systems are protected in real time, the intellectualization of the integrated circuits and the systems is met, and the normal and reliable work of the systems is effectively ensured. The realization of the control of high-voltage and power integrated circuits and application systems thereof is a research hotspot and a research scientific difficult point at home and abroad at present.
In practical application, the power semiconductor device is faced with a plurality of failure conditions, such as short-circuit events, transient current peak value overshoot under inductive load and the like, the damage of the device in a single module directly affects the reliability and stability of a circuit system, and an effective method for monitoring the stability of the device during working is to directly measure the voltage and current of the device in the power module and feed back the voltage and current in time. The traditional sampling technology is mainly realized through peripheral components, such as methods of secondary feedback sampling, resistance sampling, current mirror sampling and the like, which all bring the defects of non-adjustable signal sampling, insufficient sampling precision, increased manufacturing cost, large application circuit volume and the like.
In the aspect of current sampling, other people propose a JFET sampling structure, and as shown in figure 1, the JFET sampling device has the advantages of simple structure, high sampling precision, capability of serving as a sampling and self-powered multiplexing device and the like. In low-voltage application occasions, the JFET sampling device with the traditional structure can be used for related applications, but in high-voltage application occasions, the conventional JFET sampling device can hardly meet application requirements, firstly, the withstand voltage of the device is not enough, and the withstand voltage is difficult to design and promote again in consideration of the compromise relationship of all aspects during design; secondly, the back grid of the JFET is grounded or fixed in potential, the depth of a drift region of the sampling current is determined, and the sampling current cannot be adjusted in application, namely sampling is uncontrollable; finally, the constant current characteristic of the saturation region is poor, and the non-constant current charging can cause unstable self-power supply voltage, so that the normal work of the chip is influenced. But this configuration is not suitable for high voltage applications.
In response to the deficiencies of conventional JFET sampling devices, others have proposed a SenseFET structure as shown in fig. 2, which has a more excellent performance in current sampling: the device has the advantages of high voltage blocking capability (up to 700V), controllability of sampling current, high sampling precision, simple application (no external feedback), controllability of sampling current by controlling the grid electrode in the turn-on period, and self-power supply of the chip in the turn-off period. In addition, the SenseFET has better constant current characteristics in the saturation region when operating in the saturation region than a conventional JFET sampling device. However, the structure cannot simultaneously have the functions of current sampling and voltage sampling, and cannot completely meet the requirement of high-voltage application.
Disclosure of Invention
The invention aims to solve the problems of chip internal sampling, and provides a double-gate control sampling device based on LIGBT.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a double-gate control sampling device based on LIGBT, its cellular structure includes the semiconductor substrate 1 of the first conductivity type and substrate metal electrode 19 located in the first conductivity type semiconductor substrate 1 lower surface; the upper surface of the first conductive type semiconductor substrate 1 is provided with an epitaxial oxide layer 2; the upper surface of the epitaxial oxide layer 2 is provided with a second conductive type semiconductor drift region 3; the second conductive type semiconductor drift region 3 is provided with a second conductive type semiconductor doping region 4; the second conductive type semiconductor doping region 4 is provided with a first conductive type semiconductor anode region 5, and the upper surface of the first conductive type semiconductor anode region 5 is provided with a second metal electrode 11; the second conductivity type semiconductor drift region 3 has therein a first conductivity type semiconductor body region 13; an oxide layer 12 is formed on the upper surface of the first conductivity type semiconductor body 13; the oxide layer 12 is provided with a metal grid 14; the second conductivity type semiconductor drift region 3 has a first conductivity type semiconductor body region 18 on the right side; the first conductive type semiconductor body region 18 is provided with a second conductive type semiconductor cathode region 6, and a first second conductive type semiconductor doped region 7, a first conductive type semiconductor doped region 8, a second conductive type semiconductor doped region 7 and a first conductive type semiconductor cathode region 9 are sequentially arranged on the right side of the second conductive type semiconductor cathode region 6 from left to right; a gap is arranged between the second conductive type semiconductor cathode region 6 and the first second conductive type semiconductor doping region 7, the first conductive type semiconductor doping region 8 and the second conductive type semiconductor doping region 7 are adjacently arranged, and a third metal electrode 15 is arranged on the upper surface of the second conductive type semiconductor cathode region 6; the upper surface of the second conductive type semiconductor doping region 7 is provided with a fourth metal electrode 16; the upper surface of the first conductive type semiconductor doping region 8 is provided with a fifth metal electrode 17, and the upper surface of the first conductive type semiconductor cathode region 9 is provided with a first metal electrode 10.
Preferably, the first conductivity type semiconductor is a P-type semiconductor, and the second conductivity type semiconductor is an N-type semiconductor.
Preferably, the first conductivity type semiconductor is an N-type semiconductor, and the second conductivity type semiconductor is a P-type semiconductor.
Preferably, the first conductivity type semiconductor or the second conductivity type semiconductor is single crystal silicon, silicon carbide, or gallium nitride.
The invention has the beneficial effects that: the device can realize sampling of current flowing through the device in a conducting state, detection of anode voltage can be realized in a switching-off transient state, current sampling and voltage sampling are alternately carried out, sampling precision is high, and sampling ratio is controllable.
Drawings
FIG. 1 is a schematic diagram of a conventional JFET sampling structure;
FIG. 2 is a schematic diagram of a SenseFET sampling structure;
FIG. 3 is a schematic diagram of a two-dimensional structure of a LIGBT-based double-gate control sampling device according to the present invention;
FIG. 4 is a schematic diagram of a three-dimensional structure of a LIGBT-based double-gate control sampling device according to the present invention;
FIG. 5 is a sampling schematic of a two-dimensional device structure;
FIG. 6 is a graph of the variation of electrical parameters of various electrodes of intercepted device on and off transients, simulated by means of a simulator;
FIG. 7 is a schematic diagram of the current sampling characteristics of a LIGBT-based sampling device of the present invention;
FIG. 8 is a schematic diagram of the voltage sampling characteristics of a LIGBT-based sampling device of the present invention;
1 is a first conductive type semiconductor substrate, 2 is an epitaxial oxide layer, 3 is a second conductive type semiconductor drift region, 4 is a second conductive type semiconductor doped region, 5 is a first conductive type semiconductor anode region, 6 is a second conductive type semiconductor cathode region, 7 is a second conductive type semiconductor doped region, 8 is a first conductive type semiconductor doped region, 9 is a first conductive type semiconductor cathode region, 10 is a first metal electrode, 11 is a second metal electrode, 12 is an oxide layer, 13 is a first conductive type semiconductor body region, 14 is a metal gate, 15 is a third metal electrode, 16 is a fourth metal electrode, 17 is a fifth metal electrode, 18 is a first conductive type semiconductor body region, 19 is a substrate metal electrode, 20 is a current sampling electrode, 21 is a drift region surface second conductive type semiconductor heavily doped region, 22 is a substrate surface first conductive type semiconductor heavily doped region, reference numeral 23 denotes a first conductivity type semiconductor body region, 24 denotes a first conductivity type semiconductor heavily doped region, 25 denotes a gate metal electrode, and 26 denotes a polysilicon electrode.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
The double-gate control sampling device based on the LIGBT comprises a cell structure, as shown in FIG. 3, a first conductive type semiconductor substrate 1 and a substrate metal electrode 19 positioned on the lower surface of the first conductive type semiconductor substrate 1; the upper surface of the first conductive type semiconductor substrate 1 is provided with an epitaxial oxide layer 2; the upper surface of the epitaxial oxide layer 2 is provided with a second conductive type semiconductor drift region 3; the second conductive type semiconductor drift region 3 is provided with a second conductive type semiconductor doping region 4; the second conductive type semiconductor doping region 4 is provided with a first conductive type semiconductor anode region 5, and the upper surface of the first conductive type semiconductor anode region 5 is provided with a second metal electrode 11; the second conductivity type semiconductor drift region 3 has therein a first conductivity type semiconductor body region 13; an oxide layer 12 is formed on the upper surface of the first conductivity type semiconductor body 13; the oxide layer 12 is provided with a metal grid 14; the second conductivity type semiconductor drift region 3 has a first conductivity type semiconductor body region 18 on the right side; the first conductive type semiconductor body region 18 is provided with a second conductive type semiconductor cathode region 6, and a first second conductive type semiconductor doped region 7, a first conductive type semiconductor doped region 8, a second conductive type semiconductor doped region 7 and a first conductive type semiconductor cathode region 9 are sequentially arranged on the right side of the second conductive type semiconductor cathode region 6 from left to right; a gap is arranged between the second conductive type semiconductor cathode region 6 and the first second conductive type semiconductor doping region 7, the first conductive type semiconductor doping region 8 and the second conductive type semiconductor doping region 7 are adjacently arranged, and a third metal electrode 15 is arranged on the upper surface of the second conductive type semiconductor cathode region 6; the upper surface of the second conductive type semiconductor doping region 7 is provided with a fourth metal electrode 16; the upper surface of the first conductive type semiconductor doping region 8 is provided with a fifth metal electrode 17, and the upper surface of the first conductive type semiconductor cathode region 9 is provided with a first metal electrode 10.
Preferably, the first conductivity type semiconductor is a P-type semiconductor, and the second conductivity type semiconductor is an N-type semiconductor. Or the first conductive type semiconductor is an N-type semiconductor and the second conductive type semiconductor is a P-type semiconductor.
Preferably, the first conductivity type semiconductor or the second conductivity type semiconductor is single crystal silicon, silicon carbide, or gallium nitride.
The working principle of the present invention is illustrated below by taking a sampling device of a P-type substrate as an example:
as shown in fig. 3 and 4, based on the LIGBT structure, the second conductivity type semiconductor doping region 7 is implanted between the second conductivity type semiconductor cathode region 6 and the first conductivity type semiconductor cathode region 9 in the first conductivity type semiconductor body region 18, where the second conductivity type semiconductor doping region 7 and the first conductivity type semiconductor doping region 8 constitute a JFET structure. As shown in fig. 5, when the metal gate 14 is turned on, a current flows from the second metal electrode 11 through the inside of the device, the second conductivity type semiconductor drift region 3 is subjected to conductivity modulation, the current is shunted in the first conductivity type semiconductor body region 18, a part of the current flows through the cathode third metal electrode 15 and the first metal electrode 10, and a part of the current flows through the fifth metal electrode 17, so that the device can monitor the device current in an on state, and when the current of the second metal electrode 11 increases, the sampling current of the fifth metal electrode 17 also increases. When a positive voltage is applied to the fourth metal electrode 16, the PN junction is reversely biased, the depletion region expands to narrow the carrier path, and the current value of the fifth metal electrode 17 decreases, thereby realizing the controllability of current sampling.
When the metal gate 14 is turned off, the voltage of the second metal electrode 11 of the device rises rapidly, at this time, a large number of holes stored in the second conductivity type semiconductor drift region 3 during the forward conduction process will also be released from the third metal electrode 15, the first metal electrode 10 and the fifth metal electrode 17, a short voltage rise will occur in the fifth metal electrode 17, and the voltage rise process of the second metal electrode 11 is synchronized with the voltage rise process of the fifth metal electrode 17, so that the device can monitor the voltage of the second metal electrode 11, when a positive voltage is applied to the fourth metal electrode 16, the PN junction is reversely biased, the depletion region expands to narrow the path of carriers, the current value of the fifth metal electrode 17 decreases, and thus the controllability of voltage sampling is realized.
In order to verify the beneficial results of the invention, the structure of the device is simulated by Medici software, and the simulation of electrical parameters is carried out, wherein the main simulation parameters are as follows: substrate doping concentration of 1.2e14cm-3Drift region doping concentration of 3e14cm-3The drift region length was 60 μm, the junction depth was 30 μm, and the doping concentration of Pbody was 2e17cm-3The depth of the internal shallow junction of Pbody is 0.5 μm. The simulation result shows that: the new structure has high voltage blocking capability, the breakdown voltage of the device is 675V, and the threshold voltage is 3V. In the dynamic simulation, a voltage sampling terminal is connected with a 1 Ω sampling resistor, a cathode is grounded, the current flowing through the device is changed in a conducting state to obtain a current sampling image as shown in fig. 7, a control gate is 0V, and when the anode current increases, the sampling current of a sensing electrodeAnd also increases with the sampling of the current being linearly varied. As shown in fig. 6, the control gate is 0V, when the gate voltage drops and the device is in the off-state, the voltage of the sensing electrode will rise and fall back to 0V after reaching the peak value, and the anode voltage rising process and the sensing electrode voltage rising process are synchronous, so that the device can monitor the electrode voltage, and fig. 8 is a graph showing the change of the sensing electrode voltage following the anode voltage.
Structural parameters such as the length L, the width W and the doping concentration N of a P-type shallow junction in structural parameters of the device also influence the magnitude of sampling voltage, and the larger L, the larger W or the larger N is under the same condition, the larger the sampling current and the sampling voltage value of a sampling end are.
In summary, according to the double-gate control sampling device based on the LIGBT provided by the invention, through the Pbody built-in sampling structure, the device can alternately sample the current and the voltage, and the controllability of the sampling voltage and the current can be realized due to the existence of the control gate.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (4)
1. A double-gate control sampling device based on LIGBT comprises a first conductive type semiconductor substrate (1) and a substrate metal electrode (19) positioned on the lower surface of the first conductive type semiconductor substrate (1); the upper surface of the first conductive type semiconductor substrate (1) is provided with an epitaxial oxide layer (2); the upper surface of the epitaxial oxide layer (2) is provided with a second conductive type semiconductor drift region (3); the second conduction type semiconductor drift region (3) is provided with a second conduction type semiconductor doping region (4) on the left side and a first conduction type semiconductor body region (13) in the middle, the second conduction type semiconductor doping region (4) is provided with a first conduction type semiconductor anode region (5), and the upper surface of the first conduction type semiconductor anode region (5) is provided with a second metal electrode (11); the second conductivity type semiconductor drift region (3) has a first conductivity type semiconductor body region (13) therein; the upper surface of the first conduction type semiconductor body (13) is provided with an oxide layer (12); the oxide layer (12) is provided with a metal grid (14); the middle right side of the second conduction type semiconductor drift region (3) is provided with a second first conduction type semiconductor body region (18); the method is characterized in that: the second first conduction type semiconductor body region (18) is internally provided with a second conduction type semiconductor cathode region (6), and a first second conduction type semiconductor doped region (7), a first conduction type semiconductor doped region (8), a second conduction type semiconductor doped region (7) and a first conduction type semiconductor cathode region (9) are sequentially arranged on the right side of the second conduction type semiconductor cathode region (6) from left to right; a gap is arranged between the second conductive type semiconductor cathode region (6) and the first second conductive type semiconductor doped region (7), every two of the first second conductive type semiconductor doped region (7), the first conductive type semiconductor doped region (8), the second conductive type semiconductor doped region (7) and the first conductive type semiconductor cathode region (9) are arranged in a contact mode, and a third metal electrode (15) is arranged on the upper surface of the second conductive type semiconductor cathode region (6); the upper surfaces of the first second conduction type semiconductor doping region (7) and the second conduction type semiconductor doping region (7) are provided with a fourth metal electrode (16); the upper surface of the first conductive type semiconductor doping area (8) is provided with a fifth metal electrode (17), and the upper surface of the first conductive type semiconductor cathode area (9) is provided with a first metal electrode (10).
2. The LIGBT-based double-gate controlled sampling device of claim 1, wherein: the first conductivity type semiconductor is a P-type semiconductor and the second conductivity type semiconductor is an N-type semiconductor.
3. The LIGBT-based double-gate controlled sampling device of claim 1, wherein: the first conductivity type semiconductor is an N-type semiconductor, and the second conductivity type semiconductor is a P-type semiconductor.
4. The LIGBT-based double-gate controlled sampling device of claim 1, wherein: the first conductivity type semiconductor or the second conductivity type semiconductor is single crystal silicon, silicon carbide, or gallium nitride.
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| US20050110097A1 (en) * | 2003-10-16 | 2005-05-26 | University Of Electronic Science And Technology | Lateral low-side and high-side high-voltage devices |
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| CN105409004A (en) * | 2013-07-02 | 2016-03-16 | 剑桥微电子有限公司 | Lateral power semiconductor transistors |
| CN108122963A (en) * | 2017-12-22 | 2018-06-05 | 重庆大学 | A kind of potential controls quick landscape insulation bar double-pole-type transistor |
| CN108767006A (en) * | 2018-05-31 | 2018-11-06 | 电子科技大学 | A kind of IGBT device of integrated voltage sample function |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050110097A1 (en) * | 2003-10-16 | 2005-05-26 | University Of Electronic Science And Technology | Lateral low-side and high-side high-voltage devices |
| CN102751316A (en) * | 2012-07-31 | 2012-10-24 | 电子科技大学 | Transverse signal operation instruction (SOI) power device |
| CN105409004A (en) * | 2013-07-02 | 2016-03-16 | 剑桥微电子有限公司 | Lateral power semiconductor transistors |
| CN108122963A (en) * | 2017-12-22 | 2018-06-05 | 重庆大学 | A kind of potential controls quick landscape insulation bar double-pole-type transistor |
| CN108767006A (en) * | 2018-05-31 | 2018-11-06 | 电子科技大学 | A kind of IGBT device of integrated voltage sample function |
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