CN102738165B - A kind of mix-crystal facial plane strain BiCMOS integrated device and preparation method - Google Patents

Abstract

The invention discloses a kind of mix-crystal facial plane strain BiCMOS integrated device and circuit preparation method.Its process is: preparation a slice SOI substrate, and the basis material on upper strata is (110) crystal face, and the basis material of lower floor is (100) crystal face; Conventional Si bipolar transistor is manufactured in bipolar device region; In nmos device region, selective growth crystal face is the strain Si epitaxial loayer of (100), prepares strained Si channel nmos device; In the region of PMOS device active area, selective growth crystal face is the strain SiGe epitaxial loayer of (110), prepares the compressive strain SiGe channel PMOS device of raceway groove; Photoetching goes between, and forms the mix-crystal facial plane strain BiCMOS integrated device that MOS device conducting channel is 22 ~ 45nm; The present invention is abundant utilizes tensile strain Si material electronics mobility higher than body Si material and compressive strain sige material electron mobility higher than body Si material and the anisotropic feature of mobility, based on SOI substrate, prepare mix-crystal facial plane strain BiCMOS integrated device and the circuit of performance enhancement.

Description

A kind of mix-crystal facial plane strain BiCMOS integrated device and preparation method

Technical field

The invention belongs to semiconductor integrated circuit technical field, particularly relate to a kind of mixing crystal face strain mix-crystal facial plane strain BiCMOS integrated device and preparation method.

Background technology

In the present age of information technology high development, the key of information technology that to take integrated circuit as the microelectric technique of representative be.Integrated circuit as with fastest developing speed in human history, have the greatest impact, most widely used technology, it has become the important symbol of measurement national science technical merit, overall national strength and a defense force.

Develop to microelectronic industry " Moore's Law " that have an immense impact on to point out: the transistor size in integrated circuit (IC) chip, within about every 18 months, increase by 1 times, performance also promotes 1 times.Over more than 40 year, world's microelectronic industry constantly advances according to this law all the time, and circuit scale has been developed into present ultra-large by initial small-scale; Si material is with the performance of its excellence, always in occupation of consequence in microelectronic industry, and CMOS integrated circuit based on Si material with the advantages such as low-power consumption, low noise, high input impedance, high integration, good reliability in integrated circuit fields in occupation of leading position.

Along with the progressively reduction of device feature size, especially enter after nanoscale, the development of microelectric technique more and more approaches the limit of material, technology, device, is faced with huge challenge.After device feature size narrows down to 65 nanometers, the impact of the problem such as impact, technological parameter fluctuation on performances such as device leakage current, subthreshold behavior, ON state/off-state currents of the short channel effect in MOS device, high-field effect, quantum effect, parasitic parameter is more and more outstanding; And along with the develop rapidly of wireless mobile communications, to the performance of device and integrated circuit, as frequency characteristic, noise characteristic, package area, power consumption and cost etc. are had higher requirement, device prepared by traditional silica-based technique and integrated circuit more and more cannot meet demand that is novel, high-velocity electrons system.

An important performance indexes of CMOS integrated circuit is the driving force of NMOS and PMOS device, and the mobility in electronics and hole is one of key factor determining its driving force respectively; In order to improve the performance of nmos device and PMOS device and then improve the performance of CMOS integrated circuit, the mobility of two kinds of charge carriers all should be high as much as possible.

As far back as the fifties in last century, just study and found stress application on silicon materials, the mobility in electronics and hole can have been changed, thus changed NMOS prepared on semi-conducting material and the performance of PMOS device; But identical reaction is not always made to stress of the same race in electronics and hole; Meanwhile, identical crystal face is prepared nmos device and PMOS device, their mobility can not reach optimum simultaneously.

Because Si material carrier material mobility is lower, so adopt the performance of integrated circuits that SiBiCMOS technology manufactures, especially frequency performance, is greatly limited.

For this reason, will when not reducing a kind of mobility of charge carrier of types of devices, improve the mobility of the charge carrier of another kind of types of devices, this patent proposes a kind of strain gauge technique and prepares CMOS, namely strains the preparation of mix-crystal facial plane strain BiCMOS integrated device and circuit.

Summary of the invention

A kind of mix-crystal facial plane is the object of the present invention is to provide to strain BiCMOS integrated device and preparation method, to realize under the condition not changing existing equipment and increase cost, conducting channel is mix-crystal facial plane strain BiCMOS integrated device and the circuit of 22 ~ 45nm.

The object of the present invention is to provide a kind of mix-crystal facial plane to strain BiCMOS integrated device and circuit, nmos device is strain Si planar channeling, and PMOS device is strain SiGe planar channeling, and bipolar device is SiSOIBJT.

Further, the conducting channel of nmos device is tensile strain Si material, and the conducting channel of nmos device is planar channeling.

Further, the conducting channel of PMOS device is compressive strain sige material, and the conducting channel of PMOS device is planar channeling.

Further, nmos device is different with the crystal face of PMOS device, and wherein the crystal face of nmos device is (100), and the crystal face of PMOS device is (110).

Further, PMOS device adopts quantum well structure.

Further, bipolar device substrate is SOI material.

Another object of the present invention is to provide a kind of mix-crystal facial plane to strain the preparation method of BiCMOS integrated device, comprise the steps:

The first step, choose two panels Si sheet, one piece is N-type doping content is 1 ~ 5 × 10 ¹⁵cm ^-3si(110) substrate slice, as the basis material of upper strata active layer, another block is P type doping content is 1 ~ 5 × 10 ¹⁵cm ^-3si(100) substrate slice, as the basis material of lower floor's active layer; Be oxidized two panels Si sheet surface, oxidated layer thickness is 0.5 ~ 1 μm, adopts chemico-mechanical polishing (CMP) technique to carry out polishing to two oxide layer surfaces;

Second step, to hydrogen injecting in the active layer basis material of upper strata, and two panels Si sheet oxide layer is placed in ultra-high vacuum environment relatively at the temperature of 350 ~ 480 DEG C and realizes bonding; Si sheet temperature after bonding is raised 100 ~ 200 DEG C, make the hydrogen place fracture that upper strata basis material is injecting, the part unnecessary to upper strata basis material is peeled off, and retains the Si material of 100 ~ 200nm, and carry out chemico-mechanical polishing (CMP) at its break surface, form SOI substrate;

3rd step, photoetching bipolar device active area, epitaxial growth one deck doping content is 1 × 10 ¹⁶~ 1 × 10 ¹⁷cm ^-3si layer, thickness is 100 ~ 200nm, as collector region;

4th step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO ₂, photoetching isolated area, utilizes dry etch process, etches in isolated area the deep trouth that the degree of depth is 2.5 ~ 3.5 μm, utilizes chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin, deep trouth inner surface is all covered, last deposit SiO ₂fill up in deep trouth, form deep trench isolation;

5th step, contact zone, photoetching collector region, carry out the injection of N-type impurity to collector region, and at 800 ~ 950 DEG C, annealing 30 ~ 90min activator impurity, forming doping content is 1 × 10 ¹⁹~ 1 × 10 ²⁰the heavy doping collector electrode of cm-3;

6th step, at substrate surface thermal oxidation one SiO ₂layer, photoetching base, carries out the injection of p type impurity to base, and at 800 ~ 950 DEG C, annealing 30 ~ 90min activator impurity, forming doping content is 1 × 10 ¹⁸~ 5 × 10 ¹⁸cm ^-3base;

7th step, at substrate surface thermal oxidation one SiO ₂layer, photoetching emitter region, carries out the injection of N-type impurity to substrate, and at 800 ~ 950 DEG C, annealing 30 ~ 90min activator impurity, forming doping content is 5 × 10 ¹⁹~ 5 × 10 ²⁰cm ^-3highly doped emitter, utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ~ 800 DEG C, deposit one SiO ₂layer;

8th step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO ₂, photoetching nmos device active area, utilizes dry etch process, in nmos device active area, etches the deep trouth that the degree of depth is 1.7 ~ 2.9 μm, the oxide layer of centre is carved thoroughly; Utilize chemical vapor deposition (CVD) method, at 600 ~ 750 DEG C, selective epitaxial growth four layer material on the nmos device active area of (100) crystal face substrate: the P type Si resilient coating of ground floor to be thickness be 200 ~ 400nm, doping content is 1 ~ 5 × 10 ¹⁵cm ^-3; The P type SiGe graded bedding of the second layer to be thickness be 1.3 ~ 2.1nm, this layer of bottom Ge component is 0%, and top Ge component is 15 ~ 25%, and doping content is 1 ~ 5 × 10 ¹⁵cm ^-3; Third layer is Ge component is 15 ~ 25%, and thickness is the P type SiGe layer of 200 ~ 400nm, and doping content is 0.5 ~ 5 × 10 ¹⁷cm ^-3; The P type strained si layer/of the 4th layer of to be thickness be 8 ~ 20nm, doping content is 0.5 ~ 5 × 10 ¹⁷cm ^-3, as the raceway groove of nmos device; Utilize wet etching, etch away the layer SiO on surface ₂;

9th step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO ₂photoetching PMOS device active area, utilizes chemical vapor deposition (CVD) method, at 600 ~ 750 DEG C, selective epitaxial growth trilaminate material on PMOS device active area: the N-type Si resilient coating of ground floor to be thickness be 100 ~ 200nm, doping content is 0.5 ~ 5 × 10 ¹⁷cm ^-3, the N-type SiGe strained layer of the second layer to be thickness be 8 ~ 20nm, Ge component is 15 ~ 25%, and doping content is 0.5 ~ 5 × 10 ¹⁷cm ^-3, as the raceway groove of PMOS device, the intrinsic relaxation Si cap layers of third layer to be thickness be 3 ~ 5nm, forms PMOS device active area; Utilize wet etching, etch away the layer SiO on surface ₂;

Tenth step, photoetching Chang Yang district, utilize dry etch process, and oxygen district on the scene etches the shallow slot that the degree of depth is 0.3 ~ 0.5 μm; Recycling chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, fills SiO in shallow slot ₂; Finally, by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation;

11 step, at 300 ~ 400 DEG C, use the method deposit HfO of atomic layer chemical vapor deposit (ALCVD) on the active area ₂layer, thickness is 6 ~ 10nm, as the gate medium of nmos device and PMOS device, recycling chemical vapor deposition (CVD) method, at 600 ~ 750 DEG C, on gate dielectric layer deposit a layer thickness be the intrinsic Poly-SiGe of 100 ~ 500nm as gate electrode, Ge component is 10 ~ 30%; Photoetching NMOS and PMOS device gate medium and grid polycrystalline, form grid;

12 step, photoetching nmos device active area, carry out N-type ion implantation to nmos device active area, and forming doping content is 1 ~ 5 × 10 ¹⁸cm ^-3n-type lightly-doped source drain structure (N-LDD) region; Photoetching PMOS device active area, carries out P type ion implantation to PMOS device active area, and forming doping content is 1 ~ 5 × 10 ¹⁸cm ^-3p type lightly-doped source drain structure (P-LDD) region;

13 step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, deposit one thickness is the SiO of 3 ~ 5nm over the entire substrate ₂layer, falls this layer of SiO with dry etching ₂, form nmos device and PMOS device grid curb wall;

14 step, photoetching nmos device active area, carry out N-type ion implantation in nmos device active area, and autoregistration generates the source region of nmos device, drain region and grid; Photoetching PMOS device active area, carries out N-type ion implantation in PMOS device active area, and autoregistration generates the source region of PMOS device, drain region and grid;

15 step, use chemical vapor deposition (CVD) method over the entire substrate, at 600 ~ 800 DEG C, the SiO that deposit 300 ~ 500nm is thick ₂layer; Make lead-in wire window by lithography, sputter layer of metal titanium (Ti) over the entire substrate, alloy, autoregistration forms metal silicide, the metal that clean surface is unnecessary, forms metal electrode, forms the mix-crystal facial plane strain BiCMOS integrated device that MOS device conducting channel is 22 ~ 45nm.

Further, channel length gets 22 ~ 45nm.

Further, maximum temperature involved in this preparation method determines according to chemical vapor deposition (CVD) technological temperature, and maximum temperature is less than or equal to 800 DEG C.

Another object of the present invention is to provide a kind of mix-crystal facial plane to strain the preparation method of BiCMOS integrated circuit, comprise the steps:

Step 1, implementation method prepared by SOI substrate material is:

(1a) choosing N-type doping content is 1 × 10 ¹⁵cm ^-3si sheet, crystal face is (110), is oxidized its surface, and oxidated layer thickness is 0.5 μm, as the basis material on upper strata, and in this basis material hydrogen injecting;

(1b) choosing P type doping content is 1 × 10 ¹⁵cm ^-3si sheet, crystal face is (100), is oxidized its surface, and oxidated layer thickness is 0.5 μm, as the basis material of lower floor;

(1c) adopt chemico-mechanical polishing (CMP) technique, respectively polishing is carried out to the upper strata substrate material surface after lower floor and hydrogen injecting;

(1d) by the lower floor after polishing and upper strata substrate material surface SiO ₂relatively be close to, be placed in ultra-high vacuum environment and realize bonding at 350 DEG C of temperature;

(1e) substrate temperature after bonding is raised 200 DEG C, make the hydrogen place fracture that upper strata basis material is injecting, the part unnecessary to upper strata basis material is peeled off, and retains the Si material of 100nm, and carry out chemico-mechanical polishing (CMP) at this break surface, form soi structure;

Step 2, the implementation method of isolation preparation is:

(2a) photoetching bipolar device active area, epitaxial growth one deck doping content is 1 × 10 ¹⁶cm ^-3si layer, thickness is 100nm, as collector region;

(2b) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit one deck SiO ₂;

(2c) photoetching isolated area, utilizes dry etch process, etches in isolated area the deep trouth that the degree of depth is 2.5 μm;

(2d) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at deep trouth inner surface deposit SiO ₂layer, all covers deep trouth inner surface;

(2e) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, SiO in deep trouth ₂on layer, the layer of deposit layer of sin again, all covers deep trouth inner surface;

(2f) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in deep trouth, fill SiO ₂, utilize chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form deep trench isolation;

Step 3, implementation method prepared by bipolar device is:

(3a) contact zone, photoetching collector region, carries out the injection of N-type impurity to collector region, and at 800 DEG C, annealing 90min activator impurity, forming doping content is 1 × 10 ¹⁹cm ^-3heavy doping collector electrode;

(3b) at substrate surface thermal oxidation one SiO ₂layer, photoetching base, carries out the injection of p type impurity to base, and at 800 DEG C, annealing 90min activator impurity, forming doping content is 1 × 10 ¹⁸cm ^-3base;

(3c) at substrate surface thermal oxidation one SiO ₂layer, photoetching emitter region, carries out the injection of N-type impurity to substrate, and at 800 DEG C, annealing 90min activator impurity, becomes doping content to be 5 × 10 ¹⁹cm ^-3highly doped emitter, form bipolar transistor;

(3d) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 DEG C, deposit one SiO ₂layer;

Step 4, implementation method prepared by nmos device district is:

(4a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit one deck SiO ₂;

(4b) photoetching nmos device active area, utilizes dry etch process, in nmos device active area, etches the deep trouth that the degree of depth is 1.7 μm, oxide layer is carved thoroughly;

(4c) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, in deep trouth, grow the P type Si resilient coating that a layer thickness is 200nm along (100) crystal face, doping content is 1 × 10 ¹⁵cm ^-3;

(4d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, P type resilient coating grows the SiGe that a layer thickness is the P type Ge component trapezoidal profile of 1.3 μm, bottom Ge component is 0%, and top is 15%, and doping content is 1 × 10 ¹⁵cm ^-3;

(4e) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, the SiGe layer of Ge component trapezoidal profile grows the P type SiGe layer that a layer thickness is 200nm, and Ge component is 15%, and doping content is 5 × 10 ¹⁶cm ^-3;

(4f) utilize chemical vapor deposition (CVD) method, at 600 DEG C, growing a layer thickness is on the sige layer the strained si layer/of 20nm, and doping content is 5 × 10 ¹⁶cm ^-3, as the raceway groove of nmos device;

(4g) utilize wet etching, etch away the layer SiO on surface ₂;

Step 5, implementation method prepared by PMOS device district is:

(5a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit one deck SiO ₂;

(5b) photoetching PMOS device active area, utilizes the method for chemical vapor deposition (CVD), and at 600 DEG C, grow along (110) crystal face the N-type Si resilient coating that a layer thickness is 200nm in PMOS device active area, doping content is 5 × 10 ¹⁶cm ^-3;

(5c) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, Si resilient coating grows the P type SiGe layer that a layer thickness is 20nm, and Ge component is 15%, and doping content is 5 × 10 ¹⁶cm ^-3;

(5d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, strained sige layer grows the intrinsic relaxation Si cap layers that a layer thickness is 5nm, form PMOS device active area;

(5e) utilize wet etching, etch away the layer SiO on surface ₂;

Step 6, implementation method prepared by shallow-trench isolation is:

(6a) photoetching Chang Yang district, utilizes dry etch process, etches in isolated area the shallow slot that the degree of depth is 0.3 μm;

(6b) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂;

(6c) by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation;

Step 7, implementation method prepared by MOS device grid and light dope source and drain (LDD) is:

(7a) at 300 DEG C, the method deposit HfO of atomic layer chemical vapor deposit (ALCVD) is used on the active area ₂layer, thickness is 6nm, as the gate medium of nmos device and PMOS device;

(7b) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, the Poly-SiGe of deposit one deck intrinsic on gate dielectric layer, thickness is 100nm, Ge component is 10%;

(7c) photoetching NMOS and PMOS device gate medium and grid polycrystalline, forms grid;

(7d) photoetching nmos device active area, carries out N-type ion implantation to nmos device active area, and forming doping content is 1 × 10 ¹⁸cm ^-3n-type lightly-doped source drain structure (N-LDD) region;

(7e) photoetching PMOS device active area, carries out P type ion implantation to PMOS device active area, and forming doping content is 1 × 10 ¹⁸cm ^-3p type lightly-doped source drain structure (P-LDD) region;

Step 8, the implementation method that MOS device is formed is:

(8a) utilize chemical vapor deposition (CVD) method, at 600 DEG C, deposit one thickness is the SiO of 3nm over the entire substrate ₂layer;

(8b) dry etch process is utilized, eating away this layer of SiO ₂, retain nmos device and PMOS device grid curb wall;

(8c) photoetching nmos device active area, carries out N-type ion implantation in nmos device active area, and autoregistration generates the source of nmos device, drain region and grid;

(8d) photoetching PMOS device active area, carries out N-type ion implantation in PMOS device active area, and autoregistration generates the source of PMOS device, drain region and grid;

Step 9, the implementation method forming BiCMOS integrated circuit is:

(9a) by chemical vapor deposition (CVD) method, at 600 DEG C, the SiO that deposit 300nm is thick over the entire substrate ₂layer;

(9b) photoetching lead-in wire window, sputters layer of metal titanium (Ti), alloy over the entire substrate, and autoregistration forms metal silicide, the metal that clean surface is unnecessary, forms Metal Contact;

(9c) splash-proofing sputtering metal, photoetching goes between, form the drain electrode of the source electrode of nmos device, gate electrode, drain electrode and PMOS device, source electrode, gate electrode respectively, and bipolar transistor emitter pole, base metal are drawn, collector electrode metal goes between, final MOS device forms the mix-crystal facial plane strain BiCMOS integrated device and circuit that conducting channel is 22nm.

tool of the present invention has the following advantages:

1. the mix-crystal facial plane that prepared by the present invention strains in BiCMOS integrated device and circuit and have employed SOI substrate, reduces the power consumption of device and circuit, improves the reliability of device and circuit;

2. the mix-crystal facial plane that prepared by the present invention strains BiCMOS integrated device and circuit have employed mixing crystal face substrate technology, namely on same substrate slice, be distributed with (100) and (110) these two kinds of crystal faces, on (100) crystal face, electron mobility is the highest, and for hole, (110) the highest on crystal face, for 2.5 times on (100) crystal face, present invention incorporates two kinds of crystal faces that carrier mobility reaches the highest simultaneously, when not reducing a kind of mobility of charge carrier of types of devices, the mobility of the charge carrier of another kind of types of devices can be improved;

3. the mix-crystal facial plane that prepared by the present invention strains BiCMOS integrated device and circuit, adopt selective epitaxial technology, respectively in nmos device and PMOS device active area selective growth tensile strain Si and compressive strain sige material, nmos device and the electric property such as PMOS device frequency performance and current driving ability are obtained promote, thus cmos device and performance of integrated circuits obtain enhancing simultaneously;

4. the mix-crystal facial plane that prepared by the present invention strains MOS device in BiCMOS integrated device and circuit structure and have employed the HfO of high-k ₂as gate medium, improve the grid-control ability of MOS device, enhance the electric property of NMOS and PMOS device;

5. it is quantum well devices that the mix-crystal facial plane that prepared by the present invention strains PMOS device in BiCMOS integrated device and circuit structure, namely strain SiGe channel layer is between Si cap layers and body Si layer, compared with surface channel device, this device can reduce channel interface scattering effectively, improves device electrology characteristic; Meanwhile, quantum well can make the problem in hot electron injection grid medium improve, and adds the reliability of device and circuit;

6. the present invention prepares in mix-crystal facial plane strain BiCMOS integrated device and circuit technology, adopt Poly-SiGe material as gate electrode, its work function changes with the change of Ge component, by regulating Ge component in Poly-SiGe, realizing CMOS threshold voltage can continuous setup, decrease processing step, reduce technology difficulty;

7. it is 800 DEG C that the mix-crystal facial plane that prepared by the present invention strains the maximum temperature related in BiCMOS integrated device and circuitry processes, lower than the technological temperature causing strained Si channel stress relaxation, therefore this preparation method can keep strained Si channel stress effectively, improves the performance of integrated circuit;

8. the mix-crystal facial plane that prepared by the present invention strains in BiCMOS integrated device and circuit, bipolar device adopts the collector region thickness of SOI substrate thin compared with traditional devices, therefore, there is collector region effect extending transversely in this device, and two dimensional electric field can be formed in collector region, thus improve reverse breakdown voltage and the Early voltage of this device, under identical breakdown characteristics, there is the characteristic frequency more excellent than traditional devices.

Accompanying drawing explanation

Fig. 1 is process chart prepared by mix-crystal facial plane provided by the invention strain BiCMOS integrated device.

Embodiment

In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.

Embodiments provide a kind of mix-crystal facial plane strain BiCMOS integrated device and circuit, nmos device is strain Si planar channeling, and PMOS device is strain SiGe planar channeling, and bipolar device is SiSOIBJT.

As a prioritization scheme of the embodiment of the present invention, the conducting channel of nmos device is tensile strain Si material, and the conducting channel of nmos device is planar channeling.

As a prioritization scheme of the embodiment of the present invention, the conducting channel of PMOS device is compressive strain sige material, and the conducting channel of PMOS device is planar channeling.

As a prioritization scheme of the embodiment of the present invention, the conducting channel of PMOS device is compressive strain sige material, and the conducting channel of PMOS device is planar channeling.

As a prioritization scheme of the embodiment of the present invention, PMOS device adopts quantum well structure.

As a prioritization scheme of the embodiment of the present invention, bipolar device substrate is SOI material.

Referring to accompanying drawing 1, preparation method's technological process of mix-crystal facial plane strain BiCMOS integrated device of the present invention and circuit is described in further detail.

Embodiment 1: preparation 22nm mix-crystal facial plane strain BiCMOS integrated device and circuit, concrete steps are as follows:

Step 1, prepared by SOI substrate material.

(1a) choosing N-type doping content is 1 × 10 ¹⁵cm ^-3si sheet, crystal face is (110), is oxidized its surface, and oxidated layer thickness is 0.5 μm, as the basis material on upper strata, and in this basis material hydrogen injecting;

(1b) choosing P type doping content is 1 × 10 ¹⁵cm ^-3si sheet, crystal face is (100), is oxidized its surface, and oxidated layer thickness is 0.5 μm, as the basis material of lower floor;

(1c) adopt chemico-mechanical polishing (CMP) technique, respectively polishing is carried out to the upper strata substrate material surface after lower floor and hydrogen injecting;

(1d) by the lower floor after polishing and upper strata substrate material surface SiO ₂relatively be close to, be placed in ultra-high vacuum environment and realize bonding at 350 DEG C of temperature;

(1e) substrate temperature after bonding is raised 200 DEG C, make the hydrogen place fracture that upper strata basis material is injecting, the part unnecessary to upper strata basis material is peeled off, and retains the Si material of 100nm, and carry out chemico-mechanical polishing (CMP) at this break surface, form soi structure.

Step 2, isolation preparation.

(2a) photoetching bipolar device active area, epitaxial growth one deck doping content is 1 × 10 ¹⁶cm ^-3si layer, thickness is 100nm, as collector region;

(2b) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit one deck SiO ₂;

(2c) photoetching isolated area, utilizes dry etch process, etches in isolated area the deep trouth that the degree of depth is 2.5 μm;

(2d) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at deep trouth inner surface deposit SiO ₂layer, all covers deep trouth inner surface;

(2e) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, SiO in deep trouth ₂on layer, the layer of deposit layer of sin again, all covers deep trouth inner surface;

(2f) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in deep trouth, fill SiO ₂, utilize chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form deep trench isolation.

Step 3, prepared by bipolar device.

(3a) contact zone, photoetching collector region, carries out the injection of N-type impurity to collector region, and at 800 DEG C, annealing 90min activator impurity, forming doping content is 1 × 10 ¹⁹cm ^-3heavy doping collector electrode;

(3b) at substrate surface thermal oxidation one SiO ₂layer, photoetching base, carries out the injection of p type impurity to base, and at 800 DEG C, annealing 90min activator impurity, forming doping content is 1 × 10 ¹⁸cm ^-3base;

(3c) at substrate surface thermal oxidation one SiO ₂layer, photoetching emitter region, carries out the injection of N-type impurity to substrate, and at 800 DEG C, annealing 90min activator impurity, becomes doping content to be 5 × 10 ¹⁹cm ^-3highly doped emitter, form bipolar transistor;

(3d) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 DEG C, deposit one SiO ₂layer.

Step 4, prepared by nmos device district.

(4a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit one deck SiO ₂;

(4b) photoetching nmos device active area, utilizes dry etch process, in nmos device active area, etches the deep trouth that the degree of depth is 1.7 μm, oxide layer is carved thoroughly;

(4c) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, in deep trouth, grow the P type Si resilient coating that a layer thickness is 200nm along (100) crystal face, doping content is 1 × 10 ¹⁵cm ^-3;

(4d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, P type resilient coating grows the SiGe that a layer thickness is the P type Ge component trapezoidal profile of 1.3 μm, bottom Ge component is 0%, and top is 15%, and doping content is 1 × 10 ¹⁵cm ^-3;

(4e) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, the SiGe layer of Ge component trapezoidal profile grows the P type SiGe layer that a layer thickness is 200nm, and Ge component is 15%, and doping content is 5 × 10 ¹⁶cm ^-3;

(4f) utilize chemical vapor deposition (CVD) method, at 600 DEG C, growing a layer thickness is on the sige layer the strained si layer/of 20nm, and doping content is 5 × 10 ¹⁶cm ^-3, as the raceway groove of nmos device;

(4g) utilize wet etching, etch away the layer SiO on surface ₂.

Step 5, prepared by PMOS device district.

(5a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit one deck SiO ₂;

(5b) photoetching PMOS device active area, utilizes the method for chemical vapor deposition (CVD), and at 600 DEG C, grow along (110) crystal face the N-type Si resilient coating that a layer thickness is 200nm in PMOS device active area, doping content is 5 × 10 ¹⁶cm ^-3;

(5c) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, Si resilient coating grows the P type SiGe layer that a layer thickness is 20nm, and Ge component is 15%, and doping content is 5 × 10 ¹⁶cm ^-3;

(5d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, strained sige layer grows the intrinsic relaxation Si cap layers that a layer thickness is 5nm, form PMOS device active area;

(5e) utilize wet etching, etch away the layer SiO on surface ₂.

Step 6, prepared by shallow-trench isolation.

(6a) photoetching Chang Yang district, utilizes dry etch process, etches in isolated area the shallow slot that the degree of depth is 0.3 μm;

(6b) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂;

(6c) by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation.

Step 7, prepared by MOS device grid and light dope source and drain (LDD).

(7a) at 300 DEG C, the method deposit HfO of atomic layer chemical vapor deposit (ALCVD) is used on the active area ₂layer, thickness is 6nm, as the gate medium of nmos device and PMOS device;

(7b) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, the Poly-SiGe of deposit one deck intrinsic on gate dielectric layer, thickness is 100nm, Ge component is 10%;

(7c) photoetching MOS device gate medium and grid polycrystalline, form grid;

(7d) photoetching nmos device active area, carries out N-type ion implantation to nmos device active area, and forming doping content is 1 × 10 ¹⁸cm ^-3n-type lightly-doped source drain structure (N-LDD) region;

(7e) photoetching PMOS device active area, carries out P type ion implantation to PMOS device active area, and forming doping content is 1 × 10 ¹⁸cm ^-3p type lightly-doped source drain structure (P-LDD) region.

Step 8, MOS device is formed.

(8a) utilize chemical vapor deposition (CVD) method, at 600 DEG C, deposit one thickness is the SiO of 3nm over the entire substrate ₂layer;

(8b) dry etch process is utilized, eating away this layer of SiO ₂, retain nmos device and PMOS device grid curb wall;

(8c) photoetching nmos device active area, carries out N-type ion implantation in nmos device active area, and autoregistration generates the source of nmos device, drain region and grid;

(8d) photoetching PMOS device active area, carries out N-type ion implantation in PMOS device active area, and autoregistration generates the source of PMOS device, drain region and grid.

Step 9, forms BiCMOS integrated circuit.

(9a) by chemical vapor deposition (CVD) method, at 600 DEG C, the SiO that deposit 300nm is thick over the entire substrate ₂layer;

(9b) photoetching lead-in wire window, sputters layer of metal titanium (Ti), alloy over the entire substrate, and autoregistration forms metal silicide, the metal that clean surface is unnecessary, forms Metal Contact;

(9c) splash-proofing sputtering metal, photoetching goes between, form the drain electrode of the source electrode of nmos device, gate electrode, drain electrode and PMOS device, source electrode, gate electrode respectively, and bipolar transistor emitter pole, base metal are drawn, collector electrode metal goes between, final MOS device forms the mix-crystal facial plane strain BiCMOS integrated device and circuit that conducting channel is 22nm.

Embodiment 2: preparation 30nm mix-crystal facial plane strain BiCMOS integrated device and circuit, concrete steps are as follows:

Step 1, prepared by SOI substrate material.

(1a) choosing N-type doping content is 3 × 10 ¹⁵cm ^-3si sheet, crystal face is (110), is oxidized its surface, and oxidated layer thickness is 0.75 μm, as the basis material on upper strata, and in this basis material hydrogen injecting;

(1b) choosing P type doping content is 3 × 10 ¹⁵cm ^-3si sheet, crystal face is (100), is oxidized its surface, and oxidated layer thickness is 0.75 μm, as the basis material of lower floor;

(1c) adopt chemico-mechanical polishing (CMP) technique, respectively polishing is carried out to the upper strata active layer substrate material surface after lower floor and hydrogen injecting;

(1d) by the lower floor after polishing and upper strata substrate material surface SiO ₂relatively be close to, be placed in ultra-high vacuum environment and realize bonding at 400 DEG C of temperature;

(1e) substrate temperature after bonding is raised 150 DEG C, make the hydrogen place fracture that upper strata basis material is injecting, the part unnecessary to upper strata basis material is peeled off, and retains the Si material of 150nm, and carry out chemico-mechanical polishing (CMP) at this break surface, form soi structure.

Step 2, isolation preparation.

(2a) photoetching bipolar device active area, epitaxial growth one deck doping content is 5 × 10 ¹⁶cm ^-3si layer, thickness is 150nm, as collector region;

(2b) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface deposit one deck SiO ₂;

(2c) photoetching isolated area, utilizes dry etch process, etches in isolated area the deep trouth that the degree of depth is 3 μm;

(2d) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at deep trouth inner surface deposit SiO ₂layer, all covers deep trouth inner surface;

(2e) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, SiO in deep trouth ₂on layer, the layer of deposit layer of sin again, all covers deep trouth inner surface;

(2f) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in deep trouth, fill SiO ₂, utilize chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form deep trench isolation.

Step 3, prepared by bipolar device.

(3a) contact zone, photoetching collector region, carries out the injection of N-type impurity to collector region, and at 900 DEG C, annealing 45min activator impurity, forming doping content is 5 × 10 ¹⁹cm ^-3heavy doping collector electrode;

(3b) at substrate surface thermal oxidation one SiO ₂layer, photoetching base, carries out the injection of p type impurity to base, and at 900 DEG C, annealing 45min activator impurity, forming doping content is 3 × 10 ¹⁸cm ^-3base;

(3c) at substrate surface thermal oxidation one SiO ₂layer, photoetching emitter region, carries out the injection of N-type impurity to substrate, and at 900 DEG C, annealing 45min activator impurity, becomes doping content to be 1 × 10 ²⁰cm ^-3highly doped emitter, form bipolar transistor;

(3d) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 700 DEG C, deposit one SiO ₂layer.

Step 4, prepared by nmos device district.

(4a) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface deposit one deck SiO ₂;

(4b) photoetching nmos device active area, utilizes dry etch process, in nmos device active area, etches the deep trouth that the degree of depth is 2.3 μm, oxide layer is carved thoroughly;

(4c) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, in deep trouth, grow the P type Si resilient coating that a layer thickness is 300nm along (100) crystal face, doping content is 3 × 10 ¹⁵cm ^-3;

(4d) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, P type resilient coating grows the SiGe that a layer thickness is the P type Ge component trapezoidal profile of 1.7 μm, bottom Ge component is 0%, and top is 20%, and doping content is 3 × 10 ¹⁵cm ^-3;

(4e) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, the SiGe layer of Ge component trapezoidal profile grows the P type SiGe layer that a layer thickness is 300nm, and Ge component is 20%, and doping content is 1 × 10 ¹⁷cm ^-3;

(4f) utilize chemical vapor deposition (CVD) method, at 700 DEG C, growing a layer thickness is on the sige layer the strained si layer/of 15nm, and doping content is 1 × 10 ¹⁷cm ^-3, as the raceway groove of nmos device;

(4g) utilize wet etching, etch away the layer SiO on surface ₂.

Step 5, prepared by PMOS device district.

(5a) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface deposit one deck SiO ₂;

(5b) photoetching PMOS device active area, utilizes the method for chemical vapor deposition (CVD), and at 700 DEG C, grow along (110) crystal face the N-type Si resilient coating that a layer thickness is 300nm in PMOS device active area, doping content is 1 × 10 ¹⁷cm ^-3;

(5c) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, Si resilient coating grows the P type SiGe layer that a layer thickness is 15nm, and Ge component is 20%, and doping content is 1 × 10 ¹⁷cm ^-3;

(5d) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, strained sige layer grows the intrinsic relaxation Si cap layers that a layer thickness is 4nm, form PMOS device active area;

(5e) utilize wet etching, etch away the layer SiO on surface ₂.

Step 6, prepared by shallow-trench isolation.

(6a) photoetching Chang Yang district, utilizes dry etch process, etches in isolated area the shallow slot that the degree of depth is 0.4 μm;

(6b) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in shallow slot, fill SiO ₂;

(6c) by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation.

Step 7, prepared by MOS device grid and light dope source and drain (LDD).

(7a) at 350 DEG C, the method deposit HfO of atomic layer chemical vapor deposit (ALCVD) is used on the active area ₂layer, thickness is 8nm, as the gate medium of nmos device and PMOS device;

(7b) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, the Poly-SiGe of deposit one deck intrinsic on gate dielectric layer, thickness is 300nm, Ge component is 20%;

(7c) photoetching MOS device gate medium and grid polycrystalline, form grid;

(7d) photoetching nmos device active area, carries out N-type ion implantation to nmos device active area, and forming doping content is 3 × 10 ¹⁸cm ^-3n-type lightly-doped source drain structure (N-LDD) region;

(7e) photoetching PMOS device active area, carries out P type ion implantation to PMOS device active area, and forming doping content is 3 × 10 ¹⁸cm ^-3p type lightly-doped source drain structure (P-LDD) region.

Step 8, MOS device is formed.

(8a) utilize chemical vapor deposition (CVD) method, at 700 DEG C, deposit one thickness is the SiO of 4nm over the entire substrate ₂layer;

(8b) dry etch process is utilized, eating away this layer of SiO ₂, retain nmos device and PMOS device grid curb wall;

(8c) photoetching nmos device active area, carries out N-type ion implantation in nmos device active area, and autoregistration generates the source of nmos device, drain region and grid;

(8d) photoetching PMOS device active area, carries out N-type ion implantation in PMOS device active area, and autoregistration generates the source of PMOS device, drain region and grid.

Step 9, forms BiCMOS integrated circuit.

(9a) by chemical vapor deposition (CVD) method, at 700 DEG C, the SiO that deposit 400nm is thick over the entire substrate ₂layer;

(9b) photoetching lead-in wire window, sputters layer of metal titanium (Ti), alloy over the entire substrate, and autoregistration forms metal silicide, the metal that clean surface is unnecessary, forms Metal Contact;

(9c) splash-proofing sputtering metal, photoetching goes between, form the drain electrode of the source electrode of nmos device, gate electrode, drain electrode and PMOS device, source electrode, gate electrode respectively, and bipolar transistor emitter pole, base stage, collector electrode metal lead-in wire, final MOS device forms the mix-crystal facial plane strain BiCMOS integrated device and circuit that conducting channel is 30nm.

Embodiment 3: preparation 45nm mix-crystal facial plane strain BiCMOS integrated device and circuit, concrete steps are as follows:

Step 1, prepared by SOI substrate material.

(1a) choosing N-type doping content is 5 × 10 ¹⁵cm ^-3si sheet, crystal face is (110), is oxidized its surface, and oxidated layer thickness is 1 μm, as the basis material on upper strata, and in this basis material hydrogen injecting;

(1b) choosing P type doping content is 5 × 10 ¹⁵cm ^-3si sheet, crystal face is (100), is oxidized its surface, and oxidated layer thickness is 1 μm, as the basis material of lower floor;

(1c) adopt chemico-mechanical polishing (CMP) technique, respectively under layer by layer with hydrogen injecting after upper strata substrate material surface carry out polishing;

(1d) by the lower floor after polishing and upper strata substrate material surface SiO ₂relatively be close to, be placed in ultra-high vacuum environment and realize bonding at 480 DEG C of temperature;

(1e) substrate temperature after bonding is raised 100 DEG C, make the hydrogen place fracture that upper strata basis material is injecting, the part unnecessary to upper strata basis material is peeled off, and retains the Si material of 200nm, and carry out chemico-mechanical polishing (CMP) at this break surface, form soi structure.

Step 2, isolation preparation.

(2a) photoetching bipolar device active area, epitaxial growth one deck doping content is 1 × 10 ¹⁷cm ^-3si layer, thickness is 200nm, as collector region;

(2b) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit one deck SiO ₂;

(2c) photoetching isolated area, utilizes dry etch process, etches in isolated area the deep trouth that the degree of depth is 3.5 μm;

(2d) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at deep trouth inner surface deposit SiO ₂layer, all covers deep trouth inner surface;

(2e) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, SiO in deep trouth ₂on layer, the layer of deposit layer of sin again, all covers deep trouth inner surface;

(2f) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in deep trouth, fill SiO ₂, utilize chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form deep trench isolation.

Step 3, prepared by bipolar device.

(3a) contact zone, photoetching collector region, carries out the injection of N-type impurity to collector region, and at 950 DEG C, annealing 30min activator impurity, forming doping content is 1 × 10 ²⁰cm ^-3heavy doping collector electrode;

(3b) at substrate surface thermal oxidation one SiO ₂layer, photoetching base, carries out the injection of p type impurity to base, and at 950 DEG C, annealing 30min activator impurity, forming doping content is 5 × 10 ¹⁸cm ^-3base;

(3c) at substrate surface thermal oxidation one SiO ₂layer, photoetching emitter region, carries out the injection of N-type impurity to substrate, and at 950 DEG C, annealing 30min activator impurity, becomes doping content to be 5 × 10 ²⁰cm ^-3highly doped emitter, form bipolar transistor;

(3d) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 800 DEG C, deposit one SiO ₂layer.

Step 4, prepared by nmos device district.

(4a) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit one deck SiO ₂;

(4b) photoetching nmos device active area, utilizes dry etch process, in nmos device active area, etches the deep trouth that the degree of depth is 2.9 μm, oxide layer is carved thoroughly;

(4c) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in deep trouth, grow the P type Si resilient coating that a layer thickness is 400nm along (100) crystal face, doping content is 5 × 10 ¹⁵cm ^-3;

(4d) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, P type resilient coating grows the SiGe that a layer thickness is the P type Ge component trapezoidal profile of 2.1 μm, bottom Ge component is 0%, and top is 25%, and doping content is 5 × 10 ¹⁵cm ^-3;

(4e) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, the SiGe layer of Ge component trapezoidal profile grows the P type SiGe layer that a layer thickness is 400nm, and Ge component is 25%, and doping content is 5 × 10 ¹⁷cm ^-3;

(4f) utilize chemical vapor deposition (CVD) method, at 750 DEG C, growing a layer thickness is on the sige layer the strained si layer/of 8nm, and doping content is 5 × 10 ¹⁷cm ^-3, as the raceway groove of nmos device;

(4g) utilize wet etching, etch away the layer SiO on surface ₂.

Step 5, prepared by PMOS device district.

(5a) chemical vapor deposition chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit one deck SiO ₂;

(5b) photoetching PMOS device active area, utilizes the method for chemical vapor deposition (CVD), and at 750 DEG C, grow along (110) crystal face the N-type Si resilient coating that a layer thickness is 400nm in PMOS device active area, doping content is 5 × 1017cm ^-3;

(5c) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, Si resilient coating grows the P type SiGe layer that a layer thickness is 8nm, and Ge component is 25%, and doping content is 5 × 10 ¹⁷cm ^-3;

(5d) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, strained sige layer grows the intrinsic relaxation Si cap layers that a layer thickness is 3nm, form PMOS device active area;

(5e) utilize wet etching, etch away the layer SiO on surface ₂.

Step 6, prepared by shallow-trench isolation.

(6a) photoetching Chang Yang district, utilizes dry etch process, etches in isolated area the shallow slot that the degree of depth is 0.5 μm;

(6b) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in shallow slot, fill SiO ₂;

(6c) by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation.

Step 7, prepared by MOS device grid and light dope source and drain (LDD).

(7a) at 400 DEG C, the method deposit HfO of atomic layer chemical vapor deposit (ALCVD) is used on the active area ₂layer, thickness is 10nm, as the gate medium of nmos device and PMOS device;

(7b) chemical vapor deposition (CVD) method is utilized, at 750 DEG C, the Poly-SiGe of deposit one deck intrinsic on gate dielectric layer, thickness is 500nm, Ge component is 30%;

(7c) photoetching MOS device gate medium and grid polycrystalline, form grid;

(7d) photoetching nmos device active area, carries out N-type ion implantation to nmos device active area, and forming doping content is 5 × 10 ¹⁸cm ^-3n-type lightly-doped source drain structure (N-LDD) region;

(7e) photoetching PMOS device active area, carries out P type ion implantation to PMOS device active area, and forming doping content is 5 × 10 ¹⁸cm ^-3p type lightly-doped source drain structure (P-LDD) region.

Step 8, MOS device is formed.

(8a) utilize chemical vapor deposition (CVD) method, at 800 DEG C, deposit one thickness is the SiO of 5nm over the entire substrate ₂layer;

(8b) dry etch process is utilized, eating away this layer of SiO ₂, retain nmos device and PMOS device grid curb wall;

(8c) photoetching nmos device active area, carries out N-type ion implantation in nmos device active area, and autoregistration generates the source of nmos device, drain region and grid;

(8d) photoetching PMOS device active area, carries out N-type ion implantation in PMOS device active area, and autoregistration generates the source of PMOS device, drain region and grid.

Step 9, forms BiCMOS integrated circuit.

(9a) by chemical vapor deposition (CVD) method, at 800 DEG C, the SiO that deposit 500nm is thick over the entire substrate ₂layer;

(9b) photoetching lead-in wire window, sputters layer of metal titanium (Ti), alloy over the entire substrate, and autoregistration forms metal silicide, the metal that clean surface is unnecessary, forms Metal Contact;

(9c) splash-proofing sputtering metal, photoetching goes between, form the drain electrode of the source electrode of nmos device, gate electrode, drain electrode and PMOS device, source electrode, gate electrode respectively, and bipolar transistor emitter pole, base stage, collector electrode metal lead-in wire, final MOS device forms the mix-crystal facial plane strain BiCMOS integrated device and circuit that conducting channel is 45nm.

The mixing crystal face strain mix-crystal facial plane strain BiCMOS integrated device that the embodiment of the present invention provides and preparation method's tool have the following advantages:

1. the mix-crystal facial plane that prepared by the present invention strains in BiCMOS integrated device and circuit and have employed SOI substrate, reduces the power consumption of device and circuit, improves the reliability of device and circuit;

2. the mix-crystal facial plane that prepared by the present invention strains BiCMOS integrated device and circuit have employed mixing crystal face substrate technology, namely on same substrate slice, be distributed with (100) and (110) these two kinds of crystal faces, on (100) crystal face, electron mobility is the highest, and for hole, (110) the highest on crystal face, for 2.5 times on (100) crystal face, present invention incorporates two kinds of crystal faces that carrier mobility reaches the highest simultaneously, when not reducing a kind of mobility of charge carrier of types of devices, the mobility of the charge carrier of another kind of types of devices can be improved;

3. the mix-crystal facial plane that prepared by the present invention strains BiCMOS integrated device and circuit, adopt selective epitaxial technology, respectively in nmos device and PMOS device active area selective growth tensile strain Si and compressive strain sige material, nmos device and the electric property such as PMOS device frequency performance and current driving ability are obtained promote, thus cmos device and performance of integrated circuits obtain enhancing simultaneously;

4. the mix-crystal facial plane that prepared by the present invention strains MOS device in BiCMOS integrated device and circuit structure and have employed the HfO of high-k ₂as gate medium, improve the grid-control ability of MOS device, enhance the electric property of NMOS and PMOS device;

5. it is quantum well devices that the mix-crystal facial plane that prepared by the present invention strains PMOS device in BiCMOS integrated device and circuit structure, namely strain SiGe channel layer is between Si cap layers and body Si layer, compared with surface channel device, this device can reduce channel interface scattering effectively, improves device electrology characteristic; Meanwhile, quantum well can make the problem in hot electron injection grid medium improve, and adds the reliability of device and circuit;

6. the present invention prepares in mix-crystal facial plane strain BiCMOS integrated device and circuit technology, adopt Poly-SiGe material as gate electrode, its work function changes with the change of Ge component, by regulating Ge component in Poly-SiGe, realizing CMOS threshold voltage can continuous setup, decrease processing step, reduce technology difficulty;

7. it is 800 DEG C that the mix-crystal facial plane that prepared by the present invention strains the maximum temperature related in BiCMOS integrated device and circuitry processes, lower than the technological temperature causing strained Si channel stress relaxation, therefore this preparation method can keep strained Si channel stress effectively, improves the performance of integrated circuit;

8. the mix-crystal facial plane that prepared by the present invention strains in BiCMOS integrated device and circuit, bipolar device adopts the collector region thickness of SOI substrate thin compared with traditional devices, therefore, there is collector region effect extending transversely in this device, and two dimensional electric field can be formed in collector region, thus improve reverse breakdown voltage and the Early voltage of this device, under identical breakdown characteristics, there is the characteristic frequency more excellent than traditional devices.The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.

Claims (3)

1. a preparation method for mix-crystal facial plane strain BiCMOS integrated device, is characterized in that, comprise the steps:

The first step, choose two panels Si sheet, one piece is N-type doping content is 1 ~ 5 × 10 ¹⁵cm ^-3si (110) substrate slice, as the basis material of upper strata active layer, another block is P type doping content is 1 ~ 5 × 10 ¹⁵cm ^-3si (100) substrate slice, as the basis material of lower floor's active layer; Be oxidized two panels Si sheet surface, oxidated layer thickness is 0.5 ~ 1 μm, adopts chemico-mechanical polishing (CMP) technique to carry out polishing to two oxide layer surfaces;

Second step, to hydrogen injecting in the active layer basis material of upper strata, and two panels Si sheet oxide layer is placed in ultra-high vacuum environment relatively at the temperature of 350 ~ 480 DEG C and realizes bonding; Si sheet temperature after bonding is raised 100 ~ 200 DEG C, make the hydrogen place fracture that upper strata basis material is injecting, the part unnecessary to upper strata basis material is peeled off, and retains the Si material of 100 ~ 200nm, and carry out chemico-mechanical polishing (CMP) at its break surface, form SOI substrate;

3rd step, photoetching bipolar device active area, epitaxial growth one deck doping content is 1 × 10 ¹⁶~ 1 × 10 ¹⁷cm ^-3si layer, thickness is 100 ~ 200nm, as collector region;

4th step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO ₂, photoetching isolated area, utilizes dry etch process, etches in isolated area the deep trouth that the degree of depth is 2.5 ~ 3.5 μm, utilizes chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin, deep trouth inner surface is all covered, last deposit SiO ₂fill up in deep trouth, form deep trench isolation;

5th step, contact zone, photoetching collector region, carry out the injection of N-type impurity to collector region, and at 800 ~ 950 DEG C, annealing 30 ~ 90min activator impurity, forming doping content is 1 × 10 ¹⁹~ 1 × 10 ²⁰the heavy doping collector electrode of cm-3;

6th step, at substrate surface thermal oxidation one SiO ₂layer, photoetching base, carries out the injection of p type impurity to base, and at 800 ~ 950 DEG C, annealing 30 ~ 90min activator impurity, forming doping content is 1 × 10 ¹⁸~ 5 × 10 ¹⁸cm ^-3base;

7th step, at substrate surface thermal oxidation one SiO ₂layer, photoetching emitter region, carries out the injection of N-type impurity to substrate, and at 800 ~ 950 DEG C, annealing 30 ~ 90min activator impurity, forming doping content is 5 × 10 ¹⁹~ 5 × 10 ²⁰cm ^-3highly doped emitter, utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ~ 800 DEG C, deposit one SiO ₂layer;

8th step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO ₂, photoetching nmos device active area, utilizes dry etch process, in nmos device active area, etches the deep trouth that the degree of depth is 1.7 ~ 2.9 μm, the oxide layer of centre is carved thoroughly; Utilize chemical vapor deposition (CVD) method, at 600 ~ 750 DEG C, selective epitaxial growth four layer material on the nmos device active area of (100) crystal face substrate: the P type Si resilient coating of ground floor to be thickness be 200 ~ 400nm, doping content is 1 ~ 5 × 10 ¹⁵cm ^-3; The P type SiGe graded bedding of the second layer to be thickness be 1.3 ~ 2.1nm, this layer of bottom Ge component is 0%, and top Ge component is 15 ~ 25%, and doping content is 1 ~ 5 × 10 ¹⁵cm ^-3; Third layer is Ge component is 15 ~ 25%, and thickness is the P type SiGe layer of 200 ~ 400nm, and doping content is 0.5 ~ 5 × 10 ¹⁷cm ^-3, the P type strained si layer/of the 4th layer of to be thickness be 8 ~ 20nm, doping content is 0.5 ~ 5 × 10 ¹⁷cm ^-3, as the raceway groove of nmos device; Utilize wet etching, etch away the layer SiO on surface ₂;

9th step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO ₂photoetching PMOS device active area, utilizes chemical vapor deposition (CVD) method, at 600 ~ 750 DEG C, selective epitaxial growth trilaminate material on PMOS device active area: the N-type Si resilient coating of ground floor to be thickness be 100 ~ 200nm, doping content is 0.5 ~ 5 × 10 ¹⁷cm ^-3, the N-type SiGe strained layer of the second layer to be thickness be 8 ~ 20nm, Ge component is 15 ~ 25%, and doping content is 0.5 ~ 5 × 10 ¹⁷cm ^-3, as the raceway groove of PMOS device; The intrinsic relaxation Si cap layers of third layer to be thickness be 3 ~ 5nm, forms PMOS device active area; Utilize wet etching, etch away the layer SiO on surface ₂;

Tenth step, photoetching Chang Yang district, utilize dry etch process, and oxygen district on the scene etches the shallow slot that the degree of depth is 0.3 ~ 0.5 μm; Recycling chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, fills SiO in shallow slot ₂; Finally, by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation;

11 step, at 300 ~ 400 DEG C, use the method deposit HfO of atomic layer chemical vapor deposit (ALCVD) on the active area ₂layer, thickness is 6 ~ 10nm, as the gate medium of nmos device and PMOS device, recycling chemical vapor deposition (CVD) method, at 600 ~ 750 DEG C, on gate dielectric layer deposit a layer thickness be the intrinsic Poly-SiGe of 100 ~ 500nm as gate electrode, Ge component is 10 ~ 30%; Photoetching NMOS and PMOS device gate medium and grid polycrystalline, form grid;

12 step, photoetching nmos device active area, carry out N-type ion implantation to nmos device active area, and forming doping content is 1 ~ 5 × 10 ¹⁸cm ^-3n-type lightly-doped source drain structure (N-LDD) region; Photoetching PMOS device active area, carries out P type ion implantation to PMOS device active area, and forming doping content is 1 ~ 5 × 10 ¹⁸cm ^-3p type lightly-doped source drain structure (P-LDD) region;

13 step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, deposit one thickness is the SiO of 3 ~ 5nm over the entire substrate ₂layer, falls this layer of SiO with dry etching ₂, form nmos device and PMOS device grid curb wall;

14 step, photoetching nmos device active area, carry out N-type ion implantation in nmos device active area, and autoregistration generates the source region of nmos device, drain region and grid; Photoetching PMOS device active area, carries out N-type ion implantation in PMOS device active area, and autoregistration generates the source region of PMOS device, drain region and grid;

15 step, use chemical vapor deposition (CVD) method over the entire substrate, at 600 ~ 800 DEG C, the SiO that deposit 300 ~ 500nm is thick ₂layer; Make lead-in wire window by lithography, sputter layer of metal titanium (Ti) over the entire substrate, alloy, autoregistration forms metal silicide, the metal that clean surface is unnecessary, forms metal electrode, forms the mix-crystal facial plane strain BiCMOS integrated device that MOS device conducting channel is 22 ~ 45nm.

2. preparation method according to claim 1, is characterized in that, the channel length of NMOS and PMOS device gets 22 ~ 45nm.

3. a preparation method for mix-crystal facial plane strain BiCMOS integrated circuit, is characterized in that, comprise the steps:

Step 1, implementation method prepared by SOI substrate material is:

(1a) choosing N-type doping content is 1 × 10 ¹⁵cm ^-3si sheet, crystal face is (110), is oxidized its surface, and oxidated layer thickness is 0.5 μm, as the basis material on upper strata, and in this basis material hydrogen injecting;

(1b) choosing P type doping content is 1 × 10 ¹⁵cm ^-3si sheet, crystal face is (100), is oxidized its surface, and oxidated layer thickness is 0.5 μm, as the basis material of lower floor;

(1c) adopt chemico-mechanical polishing (CMP) technique, respectively polishing is carried out to the upper strata substrate material surface after lower floor and hydrogen injecting;

(1d) by the lower floor after polishing and upper strata substrate material surface SiO ₂relatively be close to, be placed in ultra-high vacuum environment and realize bonding at 350 DEG C of temperature;

(1e) substrate temperature after bonding is raised 200 DEG C, make the hydrogen place fracture that upper strata basis material is injecting, the part unnecessary to upper strata basis material is peeled off, and retains the Si material of 100nm, and carry out chemico-mechanical polishing (CMP) at this break surface, form soi structure;

Step 2, the implementation method of isolation preparation is:

(2a) photoetching bipolar device active area, epitaxial growth one deck doping content is 1 × 10 ¹⁶cm ^-3si layer, thickness is 100nm, as collector region;

(2b) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit one deck SiO ₂;

(2c) photoetching isolated area, utilizes dry etch process, etches in isolated area the deep trouth that the degree of depth is 2.5 μm;

(2d) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at deep trouth inner surface deposit SiO ₂layer, all covers deep trouth inner surface;

(2e) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, SiO in deep trouth ₂on layer, the layer of deposit layer of sin again, all covers deep trouth inner surface;

(2f) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in deep trouth, fill SiO ₂, utilize chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form deep trench isolation;

Step 3, implementation method prepared by bipolar device is:

(3a) contact zone, photoetching collector region, carries out the injection of N-type impurity to collector region, and at 800 DEG C, annealing 90min activator impurity, forming doping content is 1 × 10 ¹⁹cm ^-3heavy doping collector electrode;

(3b) at substrate surface thermal oxidation one SiO ₂layer, photoetching base, carries out the injection of p type impurity to base, and at 800 DEG C, annealing 90min activator impurity, forming doping content is 1 × 10 ¹⁸cm ^-3base;

(3c) at substrate surface thermal oxidation one SiO ₂layer, photoetching emitter region, carries out the injection of N-type impurity to substrate, and at 800 DEG C, annealing 90min activator impurity, becomes doping content to be 5 × 10 ¹⁹cm ^-3highly doped emitter, form bipolar transistor;

(3d) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 DEG C, deposit one SiO ₂layer;

Step 4, implementation method prepared by nmos device district is:

(4a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit one deck SiO ₂;

(4b) photoetching nmos device active area, utilizes dry etch process, in nmos device active area, etches the deep trouth that the degree of depth is 1.7 μm, oxide layer is carved thoroughly;

(4c) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, in deep trouth, grow the P type Si resilient coating that a layer thickness is 200nm along (100) crystal face, doping content is 1 × 10 ¹⁵cm ^-3;

(4d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, P type resilient coating grows the SiGe that a layer thickness is the P type Ge component trapezoidal profile of 1.3 μm, bottom Ge component is 0%, and top is 15%, and doping content is 1 × 10 ¹⁵cm ^-3;

(4e) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, the SiGe layer of Ge component trapezoidal profile grows the P type SiGe layer that a layer thickness is 200nm, and Ge component is 15%, and doping content is 5 × 10 ¹⁶cm ^-3;

(4f) utilize chemical vapor deposition (CVD) method, at 600 DEG C, growing a layer thickness is on the sige layer the strained si layer/of 20nm, and doping content is 5 × 10 ¹⁶cm ^-3, as the raceway groove of nmos device;

(4g) utilize wet etching, etch away the layer SiO on surface ₂;

Step 5, implementation method prepared by PMOS device district is:

(5a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit one deck SiO ₂;

(5b) photoetching PMOS device active area, utilizes the method for chemical vapor deposition (CVD), and at 600 DEG C, grow along (110) crystal face the N-type Si resilient coating that a layer thickness is 200nm in PMOS device active area, doping content is 5 × 10 ¹⁶cm ^-3;

(5c) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, Si resilient coating grows the P type SiGe layer that a layer thickness is 20nm, and Ge component is 15%, and doping content is 5 × 10 ¹⁶cm ^-3;

(5d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, strained sige layer grows the intrinsic relaxation Si cap layers that a layer thickness is 5nm, form PMOS device active area;

(5e) utilize wet etching, etch away the layer SiO on surface ₂;

Step 6, implementation method prepared by shallow-trench isolation is:

(6a) photoetching Chang Yang district, utilizes dry etch process, etches in isolated area the shallow slot that the degree of depth is 0.3 μm;

(6b) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂;

(6c) by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation;

Step 7, implementation method prepared by MOS device grid and light dope source and drain (LDD) is:

(7a) at 300 DEG C, the method deposit HfO of atomic layer chemical vapor deposit (ALCVD) is used on the active area ₂layer, thickness is 6nm, as the gate medium of nmos device and PMOS device;

(7b) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, the Poly-SiGe of deposit one deck intrinsic on gate dielectric layer, thickness is 100nm, Ge component is 10%;

(7c) photoetching MOS device gate medium and grid polycrystalline, form grid;

(7d) photoetching nmos device active area, carries out N-type ion implantation to nmos device active area, and forming doping content is 1 × 10 ¹⁸cm ^-3n-type lightly-doped source drain structure (N-LDD) region;

(7e) photoetching PMOS device active area, carries out P type ion implantation to PMOS device active area, and forming doping content is 1 × 10 ¹⁸cm ^-3p type lightly-doped source drain structure (P-LDD) region;

Step 8, the implementation method that MOS device is formed is:

(8a) utilize chemical vapor deposition (CVD) method, at 600 DEG C, deposit one thickness is the SiO of 3nm over the entire substrate ₂layer;

(8b) dry etch process is utilized, eating away this layer of SiO ₂, retain nmos device and PMOS device grid curb wall;

(8c) photoetching nmos device active area, carries out N-type ion implantation in nmos device active area, and autoregistration generates the source of nmos device, drain region and grid;

(8d) photoetching PMOS device active area, carries out N-type ion implantation in PMOS device active area, and autoregistration generates the source of PMOS device, drain region and grid;

Step 9, the implementation method forming BiCMOS integrated circuit is:

(9a) by chemical vapor deposition (CVD) method, at 600 DEG C, the SiO that deposit 300nm is thick over the entire substrate ₂layer;

(9b) photoetching lead-in wire window, sputters layer of metal titanium (Ti), alloy over the entire substrate, and autoregistration forms metal silicide, the metal that clean surface is unnecessary, forms Metal Contact;

(9c) splash-proofing sputtering metal, photoetching goes between, form the drain electrode of the source electrode of nmos device, gate electrode, drain electrode and PMOS device, source electrode, gate electrode respectively, and bipolar transistor emitter pole, base metal are drawn, collector electrode metal goes between, final MOS device forms the mix-crystal facial plane strain BiCMOS integrated device and circuit that conducting channel is 22nm.