CN102738165B - A planar strain BiCMOS integrated mixing device and method for preparing a crystal plane - Google Patents

A planar strain BiCMOS integrated mixing device and method for preparing a crystal plane Download PDF

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CN102738165B
CN102738165B CN201210244430.9A CN201210244430A CN102738165B CN 102738165 B CN102738165 B CN 102738165B CN 201210244430 A CN201210244430 A CN 201210244430A CN 102738165 B CN102738165 B CN 102738165B
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张鹤鸣
李妤晨
宋建军
胡辉勇
宣荣喜
吕懿
舒斌
郝跃
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西安电子科技大学
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Abstract

本发明公开了一种混合晶面平面应变BiCMOS集成器件及电路制备方法。 The present invention discloses a hybrid crystal planes BiCMOS integrated circuit device and a method for preparing strain. 其过程为:制备一片SOI衬底,上层的基体材料为(110)晶面,下层的基体材料为(100)晶面;在双极器件区域制造常规的Si双极晶体管;在NMOS器件区域,选择性生长晶面为(100)的应变Si外延层,制备应变Si沟道NMOS器件;在PMOS器件有源区的区域,选择性生长晶面为(110)的应变SiGe外延层,制备沟道的压应变SiGe沟道PMOS器件;光刻引线,构成MOS器件导电沟道为22~45nm的混合晶面平面应变BiCMOS集成器件;本发明充分了利用张应变Si材料电子迁移率高于体Si材料和压应变SiGe材料电子迁移率高于体Si材料以及迁移率各向异性的特点,基于SOI衬底,制备出了性能增强的混合晶面平面应变BiCMOS集成器件及电路。 The procedure is: SOI substrate for preparing an upper layer of the base material (110) plane, the underlying base material (100) crystal face; Si bipolar transistor manufactured in a conventional bipolar device region; in the NMOS device regions, selective growth of crystal face (100) epitaxial layer of strained Si, strained Si channel NMOS device prepared; in the region of the active area of ​​the PMOS device, the selective growth of crystal face (110) strained SiGe epitaxial layer, a channel prepared compressive strain in the SiGe channel PMOS device; photolithography leads constituting a conductive channel MOS device integrated BiCMOS device is strained mixed crystal planes 22 ~ 45nm; the invention fully tensile strained Si material using a high electron mobility material to form Si strain and high electron mobility SiGe material on a bulk Si material and the pressure characteristics of mobility anisotropy, based on an SOI substrate, a performance-enhancing prepared mixed crystal planes strain and BiCMOS integrated circuit devices.

Description

一种混合晶面平面应变BiCMOS集成器件及制备方法 A planar strain BiCMOS integrated mixing device and method for preparing a crystal plane

技术领域 FIELD

[0001] 本发明属于半导体集成电路技术领域,尤其涉及一种混合晶面应变混合晶面平面应变BiCMOS集成器件及制备方法。 [0001] The present invention belongs to the technical field of semiconductor integrated circuit, particularly to a mixed crystal strained mixed crystal surface planes BiCMOS integrated devices strain and a preparation method.

背景技术 Background technique

[0002] 在信息技术高度发展的当代,以集成电路为代表的微电子技术是信息技术的关键。 [0002] In the present highly developed information technology, integrated circuit as the representative of microelectronics technology is the key to information technology. 集成电路作为人类历史上发展最快、影响最大、应用最广泛的技术,其已成为衡量一个国家科学技术水平、综合国力和国防力量的重要标志。 Integrated circuit as the fastest growing in human history, most influential, the most widely used technology, it has become an important indicator of a country's scientific and technological level, comprehensive national strength and national defense forces.

[0003] 对微电子产业发展产生巨大影响的“摩尔定律”指出:集成电路芯片上的晶体管数目,约每18个月增加1倍,性能也提升1倍。 [0003] a huge impact on the development of the microelectronics industry, "Moore's Law" states: the number of transistors on an integrated circuit chip, approximately doubling every 18 months, but also enhance the performance doubled. 40多年来,世界微电子产业始终按照这条定律不断地向前发展,电路规模已由最初的小规模发展到现在的超大规模;Si材料以其优异的性能,在微电子产业中一直占据着重要的地位,而以Si材料为基础的CMOS集成电路以低功耗、低噪声、高输入阻抗、高集成度、可靠性好等优点在集成电路领域中占据着主导地位。 For over 40 years, the world's microelectronics industry has always been in accordance with this law continue to move forward, the circuit scale has been the first small-scale development to the present ultra-large scale; Si material for its excellent performance in the microelectronics industry has been dominated by an important position, and the Si material-based CMOS integrated circuits with low power consumption, low noise, high input impedance, high integration, reliability and good occupy a dominant position in the field of integrated circuits.

[0004] 随着器件特征尺寸的逐步减小,尤其是进入纳米尺度以后,微电子技术的发展越来越逼近材料、技术、器件的极限,面临着巨大的挑战。 [0004] With the gradual reduction in feature size devices, especially after entering the nano-scale, the development of microelectronics technology, more and more approaching limit of the material, technology, device, faces enormous challenges. 当器件特征尺寸缩小到65纳米以后,M0S器件中的短沟效应、强场效应、量子效应、寄生参量的影响、工艺参数涨落等问题对器件泄漏电流、亚阈特性、开态/关态电流等性能的影响越来越突出;而且随着无线移动通信的飞速发展,对器件和集成电路的性能,如频率特性、噪声特性、封装面积、功耗和成本等提出了更高的要求,传统硅基工艺制备的器件和集成电路越来越无法满足新型、高速电子系统的需求。 As device feature sizes down to 65 nm after the short channel effect M0S devices, intense field, quantum effects, influence of the parasitic parameters, process parameters and so on fluctuations of device leakage current, subthreshold characteristics of the on-state / off-state affect the performance of other more prominent current; and with the rapid development of wireless mobile communication, the device and performance of integrated circuits, such as frequency characteristics, noise characteristics, package size, cost and power requirements of a higher, devices and integrated circuits made of traditional silicon-based technology can not meet the growing demand for new, high-speed electronic systems.

[0005] CMOS集成电路的一个重要性能指标,是NM0S和PM0S器件的驱动能力,而电子和空穴的迀移率分别是决定其驱动能力的关键因素之一;为了提高NM0S器件和PM0S器件的性能进而提尚CMOS集成电路的性能,两种载流子的迁移率都应当尽可能地尚。 [0005] An important performance CMOS integrated circuit, and the drive capability NM0S PM0S devices, and electrons and holes Gan shift rate is one of the key factors that determine the driving ability respectively; NM0S order to improve the device and the device PM0S performance and thus improve the performance of CMOS integrated circuit yet, migration rate of the two carriers should be possible yet.

[0006] 早在上世纪五十年代,就已经研究发现在硅材料上施加应力,会改变电子和空穴的迀移率,从而改变半导体材料上所制备的NM0S和PM0S器件的性能;但电子和空穴并不总是对同种应力做出相同的反应;同时,在相同的晶面上制备NM0S器件和PM0S器件,它们的迀移率并不能同时达到最优。 [0006] As early as the 1950's, it has been found that stress applied to the silicon material, electrons and holes will change Gan drift rate, and thereby alter the performance NM0S PM0S devices produced on a semiconductor material; however, the electronic and holes are not always the same reaction to make the same kinds of stress; the same time, the device prepared in the same NM0S crystal device and PM0S surface thereof Gan shift rate and at the same time is not optimal.

[0007]由于Si材料载流子材料迀移率较低,所以采用Si BiCMOS技术制造的集成电路性能,尤其是频率性能,受到了极大的限制。 [0007] Since Si material carrier material Gan drift rate is low, so the performance of integrated circuits using Si BiCMOS technology manufacturing, in particular, frequency performance, has been greatly limited.

[0008] 为此,要在不降低一种类型器件的载流子的迀移率的情况下,提高另一种类型器件的载流子的迀移率,本专利提出一种应变技术制备CM0S,即应变混合晶面平面应变BiCMOS集成器件及电路的制备。 [0008] For this reason, in the case Gan to one type of device without lowering the carrier shift rate, increase the carrier device of another type Gan drift rate, this patent proposes a technique for preparing a strain CM0S , i.e. plane strain prepared by mixing BiCMOS integrated circuit devices and a crystal plane strain.

发明内容 SUMMARY

[0009] 本发明的目的在于提供一种混合晶面平面应变BiCMOS集成器件及制备方法,以实现在不改变现有设备和增加成本的条件下,导电沟道为22〜45nm的混合晶面平面应变BiCMOS集成器件及电路。 [0009] The object of the present invention is to provide a hybrid crystal planes BiCMOS integrated devices and strain preparation method, to achieve without changing the existing condition of equipment and cost increase, as the conduction channel of the mixed crystal planes 22~45nm BiCMOS integrated circuit devices and strain.

[0010] 本发明的目的在于提供一种混合晶面平面应变BiCMOS集成器件及电路,NM0S器件为应变Si平面沟道,PM0S器件为应变SiGe平面沟道,双极器件为Si SOI BJT。 [0010] The object of the present invention is to provide a hybrid crystal planes strain BiCMOS integrated circuit devices and, NM0S planar channel device is strained Si, strained SiGe PMOS device is a flat channel, the bipolar device is a Si SOI BJT.

[0011] 进一步、NMOS器件的导电沟道是张应变Si材料,NM0S器件的导电沟道为平面沟道。 [0011] Further, the conductive channel NMOS device is tensile strained Si material, conductive channel NM0S planar channel devices.

[0012] 进一步、PMOS器件的导电沟道是压应变SiGe材料,PM0S器件的导电沟道为平面沟道。 [0012] Further, the conductive channel PMOS devices is compressively strained SiGe material, conductive channel PM0S planar channel devices.

[0013] 进一步、NM0S器件和PM0S器件的晶面不同,其中NM0S器件的晶面为(100),PM0S器件的晶面为(110)。 [0013] Further, the device and PM0S device NM0S different crystal faces, wherein the crystal plane NM0S device is (100) crystal plane PM0S device (110).

[0014] 进一步、PM0S器件采用量子阱结构。 [0014] Further, PM0S device using a quantum well structure.

[0015] 进一步、双极器件衬底为S0I材料。 [0015] Further, the substrate is a bipolar device S0I material.

[0016] 本发明的另一目的在于提供一种混合晶面平面应变BiCMOS集成器件的制备方法,包括如下步骤: [0016] Another object of the present invention is to provide a method for preparing a mixed crystal planes strain BiCMOS integrated device, comprising the steps of:

[0017] 第一步、选取两片Si片,一块是N型掺杂浓度为1〜5X1015cm3的Si (110)衬底片,作为上层有源层的基体材料,另一块是P型掺杂浓度为1〜5X1015cm3的Si (100)衬底片,作为下层有源层的基体材料;对两片Si片表面进行氧化,氧化层厚度为0.5~1 μπι,采用化学机械抛光(CMP)工艺对两个氧化层表面进行抛光; [0017] The first step, select two Si wafer, an N type doping concentration of 1~5X1015cm3 Si (110) substrate sheet, as the base material of the upper layer of the active layer, the other is a P-type dopant concentration 1~5X1015cm3 the Si (100) substrate sheet, as a lower layer of the active layer, the base material; two on the sheet surface oxidized Si, the oxide layer having a thickness of 0.5 ~ 1 μπι, chemical mechanical polishing (CMP) process of two oxide polishing the surface layer;

[0018] 第二步、对上层有源层基体材料中注入氢,并将两片Si片氧化层相对置于超高真空环境中在350〜480°C的温度下实现键合;将键合后的Si片温度升高100〜200°C,使上层基体材料在注入的氢处断裂,对上层基体材料多余的部分进行剥离,保留100~200nm的Si材料,并在其断裂表面进行化学机械抛光(CMP),形成S0I衬底; [0018] The second step, a hydrogen implanted layer of the upper layer of the active matrix material, and the two Si wafer disposed opposite the oxide layer to achieve ultra-high vacuum environment at a temperature of bonding of 350~480 ° C; the bonded the Si substrate temperature is raised 100~200 ° C, the base material of the upper layer at the hydrogen injected at the fracture, the material of the upper layer of excess base part peeled ~ 200nm retention material 100 is Si, and a chemical mechanical fracture surface thereof polishing (CMP), the substrate is formed S0I;

[0019] 第三步、光刻双极器件有源区,外延生长一层掺杂浓度为IX 1016〜lX1017cm3的Si层,厚度为100〜200nm,作为集电区; [0019] The third step, photolithography bipolar device active region, the doping concentration of the epitaxial growth layer 1016~lX1017cm3 IX Si layer of a thickness of 100~200nm, a collector region;

[0020] 第四步、利用化学汽相淀积(CVD)方法,在600〜800°C,在衬底表面淀积一层Si02,光刻隔离区,利用干法刻蚀工艺,在隔离区刻蚀出深度为2.5〜3.5 μπι的深槽,利用化学汽相淀积(CVD)方法,在600〜800°C,在衬底表面淀积一层Si02和一层SiN,将深槽内表面全部覆盖,最后淀积Si02将深槽内填满,形成深槽隔离; [0020] The fourth step, by chemical vapor deposition (CVD) method, at 600~800 ° C, depositing a layer of Si02, photolithography isolation region on the substrate surface by a dry etching process, the isolation region 2.5~3.5 μπι etched deep groove depth, using a chemical vapor deposition (CVD) method, at 600~800 ° C, depositing a layer of SiN and Si02 on the substrate surface, the inner surface of the deep groove to cover all of the last deposited Si02 fills deep trench, forming deep trench isolation;

[0021] 第五步、光刻集电区接触区,对集电区进行N型杂质的注入,并在800〜950°C,退火30〜90min激活杂质,形成掺杂浓度为1 X 1019〜1 X 10 20cm-3的重掺杂集电极; [0021] The fifth step, photolithography collector region contact area, implanting a collector region of N-type impurities, and the impurities are activated 30~90min at 800~950 ° C, annealing, forming a doping concentration of 1 X 1019~ 1 X 10 20cm-3 a heavily doped collector;

[0022] 第六步、在衬底表面热氧化一S1jl,光刻基区,对基区进行P型杂质的注入,并在800〜950°C,退火30〜90min激活杂质,形成掺杂浓度为IX 1018〜5X10 18cm 3的基区; [0022] a sixth step of thermally oxidizing the surface of the substrate in a S1jl, the lithographic base, the base region implanting P-type impurities, and the impurities are activated at 30~90min 800~950 ° C, annealing, dopant concentration formed IX is a group of region 1018~5X10 18cm 3;

[0023] 第七步、在衬底表面热氧化一S1jl,光刻发射区,对衬底进行N型杂质的注入,并在800〜950°C,退火30〜90min激活杂质,形成掺杂浓度为5X 1019~ 5X 10 20cm 3的重掺杂发射区,在衬底表面利用化学汽相淀积(CVD)的方法,在600〜800°C,淀积一S1jl ; [0023] In a seventh step, the surface of the substrate in a thermal oxidation S1jl, photolithography emitting region, the substrate is implanted N-type impurities, and the impurities are activated 30~90min at 800~950 ° C, annealing, dopant concentration formed a heavily doped emitter region of 5X 1019 ~ 5X 10 20cm 3, the surface of the substrate by chemical vapor deposition (CVD) method, at 600~800 ° C, depositing a S1jl;

[0024] 第八步、利用化学汽相淀积(CVD)方法,在600〜800°C,在衬底表面淀积一层Si02,光刻NM0S器件有源区,利用干法刻蚀工艺,在NM0S器件有源区,刻蚀出深度为1.7〜 [0024] The eighth step, using a chemical vapor deposition (CVD) method, at 600~800 ° C, a layer of Si02 is deposited on the substrate surface, the active device region NM0S photolithography, a dry etching process, in NM0S device active regions, etched depth is 1.7~

2.9 μπι的深槽,将中间的氧化层刻透;利用化学汽相淀积(CVD)方法,在600〜750°C,在 2.9 μπι deep groove, will be carved through the intermediate oxide layer; using a chemical vapor deposition (CVD) method, at 600~750 ° C, in

(100)晶面衬底的NM0S器件有源区上选择性外延生长四层材料:第一层是厚度为200〜400nm的P型Si缓冲层,掺杂浓度为1〜5X 1015cm 3;第二层是厚度为1.3〜2.lnm的P型SiGe渐变层,该层底部Ge组分是0 %,顶部Ge组分是15〜25 %,掺杂浓度为1〜5 X 1015cm 3;第三层是Ge组分为15〜25 %,厚度为200〜400nm的P型SiGe层,掺杂浓度为0.5〜5X 1017cm 3;第四层是厚度为8〜20nm的P型应变Si层,掺杂浓度为0.5〜5X1017cm 3,作为NMOS器件的沟道;利用湿法腐蚀,刻蚀掉表面的层Si02; NM0S selective epitaxial growth on the active device region (100) crystal plane of the substrate material of four layers: a first layer having a thickness of 200~400nm P-type Si buffer layer, the doping concentration of 1~5X 1015cm 3; second P-type layer having a thickness of the SiGe graded layer 1.3~2.lnm, the bottom layer is a Ge content of 0%, the top of the Ge content is 15~25%, a doping concentration of 1~5 X 1015cm 3; third layer Ge component is 15~25%, a thickness of 200~400nm P-type SiGe layer, the doping concentration of 0.5~5X 1017cm 3; fourth layer having a thickness of the strained Si layer 8~20nm P-type doped concentration is 0.5~5X1017cm 3, the channel of an NMOS device; using a wet etching, etching away the surface of the Si02 layer;

[0025] 第九步、利用化学汽相淀积(CVD)方法,在600〜800°C,在衬底表面淀积一层Si02,光刻PM0S器件有源区,利用化学汽相淀积(CVD)方法,在600〜750°C,在PM0S器件有源区上选择性外延生长三层材料:第一层是厚度为100〜200nm的N型Si缓冲层,掺杂浓度为0.5〜5X 1017cm 3,第二层是厚度为8〜20nm的N型SiGe应变层,Ge组分是15〜25%,掺杂浓度为0.5〜5X 1017cm 3,作为PM0S器件的沟道,第三层是厚度为3〜5nm的本征弛豫Si帽层,形成PM0S器件有源区;利用湿法腐蚀,刻蚀掉表面的层Si02; [0025] The ninth step, by chemical vapor deposition (CVD) method, at 600~800 ° C, a layer of Si02 is deposited on the substrate surface, the photolithography PM0S device active region, by chemical vapor deposition ( CVD) method, at 600~750 ° C, three selective epitaxial growth material on PM0S device active regions: a first layer having a thickness of 100~200nm N-type Si buffer layer, the doping concentration 0.5~5X 1017cm 3, the second layer having a thickness of N-type SiGe strained layer of 8~20nm, Ge component is 15~25%, a doping concentration of 0.5~5X 1017cm 3, as the channel PM0S device, a thickness of the third layer 3~5nm intrinsic relaxed Si cap layer, forming an active region PM0S device; using a wet etching, etching away the surface of the Si02 layer;

[0026] 第十步、光刻场氧区,利用干法刻蚀工艺,在场氧区刻蚀出深度为0.3〜0.5 μπι的浅槽;再利用化学汽相淀积(CVD)方法,在600〜800°C,在浅槽内填充Si02;最后,用化学机械抛光(CMP)方法,除去多余的氧化层,形成浅槽隔离; [0026] The tenth step, the field oxide regions photolithography, a dry etching process, the field oxide regions etched depth is shallow groove 0.3~0.5 μπι; then using a chemical vapor deposition (CVD) method, at 600 ~800 ° C, filling the shallow grooves Si02; Finally, chemical mechanical polishing (CMP) process to remove excess oxide layer, forming a shallow trench isolation;

[0027] 第^^一步、在300〜400°C,在有源区上用原子层化学汽相淀积(ALCVD)的方法淀积HfOjl,厚度为6〜10nm,作为NM0S器件和PM0S器件的栅介质,再利用化学汽相淀积(CVD)方法,在600〜750°C,在栅介质层上淀积一层厚度为100〜500nm的本征Poly-SiGe作为栅电极,Ge组分为10〜30% ;光刻NM0S和PM0S器件栅介质与栅多晶,形成栅极; [0027] ^^ first step, at 300~400 ° C, on the active region by the method of atomic layer chemical vapor deposition (ALCVD) deposited HfOjl, thickness 6~10nm, as NM0S devices and devices PM0S gate dielectric, and then using a chemical vapor deposition (CVD) method, at 600~750 ° C, is deposited to a thickness of 100~500nm intrinsic Poly-SiGe gate electrode, Ge component on the gate dielectric layer 10~30%; NM0S lithography devices and PM0S gate dielectric and the gate poly, the gate is formed;

[0028] 第十二步、光刻NM0S器件有源区,对NM0S器件有源区进行N型离子注入,形成掺杂浓度为1〜5X 10lscm 3的N型轻掺杂源漏结构(N-LDD)区域;光刻PM0S器件有源区,对PM0S器件有源区进行P型离子注入,形成掺杂浓度为1〜5X 10lscm 3的P型轻掺杂源漏结构(P-LDD)区域; [0028] The twelfth step, photolithography NM0S device active region, the active region of the device NM0S N-type ion implantation, is formed 1~5X N-type doping concentration of the lightly doped source and drain 10lscm 3 structure (N- LDD) regions; lithography PM0S device active region, the active region of the device PM0S P-type ion implantation, is formed 1~5X P-type doping concentration of the lightly doped source and drain 10lscm 3 structure (P-LDD) regions;

[0029] 第十三步、利用化学汽相淀积(CVD)方法,在600〜800°C,在整个衬底上淀积一厚度为3〜5nm的S1jl,用干法刻蚀掉这层S1 2,形成NM0S器件和PM0S器件栅极侧墙; [0029] The thirteenth step, using a chemical vapor deposition (CVD) method, at 600~800 ° C, a thickness of S1jl 3~5nm deposited over the entire substrate, which layer is etched away by a dry S1 2, and the device is formed NM0S PM0S device gate spacer;

[0030] 第十四步、光刻NM0S器件有源区,在NM0S器件有源区进行N型离子注入,自对准生成NM0S器件的源区、漏区和栅极;光刻PM0S器件有源区,在PM0S器件有源区进行N型离子注入,自对准生成PM0S器件的源区、漏区和栅极; [0030] The fourteenth step, photolithography NM0S active device region, N-type ion implantation NM0S device active region, generating a self-aligned device NM0S source, drain and gate regions; lithography device active PM0S region, in the active device region PM0S N-type ion implantation, a self-aligned source region PM0S generating device, a drain region and a gate;

[0031] 第十五步、在整个衬底上用化学汽相淀积(CVD)方法,在600〜800°C,淀积300〜500nm厚的S1jg ;光刻出引线窗口,在整个衬底上派射一层金属钛(Ti ),合金,自对准形成金属娃化物,清洗表面多余的金属,形成金属电极,构成M0S器件导电沟道为22〜45nm的混合晶面平面应变BiCMOS集成器件。 [0031] step 15, over the entire substrate by chemical vapor deposition (CVD) method, at 600~800 ° C, the deposition thickness of 300~500nm S1jg; lithograph lead window, the entire substrate send the outgoing layer of titanium (Ti), alloys, forming self-aligned metal compound baby, to clean the surface excess metal, a metal electrode constituting the conductive channel device M0S strain BiCMOS integrated device is of the mixed crystal planes 22~45nm .

[0032] 进一步、沟道长度取22〜45nm。 [0032] Further, the channel lengths are 22~45nm.

[0033] 进一步、该制备方法中所涉及的最高温度根据化学汽相淀积(CVD)工艺温度决定,最高温度小于等于800°C。 [0033] Further, the maximum temperature of the production method involved in the chemical vapor deposition (CVD) process temperature is determined, equal to a maximum temperature of less than 800 ° C.

[0034] 本发明的另一目的在于提供一种混合晶面平面应变BiCMOS集成电路的制备方法,包括如下步骤: [0034] Another object of the present invention is to provide a method for preparing a mixed crystal planes strain BiCMOS integrated circuit, comprising the steps of:

[0035] 步骤1,S0I衬底材料制备的实现方法为: [0035] Step 1, to realize a method of preparing the substrate material S0I:

[0036] (la)选取N型掺杂浓度为1 X 1015cm 3的Si片,晶面为(110),对其表面进行氧化,氧化层厚度为0.5 μ m,作为上层的基体材料,并在该基体材料中注入氢; [0036] (la) selected N-type dopant concentration of 1 X 1015cm Si sheet 3, crystal faces (110), the surface thereof is oxidized, the oxide layer having a thickness of 0.5 μ m, as an upper base material, and the matrix material is injected hydrogen;

[0037] (lb)选取P型掺杂浓度为1 X 1015cm 3的Si片,晶面为(100),对其表面进行氧化,氧化层厚度为0.5 μ m,作为下层的基体材料; [0037] (lb) selected P-type dopant concentration of 1 X 1015cm Si sheet 3, crystal faces (100), the surface thereof is oxidized, the oxide layer having a thickness of 0.5 μ m, the lower layer as a base material;

[0038] (lc)采用化学机械抛光(CMP)工艺,分别对下层和注入氢后的上层基体材料表面进行抛光处理; [0038] (lc) by chemical mechanical polishing (CMP) process, respectively the lower surface of the upper base material and the hydrogen injection polished;

[0039] (Id)将抛光处理后的下层和上层基体材料表面S1jg对紧贴,置于超高真空环境中在350°C温度下实现键合; [0039] (Id) of the lower layer after the polishing process and the surface of the material base to close the upper S1jg placed ultra-high vacuum environment to achieve bonding at a temperature of 350 ° C;

[0040] (le)将键合后的基片温度升高200°C,使上层基体材料在注入的氢处断裂,对上层基体材料多余的部分进行剥离,保留lOOnm的Si材料,并在该断裂表面进行化学机械抛光(CMP),形成SOI结构; [0040] (le) The substrate temperature after bonding increases 200 ° C, the upper layer base material in a hydrogen injected at the fracture of the material surplus upper base part peeled retained Si material lOOnm and the fracture surface chemical mechanical polishing (CMP), forming an SOI structure;

[0041] 步骤2,隔离制备的实现方法为: [0041] Step 2, to achieve isolation methods of preparation:

[0042] (2a)光刻双极器件有源区,外延生长一层掺杂浓度为lX1016cm3的Si层,厚度为lOOnm,作为集电区; [0042] (2a) of the bipolar device active region lithography, epitaxial growth of a layer of a doping concentration of lX1016cm3 Si layer with a thickness of lOOnm, as a collector region;

[0043] (2b)利用化学汽相淀积(CVD)方法,在600°C,在衬底表面淀积一层Si02; [0043] (2b) by chemical vapor deposition (CVD) method at 600 ° C, a layer of Si02 is deposited on the substrate surface;

[0044] (2c)光刻隔离区,利用干法刻蚀工艺,在隔离区刻蚀出深度为2.5 μπι的深槽; [0044] (2c) lithography isolation region by a dry etch process, the etch depth of 2.5 μπι deep trench isolation region;

[0045] (2d)利用化学汽相淀积(CVD)方法,在600°C,在深槽内表面淀积S1jl,将深槽内表面全部覆盖; Using [0045] (2d) chemical vapor deposition (CVD) method at 600 ° C, in the deep groove surface S1jl deposited, covering the entire surface of the deep trench;

[0046] (2e)利用化学汽相淀积(CVD)方法,在600°C,在深槽内S1jl上再淀积一层SiN层,将深槽内表面全部覆盖; [0046] (2e) using a chemical vapor deposition (CVD) method at 600 ° C, in the deep trench S1jl then depositing a SiN layer, covering the entire surface of the deep trench;

[0047] (2f)利用化学汽相淀积(CVD)方法,在600°C,在深槽内填充Si02,利用化学机械抛光(CMP)方法,除去多余的氧化层,形成深槽隔离; [0047] (2f) by chemical vapor deposition (CVD) method at 600 ° C, filled in the deep trench Si02, using chemical mechanical polishing (CMP) process to remove excess oxide layer, forming deep trench isolation;

[0048] 步骤3,双极器件制备的实现方法为: [0048] Step 3, methods of making bipolar device implemented as:

[0049] (3a)光刻集电区接触区,对集电区进行N型杂质的注入,并在800°C,退火90min激活杂质,形成掺杂浓度为IX 1019cm 3的重掺杂集电极; [0049] (3a) lithography collector region contact area, implanting a collector region of N-type impurities, and the impurities are activated 90min at 800 ° C, annealing, forming a doping concentration of the heavily doped collector IX 1019cm 3 ;

[0050] (3b)在衬底表面热氧化一S1jl,光刻基区,对基区进行P型杂质的注入,并在800°C,退火90min激活杂质,形成掺杂浓度为lX10lscm3的基区; [0050] (3b) thermally oxidizing the surface of the substrate in a S1jl, the lithographic base, the base region implanting P-type impurities, and the impurities are activated 90min at 800 ° C, annealing, forming a doping concentration of the base region lX10lscm3 ;

[0051] (3c)在衬底表面热氧化一S1jl,光刻发射区,对衬底进行N型杂质的注入,并在800°C,退火90min激活杂质,成掺杂浓度为5 X 1019cm 3的重掺杂发射区,构成双极晶体管; [0051] (3c) on a substrate surface of the thermal oxidation S1jl, photolithography emitting region, the substrate is implanted N-type impurities, and the impurities are activated 90min at 800 ° C, annealing, to a doping concentration 5 X 1019cm 3 a heavily doped emitter region of the bipolar transistor configuration;

[0052] (3d)在衬底表面利用化学汽相淀积(CVD)的方法,在600°C,淀积一S1jl ; [0052] (3d) on the substrate surface by chemical vapor deposition (CVD) method at 600 ° C, depositing a S1jl;

[0053] 步骤4,NM0S器件区制备的实现方法为: [0053] Step 4, to achieve a method for the preparation of the device region NM0S:

[0054] (4a)利用化学汽相淀积(CVD)方法,在600°C,在衬底表面淀积一层Si02; [0054] (4a) using a chemical vapor deposition (CVD) method at 600 ° C, a layer of Si02 is deposited on the substrate surface;

[0055] (4b)光刻NM0S器件有源区,利用干法刻蚀工艺,在NM0S器件有源区,刻蚀出深度为1.7 μπι的深槽,将氧化层刻透; [0055] (4b) NM0S active device region photolithography, dry etching process, a device active region NM0S, 1.7 μπι etched depth of the deep grooves carved through the oxide layer;

[0056] (4c)利用化学汽相淀积(CVD)的方法,在600°C,在深槽内沿(100)晶面生长一层厚度为200nm的P型Si缓冲层,掺杂浓度为1 X 1015cm 3; [0056] Method (4c) using a chemical vapor deposition (CVD), and at 600 ° C, in the deep trench along the (100) crystal plane grown to a thickness of 200nm P-type Si buffer layer, a doping concentration of 1 X 1015cm 3;

[0057] (4d)利用化学汽相淀积(CVD)的方法,在600°C,P型缓冲层上生长一层厚度为1.3 μπι的P型Ge组分梯形分布的SiGe,底部Ge组分为0%,顶部为15%,掺杂浓度为1 X 1015cm 3; [0057] (4d) using a chemical vapor deposition (CVD) method, on a 600 ° C, P-type buffer layer is grown to a thickness of the P-type SiGe 1.3 μπι trapezoidal Ge content profile, the bottom of the Ge content 0%, the top 15%, a doping concentration of 1 X 1015cm 3;

[0058] (4e)利用化学汽相淀积(CVD)的方法,在600°C,在Ge组分梯形分布的SiGe层上生长一层厚度为200nm的P型SiGe层,Ge组分为15%,掺杂浓度为5X 1016cm 3; [0058] (4e) a method using a chemical vapor deposition (CVD), and at 600 ° C, grown to a thickness of 200nm P-type SiGe layer on a SiGe layer trapezoidal Ge content profile, Ge component 15 %, a doping concentration of 5X 1016cm 3;

[0059] (4f)利用化学汽相淀积(CVD)方法,在600°C,在SiGe层上生长一层厚度为20nm的应变Si层,掺杂浓度为5X 1016cm 3,作为NM0S器件的沟道; [0059] (4f) by chemical vapor deposition (CVD) method at 600 ° C, grown on the SiGe layer with a thickness of 20nm strained Si layer, the doping concentration of 5X 1016cm 3, the groove as the device NM0S Road;

[0060] (4g)利用湿法腐蚀,刻蚀掉表面的层Si02; [0060] (4g) by wet etching, etching away the surface layer of Si02;

[0061] 步骤5,PM0S器件区制备的实现方法为: [0061] Step 5, prepared by implementation of the device region PM0S:

[0062] (5a)利用化学汽相淀积(CVD)方法,在600°C,在衬底表面淀积一层Si02; [0062] (5a) using a chemical vapor deposition (CVD) method at 600 ° C, a layer of Si02 is deposited on the substrate surface;

[0063] (5b)光刻PM0S器件有源区,利用化学汽相淀积(CVD)的方法,在600°C,在PM0S器件有源区沿(110)晶面生长一层厚度为200nm的N型Si缓冲层,掺杂浓度为5X 1016cm 3; [0063] (5b) of the active device region PM0S lithography, by chemical vapor deposition (CVD) method at 600 ° C, in the active device region along PM0S (110) crystal plane grown to a thickness of 200nm N-type Si buffer layer, the doping concentration of 5X 1016cm 3;

[0064] (5c)利用化学汽相淀积(CVD)的方法,在600°C,在Si缓冲层上生长一层厚度为20nm的P型SiGe层,Ge组分为15%,掺杂浓度为5X 1016cm 3; [0064] (5c) using a chemical vapor deposition (CVD) method at 600 ° C, grown in a thickness of 20nm on the Si buffer layer is P-type SiGe layer, Ge component of 15%, the doping concentration of 5X 1016cm 3;

[0065] (5d)利用化学汽相淀积(CVD)的方法,在600°C,在应变SiGe层上生长一层厚度为5nm的本征弛豫Si帽层,形成PM0S器件有源区; [0065] (5d) using a chemical vapor deposition (CVD) method at 600 ° C, the strain grown on the SiGe layer to a thickness of 5nm intrinsic relaxed Si cap layer formed PM0S device active region;

[0066] (5e)利用湿法腐蚀,刻蚀掉表面的层Si02; [0066] (5e) by wet etching, etching away the surface layer of Si02;

[0067] 步骤6,浅槽隔离制备的实现方法为: [0067] Step 6, to realize a method for the preparation of shallow trench isolation:

[0068] (6a)光刻场氧区,利用干法刻蚀工艺,在隔离区刻蚀出深度为0.3 μπι的浅槽; [0068] (6a) lithography field oxide region, using a dry etch process, the etch depth of 0.3 μπι shallow trench isolation region;

[0069] (6b)利用化学汽相淀积(CVD)方法,在600°C,在浅槽内填充Si02; [0069] (6b) by chemical vapor deposition (CVD) method at 600 ° C, filling the shallow grooves Si02;

[0070] (6c)用化学机械抛光(CMP)方法,除去多余的氧化层,形成浅槽隔离; [0070] (6c) by chemical mechanical polishing (CMP) process to remove excess oxide layer, forming a shallow trench isolation;

[0071] 步骤7,M0S器件栅极与轻掺杂源漏(LDD)制备的实现方法为: [0071] Step 7, M0S device gate lightly doped source and drain implementation (LDD) is prepared:

[0072] (7a)在300 °C,在有源区上用原子层化学汽相淀积(ALCVD)的方法淀积HfOjl,厚度为6nm,作为NM0S器件和PM0S器件的栅介质; [0072] (7a) at 300 ° C, a method on the active region by atomic layer chemical vapor deposition (ALCVD) deposited HfOjl, a thickness of 6nm, and a device NM0S PM0S device gate dielectric;

[0073] (7b)利用化学汽相淀积(CVD)方法,在600°C,在栅介质层上淀积一层本征的Poly-SiGe,厚度为lOOnm,Ge 组分为10% ; [0073] (7b) by chemical vapor deposition (CVD) method at 600 ° C, an intrinsic layer deposited on the gate dielectric layer Poly-SiGe, the thickness of lOOnm, Ge component of 10%;

[0074] (7c)光刻NMOS和PM0S器件栅介质与栅多晶,形成栅极; [0074] (7c) lithography PM0S NMOS device gate dielectric and the gate poly, the gate is formed;

[0075] (7d)光刻NM0S器件有源区,对NM0S器件有源区进行N型离子注入,形成掺杂浓度为1 X 1018cm 3的N型轻掺杂源漏结构(N-LDD)区域; [0075] (7d) NM0S lithographic device active region, the active region of the device NM0S N-type ion implantation, forming a doping concentration of 1 X 1018cm N-type lightly doped source and drain 3 structure (N-LDD) region ;

[0076] (7e)光刻PM0S器件有源区,对PM0S器件有源区进行P型离子注入,形成掺杂浓度为1 X 1018cm 3的P型轻掺杂源漏结构(ρ-LDD)区域; [0076] (7e) PM0S lithographic device active region, the active region of the device PM0S P-type ion implantation, forming a doping concentration of 1 X 1018cm 3 of the P-type lightly doped source drain structure (ρ-LDD) region ;

[0077] 步骤8,M0S器件形成的实现方法为: [0077] Step 8, the device-implemented method M0S formed is:

[0078] (8a)利用化学汽相淀积(CVD)方法,在600°C,在整个衬底上淀积一厚度为3nm的S1jl ; [0078] (8a) by chemical vapor deposition (CVD) method at 600 ° C, a thickness of S1jl 3nm deposited over the entire substrate;

[0079] (8b)利用干法刻蚀工艺,蚀掉这层Si02,保留NM0S器件和PM0S器件栅极侧墙; [0079] (8b) by a dry etching process, etching away this layer of Si02, and retention devices NM0S PM0S gate spacer device;

[0080] (8c)光刻NM0S器件有源区,在NM0S器件有源区进行N型离子注入,自对准生成NM0S器件的源、漏区和栅极; [0080] (8c) lithography NM0S active device region, N-type ion implantation NM0S device active region, generating a self-aligned device NM0S source and drain regions and a gate;

[0081] (8d)光刻PM0S器件有源区,在PM0S器件有源区进行N型离子注入,自对准生成PM0S器件的源、漏区和栅极; [0081] (8d) PM0S lithographic device active region in the device active region PM0S N-type ion implantation, a self-aligned source generates PM0S device, a drain region and a gate;

[0082] 步骤9,构成BiCMOS集成电路的实现方法为: [0082] Step 9, constituting the BiCMOS integrated circuit implementation is:

[0083] (9a)用化学汽相淀积(CVD)方法,在600°C,在整个衬底上淀积300nm厚的Si02层; [0083] (9a) by chemical vapor deposition (CVD) method at 600 ° C, a 300nm-thick layer of Si02 is deposited over the entire substrate;

[0084] (9b)光刻引线窗口,在整个衬底上溅射一层金属钛(Ti),合金,自对准形成金属硅化物,清洗表面多余的金属,形成金属接触; [0084] (9b) leads photolithography window, over the entire substrate sputtering a metallic titanium (Ti), alloys, self-aligned metal silicide formation, excess metal surface cleaning, metal contact is formed;

[0085] (9c)溅射金属,光刻引线,分别形成NMOS器件的源电极、栅电极、漏电极和PMOS器件的漏电极、源电极、栅电极,以及双极晶体管发射极、基极金属引、集电极金属引线,最终M0S器件构成导电沟道为22nm的混合晶面平面应变BiCMOS集成器件及电路。 [0085] (9c) sputtered metal, lead photolithography, forming a source electrode of the NMOS device, the gate electrode a drain, and the drain electrode of the PMOS device, a source electrode, a gate electrode, a bipolar transistor, and an emitter, a base metal lead, a collector metal wire, constituting the conductive channel device M0S final mixed crystal planes 22nm strain and BiCMOS integrated circuit devices.

[0086] 本发明具有如下优点: [0086] The present invention has the following advantages:

[0087] 1.本发明制备的混合晶面平面应变BiCMOS集成器件及电路中采用了SOI衬底,降低了器件与电路的功耗,提高了器件与电路的可靠性; [0087] Preparation of mixed crystal planes of the strain of the present invention 1. The BiCMOS devices and integrated circuits using an SOI substrate, and to reduce the power consumption of the circuit devices, and improve the reliability of the circuit device;

[0088] 2.本发明制备的混合晶面平面应变BiCMOS集成器件及电路采用了混合晶面衬底技术,即在同一个衬底片上分布有(100)和(110)这两种晶面,在(100)晶面上电子迀移率最高,而对于空穴,(110)晶面上最高,为(100)晶面上的2.5倍,本发明结合了载流子迀移率同时达到最高的两种晶面,能在不降低一种类型器件的载流子的迀移率的情况下,提高另一种类型器件的载流子的迀移率; [0088] Preparation of mixed crystal planes of the strain of the present invention 2. The BiCMOS integrated circuit devices and uses a hybrid technique crystal plane of the substrate, i.e., distribution (100) and (110) crystal planes of these two on the same substrate sheet, in the (100) crystal face Gan electronic shifting the highest rate, while for the hole (110) the highest crystal face, a (100) crystal face of 2.5 times, the present invention incorporates the carrier while the highest rate shift Gan the two crystal faces, the case can be reduced without Gan one type of device carrier shift rate, increase the carrier device of another type Gan shift rate;

[0089] 3.本发明制备的混合晶面平面应变BiCMOS集成器件及电路,采用选择性外延技术,分别在NM0S器件和PM0S器件有源区选择性生长张应变Si和压应变SiGe材料,使NM0S器件和PM0S器件频率性能和电流驱动能力等电学性能能够获得同时提升,从而CMOS器件与集成电路性能获得了增强; [0089] Preparation of mixed crystal planes of the strain of the present invention 3. The BiCMOS devices and integrated circuits, selective epitaxy, respectively, in the device and selectively NM0S PM0S device active region grown tensile strained Si and SiGe material compressive strain, so NM0S and electrical performance properties PM0S device frequency and the current driving ability can be obtained while improving, so that the integrated circuit CMOS device performance was enhanced;

[0090] 4.本发明制备的混合晶面平面应变BiCMOS集成器件及电路结构中M0S器件采用了高K值的Hf02作为栅介质,提高了M0S器件的栅控能力,增强了NM0S和PM0S器件的电学性能; [0090] Preparation of mixed crystal planes of the strain of the present invention 4. BiCMOS integrated circuit devices and structures M0S Hf02 device uses as high K gate dielectric, the gate control capability M0S improved devices enhanced NM0S devices and PM0S electrical properties;

[0091] 5.本发明制备的混合晶面平面应变BiCMOS集成器件及电路结构中PM0S器件为量子阱器件,即应变SiGe沟道层处于Si帽层和体Si层之间,与表面沟道器件相比,该器件能有效地降低沟道界面散射,提高了器件电学特性;同时,量子阱可以使热电子注入栅介质中的问题得到改善,增加了器件和电路的可靠性; [0091] Preparation of mixed crystal planes of the strain of the present invention 5. BiCMOS integrated circuit devices and structures PM0S device is a quantum well device, i.e., a strained SiGe channel layer is between the cap layer and the bulk Si Si layer, and the surface channel device compared to the device can effectively reduce the channel interface scattering, improving the electrical characteristics of the device; the same time, the quantum well can make the problem of hot electron injection gate dielectric is improved, increasing the reliability of the devices and circuits;

[0092] 6.本发明制备混合晶面平面应变BiCMOS集成器件及电路工艺中,采用Poly-SiGe材料作为栅电极,其功函数随Ge组分的变化而变化,通过调节Poly-SiGe中Ge组分,实现CMOS阈值电压可连续调整,减少了工艺步骤,降低了工艺难度; Preparing the mixed plane strain BiCMOS integrated circuit devices and processes [0092] 6. The crystal plane as the gate electrode, the work function changes with Ge content varied using Poly-SiGe material by adjusting the Ge content Poly-SiGe minutes, to achieve the threshold voltage CMOS continuously adjustable, reducing the process steps, reduces the difficulty of the process;

[0093] 7.本发明制备的混合晶面平面应变BiCMOS集成器件及电路过程中涉及的最高温度为800°C,低于引起应变Si沟道应力弛豫的工艺温度,因此该制备方法能有效地保持应变Si沟道应力,提高集成电路的性能; [0093] The maximum temperature of the mixed crystal planes 7. The present invention is a strain prepared in BiCMOS integrated circuits and devices involved in the process is 800 ° C, below the stress relaxation caused by strained Si channel process temperature, this method can be prepared holding channel stress strained Si, improve the performance of the integrated circuit;

[0094] 8.本发明制备的混合晶面平面应变BiCMOS集成器件及电路中,双极器件采用S0I衬底的集电区厚度较传统器件薄,因此,该器件存在集电区横向扩展效应,并能够在集电区形成二维电场,从而提高了该器件的反向击穿电压和Early电压,在相同的击穿特性下,具有比传统器件更优异的特征频率。 [0094] Preparation of the mixed crystal planes 8. The present invention is strained and BiCMOS integrated circuit device, the bipolar device is the collector region of the thickness of the substrate sheet S0I than conventional devices, therefore, the presence of lateral spreading effect collector region of the device, capable of forming a two-dimensional electric field and collector region, thereby increasing the reverse breakdown voltage of the device and the Early voltage, at the same breakdown characteristics, having more excellent frequency characteristics than conventional devices.

附图说明 BRIEF DESCRIPTION

[0095] 图1是本发明提供的混合晶面平面应变BiCMOS集成器件制备的工艺流程图。 [0095] FIG. 1 is a mixed crystal of the present invention provides a face plane strain prepared BiCMOS process flow diagram of an integrated device.

具体实施方式 Detailed ways

[0096] 为了使本发明的目的、技术方案及优点更加清楚明白,以下结合附图及实施例,对本发明进行进一步详细说明。 [0096] To make the objectives, technical solutions and advantages of the present invention will become more apparent hereinafter in conjunction with the accompanying drawings and embodiments of the present invention will be further described in detail. 应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。 It should be understood that the specific embodiments described herein are only intended to illustrate the present invention and are not intended to limit the present invention.

[0097] 本发明实施例提供了一种混合晶面平面应变BiCMOS集成器件及电路,NM0S器件为应变Si平面沟道,PM0S器件为应变SiGe平面沟道,双极器件为Si SOI BJT。 Embodiment [0097] The present invention provides a hybrid plane strain BiCMOS integrated circuit devices and crystal plane, NM0S planar channel device is a strained Si, strained SiGe PMOS device is a flat channel, the bipolar device is a Si SOI BJT.

[0098] 作为本发明实施例的一优化方案,NM0S器件的导电沟道是张应变Si材料,NMOS器件的导电沟道为平面沟道。 An optimization scheme [0098] Example embodiments of the present invention, the device is conductive channel NM0S tensile strained Si material, a conductive channel NMOS device is planar channel.

[0099] 作为本发明实施例的一优化方案,PM0S器件的导电沟道是压应变SiGe材料,PM0S器件的导电沟道为平面沟道。 An optimization scheme [0099] Example embodiments of the present invention, the device is conductive channel PM0S compressively strained SiGe material, conductive channel PM0S planar channel devices.

[0100] 作为本发明实施例的一优化方案,PM0S器件的导电沟道是压应变SiGe材料,PM0S器件的导电沟道为平面沟道。 An optimization scheme [0100] Example embodiments of the present invention, the device is conductive channel PM0S compressively strained SiGe material, conductive channel PM0S planar channel devices.

[0101] 作为本发明实施例的一优化方案,PM0S器件采用量子阱结构。 [0101] As an embodiment of the optimization of the present invention, PM0S device using a quantum well structure.

[0102] 作为本发明实施例的一优化方案,双极器件衬底为SOI材料。 An optimization scheme [0102] Example embodiments of the present invention, an SOI substrate material of the bipolar device.

[0103] 以下参照附图1,对本发明混合晶面平面应变BiCMOS集成器件及电路的制备方法工艺流程作进一步详细描述。 [0103] Referring to the drawings 1, a method for preparing a strain BiCMOS integrated circuit devices and the process of the present invention mixed crystal plane described in further detail.

[0104] 实施例1:制备22nm混合晶面平面应变BiCMOS集成器件及电路,具体步骤如下: [0104] Example 1: Preparation of a mixed crystal planes 22nm strain BiCMOS integrated circuit devices and, following these steps:

[0105] 步骤1,S0I衬底材料制备。 [0105] Step 1, S0I prepared substrate material.

[0106] (la)选取N型掺杂浓度为1 X 1015cm 3的Si片,晶面为(110),对其表面进行氧化,氧化层厚度为0.5 μ m,作为上层的基体材料,并在该基体材料中注入氢; [0106] (la) selected N-type dopant concentration of 1 X 1015cm Si sheet 3, crystal faces (110), the surface thereof is oxidized, the oxide layer having a thickness of 0.5 μ m, as an upper base material, and the matrix material is injected hydrogen;

[0107] (lb)选取P型掺杂浓度为1 X 1015cm 3的Si片,晶面为(100),对其表面进行氧化,氧化层厚度为0.5 μ m,作为下层的基体材料; [0107] (lb) selected P-type dopant concentration of 1 X 1015cm Si sheet 3, crystal faces (100), the surface thereof is oxidized, the oxide layer having a thickness of 0.5 μ m, the lower layer as a base material;

[0108] (lc)采用化学机械抛光(CMP)工艺,分别对下层和注入氢后的上层基体材料表面进行抛光处理; [0108] (lc) by chemical mechanical polishing (CMP) process, respectively the lower surface of the upper base material and the hydrogen injection polished;

[0109] (Id)将抛光处理后的下层和上层基体材料表面S1jg对紧贴,置于超高真空环境中在350°C温度下实现键合; [0109] (Id) of the lower layer after the polishing process and the surface of the material base to close the upper S1jg placed ultra-high vacuum environment to achieve bonding at a temperature of 350 ° C;

[0110] (le)将键合后的基片温度升高200°C,使上层基体材料在注入的氢处断裂,对上层基体材料多余的部分进行剥离,保留100nm的Si材料,并在该断裂表面进行化学机械抛光(CMP),形成S0I结构。 [0110] (le) The substrate temperature after bonding increases 200 ° C, the upper layer base material in a hydrogen injected at the fracture of the material surplus upper base part peeled retained Si material 100nm and the fracture surface chemical mechanical polishing (CMP), is formed S0I structure.

[0111] 步骤2,隔离制备。 [0111] Step 2, Preparation of isolated.

[0112] (2a)光刻双极器件有源区,外延生长一层掺杂浓度为lX1016cm3的Si层,厚度为100nm,作为集电区; [0112] (2a) an active device region of the bipolar lithography, epitaxial growth of a layer of a doping concentration of lX1016cm3 Si layer with a thickness of 100 nm or, as a collector region;

[0113] (2b)利用化学汽相淀积(CVD)方法,在600°C,在衬底表面淀积一层Si02; [0113] (2b) by chemical vapor deposition (CVD) method at 600 ° C, a layer of Si02 is deposited on the substrate surface;

[0114] (2c)光刻隔离区,利用干法刻蚀工艺,在隔离区刻蚀出深度为2.5 μπι的深槽; [0114] (2c) lithography isolation region by a dry etch process, the etch depth of 2.5 μπι deep trench isolation region;

[0115] (2d)利用化学汽相淀积(CVD)方法,在600°C,在深槽内表面淀积S1jl,将深槽内表面全部覆盖; Using [0115] (2d) chemical vapor deposition (CVD) method at 600 ° C, in the deep groove surface S1jl deposited, covering the entire surface of the deep trench;

[0116] (2e)利用化学汽相淀积(CVD)方法,在600°C,在深槽内S1jl上再淀积一层SiN层,将深槽内表面全部覆盖; [0116] (2e) using a chemical vapor deposition (CVD) method at 600 ° C, in the deep trench S1jl then depositing a SiN layer, covering the entire surface of the deep trench;

[0117] (2f)利用化学汽相淀积(CVD)方法,在600°C,在深槽内填充Si02,利用化学机械抛光(CMP)方法,除去多余的氧化层,形成深槽隔离。 [0117] (2f) by chemical vapor deposition (CVD) method at 600 ° C, filled in the deep trench Si02, using chemical mechanical polishing (CMP) process to remove excess oxide layer, forming deep trench isolation.

[0118] 步骤3,双极器件制备。 [0118] Step 3. Preparation of bipolar devices.

[0119] (3a)光刻集电区接触区,对集电区进行N型杂质的注入,并在800°C,退火90min激活杂质,形成掺杂浓度为IX 1019cm 3的重掺杂集电极; [0119] (3a) lithography collector region contact area, implanting a collector region of N-type impurities, and the impurities are activated 90min at 800 ° C, annealing, forming a doping concentration of the heavily doped collector IX 1019cm 3 ;

[0120] (3b)在衬底表面热氧化一S1jl,光刻基区,对基区进行P型杂质的注入,并在800°C,退火90min激活杂质,形成掺杂浓度为lX10lscm3的基区; [0120] (3b) thermally oxidizing the surface of the substrate in a S1jl, the lithographic base, the base region implanting P-type impurities, and the impurities are activated 90min at 800 ° C, annealing, forming a doping concentration of the base region lX10lscm3 ;

[0121 ] (3c)在衬底表面热氧化一S1jl,光刻发射区,对衬底进行N型杂质的注入,并在800°C,退火90min激活杂质,成掺杂浓度为5 X 1019cm 3的重掺杂发射区,构成双极晶体管; [0121] (3c) on a substrate surface of the thermal oxidation S1jl, photolithography emitting region, the substrate is implanted N-type impurities, and the impurities are activated 90min at 800 ° C, annealing, to a doping concentration 5 X 1019cm 3 a heavily doped emitter region of the bipolar transistor configuration;

[0122] (3d)在衬底表面利用化学汽相淀积(CVD)的方法,在600°C,淀积一S1jl。 [0122] (3d) on the substrate surface by chemical vapor deposition (CVD) method at 600 ° C, depositing a S1jl.

[0123] 步骤4,NM0S器件区制备。 [0123] Step 4. Preparation of NM0S device region.

[0124] (4a)利用化学汽相淀积(CVD)方法,在600°C,在衬底表面淀积一层Si02; [0124] (4a) using a chemical vapor deposition (CVD) method at 600 ° C, a layer of Si02 is deposited on the substrate surface;

[0125] (4b)光刻NMOS器件有源区,利用干法刻蚀工艺,在NMOS器件有源区,刻蚀出深度为1.7 μπι的深槽,将氧化层刻透; [0125] (4b) lithography NMOS device active region, a dry etching process, the NMOS device active region, a depth of 1.7 μπι etching of deep grooves carved through the oxide layer;

[0126] (4c)利用化学汽相淀积(CVD)的方法,在600°C,在深槽内沿(100)晶面生长一层厚度为200nm的P型Si缓冲层,掺杂浓度为1 X 1015cm 3; [0126] Method (4c) using a chemical vapor deposition (CVD), and at 600 ° C, in the deep trench along the (100) crystal plane grown to a thickness of 200nm P-type Si buffer layer, a doping concentration of 1 X 1015cm 3;

[0127] (4d)利用化学汽相淀积(CVD)的方法,在600°C,P型缓冲层上生长一层厚度为1.3 μπι的P型Ge组分梯形分布的SiGe,底部Ge组分为0%,顶部为15%,掺杂浓度为1 X 1015cm 3; [0127] (4d) using a chemical vapor deposition (CVD) method, on a 600 ° C, P-type buffer layer is grown to a thickness of the P-type SiGe 1.3 μπι trapezoidal Ge content profile, the bottom of the Ge content 0%, the top 15%, a doping concentration of 1 X 1015cm 3;

[0128] (4e)利用化学汽相淀积(CVD)的方法,在600°C,在Ge组分梯形分布的SiGe层上生长一层厚度为200nm的P型SiGe层,Ge组分为15%,掺杂浓度为5X 1016cm 3; [0128] (4e) a method using a chemical vapor deposition (CVD), and at 600 ° C, grown to a thickness of 200nm P-type SiGe layer on a SiGe layer trapezoidal Ge content profile, Ge component 15 %, a doping concentration of 5X 1016cm 3;

[0129] (4f)利用化学汽相淀积(CVD)方法,在600°C,在SiGe层上生长一层厚度为20nm的应变Si层,掺杂浓度为5X 1016cm 3,作为NM0S器件的沟道; [0129] (4f) by chemical vapor deposition (CVD) method at 600 ° C, grown on the SiGe layer with a thickness of 20nm strained Si layer, the doping concentration of 5X 1016cm 3, the groove as the device NM0S Road;

[0130] (4g)利用湿法腐蚀,刻蚀掉表面的层Si02。 [0130] (4g) by wet etching, to etch away the surface layer of Si02.

[0131] 步骤5,PM0S器件区制备。 [0131] Step 5 Preparation PM0S device region.

[0132] (5a)利用化学汽相淀积(CVD)方法,在600°C,在衬底表面淀积一层Si02; [0132] (5a) using a chemical vapor deposition (CVD) method at 600 ° C, a layer of Si02 is deposited on the substrate surface;

[0133] (5b)光刻PM0S器件有源区,利用化学汽相淀积(CVD)的方法,在600°C,在PM0S器件有源区沿(110)晶面生长一层厚度为200nm的N型Si缓冲层,掺杂浓度为5X 1016cm 3; [0133] (5b) of the active device region PM0S lithography, by chemical vapor deposition (CVD) method at 600 ° C, in the active device region along PM0S (110) crystal plane grown to a thickness of 200nm N-type Si buffer layer, the doping concentration of 5X 1016cm 3;

[0134] (5c)利用化学汽相淀积(CVD)的方法,在600°C,在Si缓冲层上生长一层厚度为20nm的P型SiGe层,Ge组分为15%,掺杂浓度为5X 1016cm 3; [0134] (5c) using a chemical vapor deposition (CVD) method at 600 ° C, grown in a thickness of 20nm on the Si buffer layer is P-type SiGe layer, Ge component of 15%, the doping concentration of 5X 1016cm 3;

[0135] (5d)利用化学汽相淀积(CVD)的方法,在600°C,在应变SiGe层上生长一层厚度为5nm的本征弛豫Si帽层,形成PM0S器件有源区; [0135] (5d) using a chemical vapor deposition (CVD) method at 600 ° C, the strain grown on the SiGe layer to a thickness of 5nm intrinsic relaxed Si cap layer formed PM0S device active region;

[0136] (5e)利用湿法腐蚀,刻蚀掉表面的层Si02。 [0136] (5e) by wet etching, to etch away the surface layer of Si02.

[0137] 步骤6,浅槽隔离制备。 [0137] Step 6, was prepared shallow trench isolation.

[0138] (6a)光刻场氧区,利用干法刻蚀工艺,在隔离区刻蚀出深度为0.3 μπι的浅槽; [0138] (6a) lithography field oxide region, using a dry etch process, the etch depth of 0.3 μπι shallow trench isolation region;

[0139] (6b)利用化学汽相淀积(CVD)方法,在600°C,在浅槽内填充Si02; [0139] (6b) by chemical vapor deposition (CVD) method at 600 ° C, filling the shallow grooves Si02;

[0140] (6c)用化学机械抛光(CMP)方法,除去多余的氧化层,形成浅槽隔离。 [0140] (6c) by chemical mechanical polishing (CMP) process to remove excess oxide layer, forming a shallow trench isolation.

[0141] 步骤7,M0S器件栅极与轻掺杂源漏(LDD)制备。 [0141] Step 7, M0S preparation device gate lightly doped source and drain (LDD).

[0142] (7a)在300 °C,在有源区上用原子层化学汽相淀积(ALCVD)的方法淀积HfOjl,厚度为6nm,作为NM0S器件和PM0S器件的栅介质; [0142] (7a) at 300 ° C, a method on the active region by atomic layer chemical vapor deposition (ALCVD) deposited HfOjl, a thickness of 6nm, and a device NM0S PM0S device gate dielectric;

[0143] (7b)利用化学汽相淀积(CVD)方法,在600°C,在栅介质层上淀积一层本征的Poly-SiGe,厚度为100nm,Ge 组分为10% ; [0143] (7b) by chemical vapor deposition (CVD) method at 600 ° C, an intrinsic layer deposited on the gate dielectric layer Poly-SiGe, the thickness of 100nm, Ge component of 10%;

[0144] (7c)光刻M0S器件栅介质与栅多晶,形成栅极; [0144] (7c) lithography device M0S gate dielectric and the gate poly, the gate is formed;

[0145] (7d)光刻NMOS器件有源区,对NMOS器件有源区进行N型离子注入,形成掺杂浓度为1 X 1018cm 3的N型轻掺杂源漏结构(N-LDD)区域; [0145] (7d) lithography NMOS device active region, the active region of the NMOS device N-type ion implantation, forming a doping concentration of 1 X 1018cm N-type lightly doped source and drain 3 structure (N-LDD) region ;

[0146] (7e)光刻PM0S器件有源区,对PM0S器件有源区进行P型离子注入,形成掺杂浓度为1 X 1018cm 3的P型轻掺杂源漏结构(ρ-LDD)区域。 [0146] (7e) PM0S lithographic device active region, the active region of the device PM0S P-type ion implantation, forming a doping concentration of 1 X 1018cm 3 of the P-type lightly doped source drain structure (ρ-LDD) region .

[0147] 步骤8,M0S器件形成。 [0147] Step 8, M0S device is formed.

[0148] (8a)利用化学汽相淀积(CVD)方法,在600°C,在整个衬底上淀积一厚度为3nm的 [0148] (8a) by chemical vapor deposition (CVD) method at 600 ° C, is deposited over the entire substrate to a thickness of 3nm

s1jl; s1jl;

[0149] (8b)利用干法刻蚀工艺,蚀掉这层Si02,保留NM0S器件和PM0S器件栅极侧墙; [0149] (8b) by a dry etching process, etching away this layer of Si02, and retention devices NM0S PM0S gate spacer device;

[0150] (8c)光刻NM0S器件有源区,在NM0S器件有源区进行N型离子注入,自对准生成NM0S器件的源、漏区和栅极; [0150] (8c) lithography NM0S active device region, N-type ion implantation NM0S device active region, generating a self-aligned device NM0S source and drain regions and a gate;

[0151] (8d)光刻PM0S器件有源区,在PM0S器件有源区进行N型离子注入,自对准生成PM0S器件的源、漏区和栅极。 [0151] (8d) PM0S lithographic device active region, N-type ion implantation PM0S device active region, self-aligned source generates PM0S device, the drain region and the gate.

[0152] 步骤9,构成BiCMOS集成电路。 [0152] Step 9, constituting the BiCMOS integrated circuit.

[0153] (9a)用化学汽相淀积(CVD)方法,在600°C,在整个衬底上淀积300nm厚的Si02层; [0153] (9a) by chemical vapor deposition (CVD) method at 600 ° C, a 300nm-thick layer of Si02 is deposited over the entire substrate;

[0154] (9b)光刻引线窗口,在整个衬底上溅射一层金属钛(Ti),合金,自对准形成金属硅化物,清洗表面多余的金属,形成金属接触; [0154] (9b) leads photolithography window, over the entire substrate sputtering a metallic titanium (Ti), alloys, self-aligned metal silicide formation, excess metal surface cleaning, metal contact is formed;

[0155] (9c)溅射金属,光刻引线,分别形成NM0S器件的源电极、栅电极、漏电极和PM0S器件的漏电极、源电极、栅电极,以及双极晶体管发射极、基极金属引、集电极金属引线,最终M0S器件构成导电沟道为22nm的混合晶面平面应变BiCMOS集成器件及电路。 [0155] (9c) of metal sputtering, photolithography leads are formed a drain electrode NM0S source device, the gate electrode, the drain electrode and the source PM0S device, a source electrode, a gate electrode, a bipolar transistor, and an emitter, a base metal lead, a collector metal wire, constituting the conductive channel device M0S final mixed crystal planes 22nm strain and BiCMOS integrated circuit devices.

[0156] 实施例2:制备30nm混合晶面平面应变BiCMOS集成器件及电路,具体步骤如下: [0156] Example 2: 30nm mixing plane strain BiCMOS integrated circuit devices and the preparation of the crystal plane, the following steps:

[0157] 步骤1,S0I衬底材料制备。 [0157] Step 1, S0I prepared substrate material.

[0158] (la)选取N型掺杂浓度为3 X 1015cm 3的Si片,晶面为(110),对其表面进行氧化,氧化层厚度为0.75 μ m,作为上层的基体材料,并在该基体材料中注入氢; [0158] (la) selected N-type dopant concentration of 3 X 1015cm Si sheet 3, crystal faces (110), the surface thereof is oxidized, the oxide layer having a thickness of 0.75 μ m, the upper layer as a base material, and the matrix material is injected hydrogen;

[0159] (lb)选取P型掺杂浓度为3X 1015cm 3的Si片,晶面为(100),对其表面进行氧化,氧化层厚度为0.75 μ m,作为下层的基体材料; [0159] (lb) selected P-type dopant concentration of the Si wafer 3X 1015cm 3, crystal faces (100), the surface thereof is oxidized, the oxide layer having a thickness of 0.75 μ m, the lower layer as a base material;

[0160] (lc)采用化学机械抛光(CMP)工艺,分别对下层和注入氢后的上层有源层基体材料表面进行抛光处理; [0160] (lc) by chemical mechanical polishing (CMP) process, respectively, and the lower layer an upper surface of the base material of the active layer after the polishing process for the hydrogen injection;

[0161] (Id)将抛光处理后的下层和上层基体材料表面S1jg对紧贴,置于超高真空环境中在400°C温度下实现键合; [0161] (Id) of the lower layer after the polishing process and the surface of the material base to close the upper S1jg placed ultra-high vacuum environment to achieve bonding at a temperature of 400 ° C;

[0162] (le)将键合后的基片温度升高150°C,使上层基体材料在注入的氢处断裂,对上层基体材料多余的部分进行剥离,保留150nm的Si材料,并在该断裂表面进行化学机械抛光(CMP),形成S0I结构。 [0162] (le) The substrate temperature after bonding increases 150 ° C, the upper layer base material in a hydrogen injected at the fracture of the material surplus upper base part peeled retained Si material 150nm and the fracture surface chemical mechanical polishing (CMP), is formed S0I structure.

[0163] 步骤2,隔离制备。 [0163] Step 2, Preparation of isolated.

[0164] (2a)光刻双极器件有源区,外延生长一层掺杂浓度为5X1016cm3的Si层,厚度为150nm,作为集电区; [0164] (2a) an active device region of the bipolar lithography, epitaxial growth of a layer of a doping concentration of 5X1016cm3 Si layer with a thickness of 150nm, a collector region;

[0165] (2b)利用化学汽相淀积(CVD)方法,在700°C,在衬底表面淀积一层Si02; [0165] (2b) by chemical vapor deposition (CVD) method at 700 ° C, a layer of Si02 is deposited on the substrate surface;

[0166] (2c)光刻隔离区,利用干法刻蚀工艺,在隔离区刻蚀出深度为3 μπι的深槽; [0166] (2c) lithography isolation region by a dry etch process, an etch depth of 3 μπι deep trench isolation region;

[0167] (2d)利用化学汽相淀积(CVD)方法,在700°C,在深槽内表面淀积S1jl,将深槽内表面全部覆盖; Using [0167] (2d) chemical vapor deposition (CVD) method at 700 ° C, in the deep groove surface S1jl deposited, covering the entire surface of the deep trench;

[0168] (2e)利用化学汽相淀积(CVD)方法,在700°C,在深槽内S1jl上再淀积一层SiN层,将深槽内表面全部覆盖; [0168] (2e) using a chemical vapor deposition (CVD) method at 700 ° C, in the deep trench S1jl then depositing a SiN layer, covering the entire surface of the deep trench;

[0169] (2f)利用化学汽相淀积(CVD)方法,在700°C,在深槽内填充Si02,利用化学机械抛光(CMP)方法,除去多余的氧化层,形成深槽隔离。 [0169] (2f) by chemical vapor deposition (CVD) method at 700 ° C, filled in the deep trench Si02, using chemical mechanical polishing (CMP) process to remove excess oxide layer, forming deep trench isolation.

[0170] 步骤3,双极器件制备。 [0170] Step 3. Preparation of bipolar devices.

[0171] (3a)光刻集电区接触区,对集电区进行N型杂质的注入,并在900°C,退火45min激活杂质,形成掺杂浓度为5X 1019cm 3的重掺杂集电极; [0171] (3a) lithography collector region contact area, implanting a collector region of N-type impurities, and the impurities are activated 45min at 900 ° C, anneal, doping concentration is formed 5X 1019cm 3 heavily doped collector ;

[0172] (3b)在衬底表面热氧化一S1jl,光刻基区,对基区进行P型杂质的注入,并在900°C,退火45min激活杂质,形成掺杂浓度为3 X 10lscm 3的基区; [0172] (3b) thermally oxidizing the surface of the substrate in a S1jl, the lithographic base, the base region implanting P-type impurities, and the impurities are activated 45min at 900 ° C, annealing, forming a doping concentration of 3 X 10lscm 3 a base region;

[0173] (3c)在衬底表面热氧化一S1jl,光刻发射区,对衬底进行N型杂质的注入,并在900°C,退火45min激活杂质,成掺杂浓度为1 X 102°cm 3的重掺杂发射区,构成双极晶体管; [0173] (3c) on a substrate surface of the thermal oxidation S1jl, photolithography emitting region, the substrate is implanted N-type impurities, and the impurities are activated 45min at 900 ° C, annealing, to a doping concentration of 1 X 102 ° cm 3 and the heavily doped emitter region of the bipolar transistor configuration;

[0174] (3d)在衬底表面利用化学汽相淀积(CVD)的方法,在700°C,淀积一S1jl。 [0174] (3d) on the substrate surface by chemical vapor deposition (CVD) method at 700 ° C, depositing a S1jl.

[0175] 步骤4,NM0S器件区制备。 [0175] Step 4. Preparation of NM0S device region.

[0176] (4a)利用化学汽相淀积(CVD)方法,在700°C,在衬底表面淀积一层Si02; [0176] (4a) using a chemical vapor deposition (CVD) method at 700 ° C, a layer of Si02 is deposited on the substrate surface;

[0177] (4b)光刻NMOS器件有源区,利用干法刻蚀工艺,在NM0S器件有源区,刻蚀出深度为2.3 μ m的深槽,将氧化层刻透; [0177] (4b) lithography NMOS device active region by a dry etching process, a device active region NM0S, etched depth of 2.3 μ m deep trench, the oxide layer is patterned through;

[0178] (4c)利用化学汽相淀积(CVD)的方法,在700°C,在深槽内沿(100)晶面生长一层厚度为300nm的P型Si缓冲层,掺杂浓度为3 X 1015cm 3; [0178] (4c) using a chemical vapor deposition (CVD) method at 700 ° C, in the deep trench along the (100) crystal plane grown to a thickness of 300nm P-type Si buffer layer, the doping concentration 3 X 1015cm 3;

[0179] (4d)利用化学汽相淀积(CVD)的方法,在700°C,P型缓冲层上生长一层厚度为1.7 μπι的P型Ge组分梯形分布的SiGe,底部Ge组分为0%,顶部为20%,掺杂浓度为3X1015cm3; [0179] (4d) using a chemical vapor deposition (CVD) method, on a 700 ° C, P-type buffer layer is grown to a thickness of the P-type SiGe 1.7 μπι trapezoidal Ge content profile, the bottom of the Ge content 0%, the top 20%, the doping concentration of 3X1015cm3;

[0180] (4e)利用化学汽相淀积(CVD)的方法,在700°C,在Ge组分梯形分布的SiGe层上生长一层厚度为300nm的P型SiGe层,Ge组分为20 %,掺杂浓度为1 X 1017cm 3; [0180] (4e) a method using a chemical vapor deposition (CVD), and at 700 ° C, grown on the Ge content SiGe layer having a thickness of trapezoidal profile P of 300nm-type SiGe layer, Ge component 20 %, a doping concentration of 1 X 1017cm 3;

[0181] (4f)利用化学汽相淀积(CVD)方法,在700°C,在SiGe层上生长一层厚度为15nm的应变Si层,掺杂浓度为1 X 1017cm 3,作为NM0S器件的沟道; [0181] (4f) by chemical vapor deposition (CVD) method at 700 ° C, SiGe layer grown on the strained Si layer to a thickness of 15nm and a doping concentration of 1 X 1017cm 3, the device as NM0S channel;

[0182] (4g)利用湿法腐蚀,刻蚀掉表面的层Si02。 [0182] (4g) by wet etching, to etch away the surface layer of Si02.

[0183] 步骤5,PM0S器件区制备。 [0183] Step 5 Preparation PM0S device region.

[0184] (5a)利用化学汽相淀积(CVD)方法,在700°C,在衬底表面淀积一层Si02; [0184] (5a) using a chemical vapor deposition (CVD) method at 700 ° C, a layer of Si02 is deposited on the substrate surface;

[0185] (5b)光刻PM0S器件有源区,利用化学汽相淀积(CVD)的方法,在700°C,在PM0S器件有源区沿(110)晶面生长一层厚度为300nm的N型Si缓冲层,掺杂浓度为IX 1017cm 3; [0185] (5b) of the active device region PM0S lithography, by chemical vapor deposition (CVD) method at 700 ° C, in the active device region along PM0S (110) crystal plane grown to a thickness of 300nm N-type Si buffer layer, the doping concentration of IX 1017cm 3;

[0186] (5c)利用化学汽相淀积(CVD)的方法,在700°C,在Si缓冲层上生长一层厚度为15nm的P型SiGe层,Ge组分为20%,掺杂浓度为1 X 1017cm 3; [0186] (5c) using the method of chemical vapor deposition (CVD), and at 700 ° C, a thickness grown on the Si buffer layer is a P-type SiGe layer of 15nm, Ge component of 20%, the doping concentration to 1 X 1017cm 3;

[0187] (5d)利用化学汽相淀积(CVD)的方法,在700°C,在应变SiGe层上生长一层厚度为4nm的本征弛豫Si帽层,形成PM0S器件有源区; [0187] (5d) using a chemical vapor deposition (CVD) method at 700 ° C, the strained SiGe layer is grown in a thickness of 4nm intrinsic relaxed Si cap layer formed PM0S device active region;

[0188] (5e)利用湿法腐蚀,刻蚀掉表面的层Si02。 [0188] (5e) by wet etching, to etch away the surface layer of Si02.

[0189] 步骤6,浅槽隔离制备。 [0189] Step 6, was prepared shallow trench isolation.

[0190] (6a)光刻场氧区,利用干法刻蚀工艺,在隔离区刻蚀出深度为0.4 μπι的浅槽; [0190] (6a) lithography field oxide region, using a dry etch process, the etch depth of 0.4 μπι shallow trench isolation region;

[0191] (6b)利用化学汽相淀积(CVD)方法,在700°C,在浅槽内填充Si02; [0191] (6b) by chemical vapor deposition (CVD) method at 700 ° C, filling the shallow grooves Si02;

[0192] (6c)用化学机械抛光(CMP)方法,除去多余的氧化层,形成浅槽隔离。 [0192] (6c) by chemical mechanical polishing (CMP) process to remove excess oxide layer, forming a shallow trench isolation.

[0193] 步骤7,M0S器件栅极与轻掺杂源漏(LDD)制备。 [0193] Step 7, M0S preparation device gate lightly doped source and drain (LDD).

[0194] (7a)在350 °C,在有源区上用原子层化学汽相淀积(ALCVD)的方法淀积HfOjl,厚度为8nm,作为NM0S器件和PM0S器件的栅介质; [0194] (7a) at 350 ° C, a method on the active region by atomic layer chemical vapor deposition (ALCVD) deposited HfOjl, a thickness of 8nm, and a device NM0S PM0S device gate dielectric;

[0195] (7b)利用化学汽相淀积(CVD)方法,在700°C,在栅介质层上淀积一层本征的Poly-SiGe,厚度为300nm,Ge 组分为20% ; [0195] (7b) by chemical vapor deposition (CVD) method at 700 ° C, an intrinsic layer deposited on the gate dielectric layer Poly-SiGe, the thickness of 300nm, Ge component of 20%;

[0196] (7c)光刻M0S器件栅介质与栅多晶,形成栅极; [0196] (7c) lithography device M0S gate dielectric and the gate poly, the gate is formed;

[0197] (7d)光刻NM0S器件有源区,对NM0S器件有源区进行N型离子注入,形成掺杂浓度为3X 10lscm 3的N型轻掺杂源漏结构(N-LDD)区域; [0197] (7d) lithography NM0S active device region, the active region of the device NM0S N-type ion implantation to form N-type doping concentration of the lightly doped source 3X 10lscm 3 drain structures (N-LDD) region;

[0198] (7e)光刻PM0S器件有源区,对PM0S器件有源区进行P型离子注入,形成掺杂浓度为3X 10lscm 3的P型轻掺杂源漏结构(Ρ-LDD)区域。 [0198] (7e) PM0S lithographic device active region, the active region of the device PM0S P-type ion implantation to form a dopant concentration of P type lightly doped source 3X 10lscm 3 drain structures (Ρ-LDD) region.

[0199] 步骤8,M0S器件形成。 [0199] Step 8, M0S device is formed.

[0200] (8a)利用化学汽相淀积(CVD)方法,在700°C,在整个衬底上淀积一厚度为4nm的 [0200] (8a) by chemical vapor deposition (CVD) method at 700 ° C, a thickness of 4nm deposited on the entire substrate,

s1jl; s1jl;

[0201] (8b)利用干法刻蚀工艺,蚀掉这层Si02,保留NM0S器件和PM0S器件栅极侧墙; [0201] (8b) by a dry etching process, etching away this layer of Si02, and retention devices NM0S PM0S gate spacer device;

[0202] (8c)光刻NM0S器件有源区,在NM0S器件有源区进行N型离子注入,自对准生成NM0S器件的源、漏区和栅极; [0202] (8c) lithography NM0S active device region, N-type ion implantation NM0S device active region, generating a self-aligned device NM0S source and drain regions and a gate;

[0203] (8d)光刻PM0S器件有源区,在PM0S器件有源区进行N型离子注入,自对准生成PM0S器件的源、漏区和栅极。 [0203] (8d) PM0S lithographic device active region, N-type ion implantation PM0S device active region, self-aligned source generates PM0S device, the drain region and the gate.

[0204] 步骤9,构成BiCMOS集成电路。 [0204] Step 9, constituting the BiCMOS integrated circuit.

[0205] (9a)用化学汽相淀积(CVD)方法,在700°C,在整个衬底上淀积400nm厚的Si02层; [0205] (9a) by chemical vapor deposition (CVD) method at 700 ° C, 400nm thick layer of Si02 is deposited over the entire substrate;

[0206] (9b)光刻引线窗口,在整个衬底上溅射一层金属钛(Ti),合金,自对准形成金属硅化物,清洗表面多余的金属,形成金属接触; [0206] (9b) leads photolithography window, over the entire substrate sputtering a metallic titanium (Ti), alloys, self-aligned metal silicide formation, excess metal surface cleaning, metal contact is formed;

[0207] (9c)溅射金属,光刻引线,分别形成NM0S器件的源电极、栅电极、漏电极和PM0S器件的漏电极、源电极、栅电极,以及双极晶体管发射极、基极、集电极金属引线,最终M0S器件构成导电沟道为30nm的混合晶面平面应变BiCMOS集成器件及电路。 [0207] (9c) sputtered metal, lead photolithography, forming a source electrode NM0S device, the gate electrode, the drain electrode and the drain electrode PM0S device, a source electrode, a gate electrode, a bipolar transistor, and an emitter, a base, a collector metal leads, finally constituting the conductive channel device M0S mixed crystal planes 30nm strain and BiCMOS integrated circuit devices.

[0208] 实施例3:制备45nm混合晶面平面应变BiCMOS集成器件及电路,具体步骤如下: [0208] Example 3: 45nm mixing plane strain BiCMOS integrated circuit devices and the preparation of the crystal plane, the following steps:

[0209] 步骤1,S0I衬底材料制备。 [0209] Step 1, S0I prepared substrate material.

[0210] (la)选取N型掺杂浓度为5 X 1015cm 3的Si片,晶面为(110),对其表面进行氧化,氧化层厚度为1 μm,作为上层的基体材料,并在该基体材料中注入氢; [0210] (la) for the selected N-type doping concentration 5 X 1015cm Si sheet 3, crystal faces (110), the surface thereof is oxidized, the oxide layer having a thickness of 1 μm, as an upper base material, and in that the matrix material is injected hydrogen;

[0211] (lb)选取P型掺杂浓度为5X 1015cm 3的Si片,晶面为(100),对其表面进行氧化,氧化层厚度为1 μm,作为下层的基体材料; [0211] (lb) selected P-type dopant concentration of 5X 1015cm Si sheet 3, crystal faces (100), the surface thereof is oxidized, the oxide layer having a thickness of 1 μm, as a base material of the lower layer;

[0212] (lc)采用化学机械抛光(CMP)工艺,分别对下层层和注入氢后的上层基体材料表面进行抛光处理; [0212] (lc) by chemical mechanical polishing (CMP) process, each of the upper surface of the base material after the implantation of hydrogen and lower layers of the polishing process;

[0213] (Id)将抛光处理后的下层和上层基体材料表面S1jg对紧贴,置于超高真空环境中在480°C温度下实现键合; [0213] (Id) of the lower layer after the polishing process and the surface of the material base to close the upper S1jg placed ultra-high vacuum environment to achieve bonding at a temperature of 480 ° C;

[0214] (le)将键合后的基片温度升高100°C,使上层基体材料在注入的氢处断裂,对上层基体材料多余的部分进行剥离,保留200nm的Si材料,并在该断裂表面进行化学机械抛光(CMP),形成SOI结构。 [0214] (le) The substrate temperature after bonding increases 100 ° C, the upper layer base material in a hydrogen injected at the fracture of the material surplus upper base part peeled retained Si material 200nm and the fracture surface chemical mechanical polishing (CMP), forming an SOI structure.

[0215] 步骤2,隔离制备。 [0215] Step 2, Preparation of isolated.

[0216] (2a)光刻双极器件有源区,外延生长一层掺杂浓度为lX1017cm3的Si层,厚度为200nm,作为集电区; [0216] (2a) an active device region of the bipolar lithography, epitaxial growth of a layer of a doping concentration of lX1017cm3 Si layer with a thickness of 200 nm, as a collector region;

[0217] (2b)利用化学汽相淀积(CVD)方法,在800°C,在衬底表面淀积一层Si02; [0217] (2b) by chemical vapor deposition (CVD) method at 800 ° C, a layer of Si02 is deposited on the substrate surface;

[0218] (2c)光刻隔离区,利用干法刻蚀工艺,在隔离区刻蚀出深度为3.5 μπι的深槽; [0218] (2c) lithography isolation region by a dry etch process, the etch depth of 3.5 μπι deep trench isolation region;

[0219] (2d)利用化学汽相淀积(CVD)方法,在800°C,在深槽内表面淀积S1jl,将深槽内表面全部覆盖; Using [0219] (2d) chemical vapor deposition (CVD) method at 800 ° C, in the deep groove surface S1jl deposited, covering the entire surface of the deep trench;

[0220] (2e)利用化学汽相淀积(CVD)方法,在800°C,在深槽内S1jl上再淀积一层SiN层,将深槽内表面全部覆盖; [0220] (2e) using a chemical vapor deposition (CVD) method at 800 ° C, in the deep trench S1jl then depositing a SiN layer, covering the entire surface of the deep trench;

[0221] (2f)利用化学汽相淀积(CVD)方法,在800°C,在深槽内填充Si02,利用化学机械抛光(CMP)方法,除去多余的氧化层,形成深槽隔离。 [0221] (2f) by chemical vapor deposition (CVD) method at 800 ° C, filled in the deep trench Si02, using chemical mechanical polishing (CMP) process to remove excess oxide layer, forming deep trench isolation.

[0222] 步骤3,双极器件制备。 [0222] Step 3. Preparation of bipolar devices.

[0223] (3a)光刻集电区接触区,对集电区进行N型杂质的注入,并在950°C,退火30min激活杂质,形成掺杂浓度为IX 102°cm 3的重掺杂集电极; [0223] (3a) lithography collector region contact area, implanting a collector region of N-type impurities, and the impurities are activated 30min at 950 ° C, annealing, forming a doping concentration of the heavily doped IX 102 cm ° 3 collector;

[0224] (3b)在衬底表面热氧化一S1jl,光刻基区,对基区进行P型杂质的注入,并在950°C,退火30min激活杂质,形成掺杂浓度为5 X 10lscm 3的基区; [0224] (3b) thermally oxidizing the surface of the substrate in a S1jl, the lithographic base, the base region implanting P-type impurities, and the impurities are activated 30min at 950 ° C, annealing, forming a doping concentration of 5 X 10lscm 3 a base region;

[0225] (3c)在衬底表面热氧化一S1jl,光刻发射区,对衬底进行N型杂质的注入,并在950°C,退火30min激活杂质,成掺杂浓度为5 X 102°cm 3的重掺杂发射区,构成双极晶体管; [0225] (3c) on a substrate surface of the thermal oxidation S1jl, photolithography emitting region, the substrate is implanted N-type impurities, and the impurities are activated 30min at 950 ° C, annealing, to a dopant concentration of 5 X 102 ° cm 3 and the heavily doped emitter region of the bipolar transistor configuration;

[0226] (3d)在衬底表面利用化学汽相淀积(CVD)的方法,在800°C,淀积一S1jl。 [0226] (3d) on the substrate surface by chemical vapor deposition (CVD) method at 800 ° C, depositing a S1jl.

[0227] 步骤4,NM0S器件区制备。 [0227] Step 4. Preparation of NM0S device region.

[0228] (4a)利用化学汽相淀积(CVD)方法,在800°C,在衬底表面淀积一层Si02; [0228] (4a) using a chemical vapor deposition (CVD) method at 800 ° C, a layer of Si02 is deposited on the substrate surface;

[0229] (4b)光刻NM0S器件有源区,利用干法刻蚀工艺,在NM0S器件有源区,刻蚀出深度为2.9 μ m的深槽,将氧化层刻透; [0229] (4b) NM0S active device region photolithography, dry etching process, a device active region NM0S, etched depth of 2.9 μ m deep trench, the oxide layer is patterned through;

[0230] (4c)利用化学汽相淀积(CVD)的方法,在750°C,在深槽内沿(100)晶面生长一层厚度为400nm的P型Si缓冲层,掺杂浓度为5 X 1015cm 3; [0230] Method (4c) using a chemical vapor deposition (CVD), and at 750 ° C, in the deep trench along the (100) crystal plane grown to a thickness of 400nm P-type Si buffer layer, the doping concentration 5 X 1015cm 3;

[0231] (4d)利用化学汽相淀积(CVD)的方法,在750°C,P型缓冲层上生长一层厚度为2.1 μπι的P型Ge组分梯形分布的SiGe,底部Ge组分为0%,顶部为25%,掺杂浓度为5 X 1015cm 3; [0231] (4d) using a chemical vapor deposition (CVD) method, on a 750 ° C, P-type buffer layer is grown to a thickness of the P-type SiGe 2.1 μπι trapezoidal Ge content profile, the bottom of the Ge content 0%, the top 25%, the doping concentration 5 X 1015cm 3;

[0232] (4e)利用化学汽相淀积(CVD)的方法,在750°C,在Ge组分梯形分布的SiGe层上生长一层厚度为400nm的P型SiGe层,Ge组分为25%,掺杂浓度为5X 1017cm 3; [0232] (4e) by chemical vapor deposition (CVD) method at 750 ° C, grown to a thickness of 400nm P-type SiGe layer on a SiGe layer in a trapezoidal Ge content profile, Ge component 25 %, a doping concentration of 5X 1017cm 3;

[0233] (4f )利用化学汽相淀积(CVD)方法,在750°C,在SiGe层上生长一层厚度为8nm的应变Si层,掺杂浓度为5X 1017cm 3,作为NM0S器件的沟道; [0233] (4f) by chemical vapor deposition (CVD) method at 750 ° C, grown on the SiGe layer with a thickness of 8nm the strained Si layer, doping concentration of 5X 1017cm 3, the groove as the device NM0S Road;

[0234] (4g)利用湿法腐蚀,刻蚀掉表面的层Si02。 [0234] (4g) by wet etching, to etch away the surface layer of Si02.

[0235] 步骤5,PM0S器件区制备。 [0235] Step 5 Preparation PM0S device region.

[0236] (5a)利用化学汽相淀积化学汽相淀积(CVD)方法,在800°C,在衬底表面淀积一层Si02; [0236] (5a) using a chemical vapor deposition chemical vapor deposition (CVD) method at 800 ° C, a layer of Si02 is deposited on the substrate surface;

[0237] (5b)光刻PM0S器件有源区,利用化学汽相淀积(CVD)的方法,在750°C,在PM0S器件有源区沿(110)晶面生长一层厚度为400nm的N型Si缓冲层,掺杂浓度为5X1017cm3; [0237] (5b) of the active device region PM0S lithography, by chemical vapor deposition (CVD) method at 750 ° C, in the active device region along PM0S (110) crystal plane grown to a thickness of 400nm N-type Si buffer layer, a doping concentration of 5X1017cm3;

[0238] (5c)利用化学汽相淀积(CVD)的方法,在750°C,在Si缓冲层上生长一层厚度为8nm的P型SiGe层,Ge组分为25 %,掺杂浓度为5 X 1017cm 3; [0238] (5c) using the method of chemical vapor deposition (CVD), and at 750 ° C, a thickness grown on the Si buffer layer is a P-type SiGe layer is 8nm, Ge component of 25%, the doping concentration It is 5 X 1017cm 3;

[0239] (5d)利用化学汽相淀积(CVD)的方法,在750°C,在应变SiGe层上生长一层厚度为3nm的本征弛豫Si帽层,形成PM0S器件有源区; [0239] (5d) using a chemical vapor deposition (CVD) method at 750 ° C, the strained SiGe layer is grown in a thickness of 3nm intrinsic relaxed Si cap layer formed PM0S device active region;

[0240] (5e)利用湿法腐蚀,刻蚀掉表面的层Si02。 [0240] (5e) by wet etching, to etch away the surface layer of Si02.

[0241] 步骤6,浅槽隔离制备。 [0241] Step 6, was prepared shallow trench isolation.

[0242] (6a)光刻场氧区,利用干法刻蚀工艺,在隔离区刻蚀出深度为0.5 μπι的浅槽; [0242] (6a) lithography field oxide region, using a dry etch process, the etch depth of 0.5 μπι shallow trench isolation region;

[0243] (6b)利用化学汽相淀积(CVD)方法,在800°C,在浅槽内填充Si02; [0243] (6b) by chemical vapor deposition (CVD) method at 800 ° C, filling the shallow grooves Si02;

[0244] (6c)用化学机械抛光(CMP)方法,除去多余的氧化层,形成浅槽隔离。 [0244] (6c) by chemical mechanical polishing (CMP) process to remove excess oxide layer, forming a shallow trench isolation.

[0245] 步骤7,M0S器件栅极与轻掺杂源漏(LDD)制备。 [0245] Step 7, M0S preparation device gate lightly doped source and drain (LDD).

[0246] (7a)在400 °C,在有源区上用原子层化学汽相淀积(ALCVD)的方法淀积HfOjl,厚度为10nm,作为NM0S器件和PM0S器件的栅介质; [0246] (7a) at 400 ° C, a method on the active region by atomic layer chemical vapor deposition (ALCVD) deposited HfOjl, a thickness of 10nm, and a device NM0S PM0S device gate dielectric;

[0247] (7b)利用化学汽相淀积(CVD)方法,在750°C,在栅介质层上淀积一层本征的Poly-SiGe,厚度为500nm,Ge 组分为30% ; [0247] (7b) by chemical vapor deposition (CVD) method at 750 ° C, an intrinsic layer deposited on the gate dielectric layer Poly-SiGe, the thickness of 500nm, Ge component is 30%;

[0248] (7c)光刻M0S器件栅介质与栅多晶,形成栅极; [0248] (7c) lithography device M0S gate dielectric and the gate poly, the gate is formed;

[0249] (7d)光刻NM0S器件有源区,对NM0S器件有源区进行N型离子注入,形成掺杂浓度为5X 10lscm 3的N型轻掺杂源漏结构(N-LDD)区域; [0249] (7d) lithography NM0S active device region, the active region of the device NM0S N-type ion implantation to form N-type doping concentration of the lightly doped source 5X 10lscm 3 drain structures (N-LDD) region;

[0250] (7e)光刻PM0S器件有源区,对PM0S器件有源区进行P型离子注入,形成掺杂浓度为5X 10lscm 3的P型轻掺杂源漏结构(Ρ-LDD)区域。 [0250] (7e) PM0S lithographic device active region, the active region of the device PM0S P-type ion implantation to form a dopant concentration of P type lightly doped source 5X 10lscm 3 drain structures (Ρ-LDD) region.

[0251] 步骤8,M0S器件形成。 [0251] Step 8, M0S device is formed.

[0252] (8a)利用化学汽相淀积(CVD)方法,在800°C,在整个衬底上淀积一厚度为5nm的S1jl ; [0252] (8a) by chemical vapor deposition (CVD) method at 800 ° C, depositing a thickness of S1jl 5nm across the substrate;

[0253] (8b)利用干法刻蚀工艺,蚀掉这层Si02,保留NM0S器件和PM0S器件栅极侧墙; [0253] (8b) by a dry etching process, etching away this layer of Si02, and retention devices NM0S PM0S gate spacer device;

[0254] (8c)光刻NM0S器件有源区,在NM0S器件有源区进行N型离子注入,自对准生成NM0S器件的源、漏区和栅极; [0254] (8c) lithography NM0S active device region, N-type ion implantation NM0S device active region, generating a self-aligned device NM0S source and drain regions and a gate;

[0255] (8d)光刻PM0S器件有源区,在PM0S器件有源区进行N型离子注入,自对准生成PM0S器件的源、漏区和栅极。 [0255] (8d) PM0S lithographic device active region, N-type ion implantation PM0S device active region, self-aligned source generates PM0S device, the drain region and the gate.

[0256] 步骤9,构成BiCMOS集成电路。 [0256] Step 9, constituting the BiCMOS integrated circuit.

[0257] (9a)用化学汽相淀积(CVD)方法,在800°C,在整个衬底上淀积500nm厚的Si02层; [0257] (9a) by chemical vapor deposition (CVD) method at 800 ° C, a 500nm thick layer of Si02 is deposited over the entire substrate;

[0258] (9b)光刻引线窗口,在整个衬底上溅射一层金属钛(Ti),合金,自对准形成金属硅化物,清洗表面多余的金属,形成金属接触; [0258] (9b) leads photolithography window, over the entire substrate sputtering a metallic titanium (Ti), alloys, self-aligned metal silicide formation, excess metal surface cleaning, metal contact is formed;

[0259] (9c)溅射金属,光刻引线,分别形成NM0S器件的源电极、栅电极、漏电极和PM0S器件的漏电极、源电极、栅电极,以及双极晶体管发射极、基极、集电极金属引线,最终M0S器件构成导电沟道为45nm的混合晶面平面应变BiCMOS集成器件及电路。 [0259] (9c) sputtered metal, lead photolithography, forming a source electrode NM0S device, the gate electrode, the drain electrode and the drain electrode PM0S device, a source electrode, a gate electrode, a bipolar transistor, and an emitter, a base, a collector metal leads, finally constituting the conductive channel device M0S mixed crystal planes 45nm strain and BiCMOS integrated circuit devices.

[0260] 本发明实施例提供的混合晶面应变混合晶面平面应变BiCMOS集成器件及制备方法具有如下优点: [0260] mixed crystal plane provided by the embodiment of the present invention is a mixed crystal planes strain BiCMOS integrated device and method for preparing the strain has the following advantages:

[0261] 1.本发明制备的混合晶面平面应变BiCMOS集成器件及电路中采用了S0I衬底,降低了器件与电路的功耗,提高了器件与电路的可靠性; [0261] Preparation of mixed crystal planes of the strain of the present invention 1. The BiCMOS integrated circuit devices and are employed S0I substrate, reducing the power consumption of the devices and circuits, devices and improve the reliability of the circuit;

[0262] 2.本发明制备的混合晶面平面应变BiCMOS集成器件及电路采用了混合晶面衬底技术,即在同一个衬底片上分布有(100)和(110)这两种晶面,在(100)晶面上电子迀移率最高,而对于空穴,(110)晶面上最高,为(100)晶面上的2.5倍,本发明结合了载流子迀移率同时达到最高的两种晶面,能在不降低一种类型器件的载流子的迀移率的情况下,提高另一种类型器件的载流子的迀移率; [0262] Preparation of mixed crystal planes of the strain of the present invention 2. The BiCMOS integrated circuit devices and uses a hybrid technique crystal plane of the substrate, i.e., distribution (100) and (110) crystal planes of these two on the same substrate sheet, in the (100) crystal face Gan electronic shifting the highest rate, while for the hole (110) the highest crystal face, a (100) crystal face of 2.5 times, the present invention incorporates the carrier while the highest rate shift Gan the two crystal faces, the case can be reduced without Gan one type of device carrier shift rate, increase the carrier device of another type Gan shift rate;

[0263] 3.本发明制备的混合晶面平面应变BiCMOS集成器件及电路,采用选择性外延技术,分别在NM0S器件和PM0S器件有源区选择性生长张应变Si和压应变SiGe材料,使NM0S器件和PM0S器件频率性能和电流驱动能力等电学性能能够获得同时提升,从而CMOS器件与集成电路性能获得了增强; [0263] Preparation of mixed crystal planes of the strain of the present invention 3. The BiCMOS devices and integrated circuits, selective epitaxy, respectively, in the device and selectively NM0S PM0S device active region grown tensile strained Si and SiGe material compressive strain, so NM0S and electrical performance properties PM0S device frequency and the current driving ability can be obtained while improving, so that the integrated circuit CMOS device performance was enhanced;

[0264] 4.本发明制备的混合晶面平面应变BiCMOS集成器件及电路结构中M0S器件采用了高K值的Hf02作为栅介质,提高了M0S器件的栅控能力,增强了NM0S和PM0S器件的电学性能; [0264] Preparation of mixed crystal planes of the strain of the present invention 4. BiCMOS integrated circuit devices and structures M0S Hf02 device uses as high K gate dielectric, the gate control capability M0S improved devices enhanced NM0S devices and PM0S electrical properties;

[0265] 5.本发明制备的混合晶面平面应变BiCMOS集成器件及电路结构中PM0S器件为量子阱器件,即应变SiGe沟道层处于Si帽层和体Si层之间,与表面沟道器件相比,该器件能有效地降低沟道界面散射,提高了器件电学特性;同时,量子阱可以使热电子注入栅介质中的问题得到改善,增加了器件和电路的可靠性; [0265] Preparation of mixed crystal planes of the strain of the present invention 5. BiCMOS integrated circuit devices and structures PM0S device is a quantum well device, i.e., a strained SiGe channel layer is between the cap layer and the bulk Si Si layer, and the surface channel device compared to the device can effectively reduce the channel interface scattering, improving the electrical characteristics of the device; the same time, the quantum well can make the problem of hot electron injection gate dielectric is improved, increasing the reliability of the devices and circuits;

[0266] 6.本发明制备混合晶面平面应变BiCMOS集成器件及电路工艺中,采用Poly-SiGe材料作为栅电极,其功函数随Ge组分的变化而变化,通过调节Poly-SiGe中Ge组分,实现CMOS阈值电压可连续调整,减少了工艺步骤,降低了工艺难度; Preparing the mixed plane strain BiCMOS integrated circuit devices and processes [0266] 6. The crystal plane as the gate electrode, the work function changes with Ge content varied using Poly-SiGe material by adjusting the Ge content Poly-SiGe minutes, to achieve the threshold voltage CMOS continuously adjustable, reducing the process steps, reduces the difficulty of the process;

[0267] 7.本发明制备的混合晶面平面应变BiCMOS集成器件及电路过程中涉及的最高温度为800°C,低于引起应变Si沟道应力弛豫的工艺温度,因此该制备方法能有效地保持应变Si沟道应力,提高集成电路的性能; [0267] maximum temperature of the mixed crystal planes 7. The present invention is a strain prepared in BiCMOS integrated circuits and devices involved in the process is 800 ° C, below the stress relaxation caused by strained Si channel process temperature, this method can be prepared holding channel stress strained Si, improve the performance of the integrated circuit;

[0268] 8.本发明制备的混合晶面平面应变BiCMOS集成器件及电路中,双极器件采用S0I衬底的集电区厚度较传统器件薄,因此,该器件存在集电区横向扩展效应,并能够在集电区形成二维电场,从而提高了该器件的反向击穿电压和Early电压,在相同的击穿特性下,具有比传统器件更优异的特征频率。 [0268] Preparation of the mixed crystal planes 8. The present invention is strained and BiCMOS integrated circuit device, the bipolar device is the collector region of the thickness of the substrate sheet S0I than conventional devices, therefore, the presence of lateral spreading effect collector region of the device, capable of forming a two-dimensional electric field and collector region, thereby increasing the reverse breakdown voltage of the device and the Early voltage, at the same breakdown characteristics, having more excellent frequency characteristics than conventional devices. 以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。 The above are only preferred embodiments of the present invention but are not intended to limit the present invention, any modifications within the spirit and principle of the present invention, equivalent replacements and improvements should fall in the protection of the present invention within range.

Claims (3)

1.一种混合晶面平面应变BiCMOS集成器件的制备方法,其特征在于,包括如下步骤:第一步、选取两片Si片,一块是N型掺杂浓度为1〜5X 1015cm 3的Si (110)衬底片,作为上层有源层的基体材料,另一块是P型掺杂浓度为1〜5 X 1015cm 3的Si (100)衬底片,作为下层有源层的基体材料;对两片Si片表面进行氧化,氧化层厚度为0.5〜1 μ m,采用化学机械抛光(CMP)工艺对两个氧化层表面进行抛光; 第二步、对上层有源层基体材料中注入氢,并将两片Si片氧化层相对置于超高真空环境中在350〜480°C的温度下实现键合;将键合后的Si片温度升高100〜200°C,使上层基体材料在注入的氢处断裂,对上层基体材料多余的部分进行剥离,保留100〜200nm的Si材料,并在其断裂表面进行化学机械抛光(CMP),形成SOI衬底; 第三步、光刻双极器件有源区,外延生长一层掺杂浓度为1 X 1016〜1 X 10 17cm 3 A mixed crystal planes strain preparation method BiCMOS integrated device, characterized by comprising the steps of: a first step, selecting two Si wafer, an N type doping concentration of 1~5X Si 1015cm 3 ( 110) substrate sheet, as the base material of the upper layer of the active layer, the other is a P-type dopant concentration of 1~5 X 1015cm Si 3 (100) substrate sheet, as a lower layer of the active layer, the base material; two of Si the sheet surface is oxidized, the oxide layer having a thickness of 0.5~1 μ m, by chemical mechanical polishing (CMP) process for polishing both surfaces of the oxide layer; a second step, a hydrogen implanted layer of the upper layer of the active matrix material, and the two Si wafer substrate disposed opposite the oxide layer to achieve ultra-high vacuum environment at a temperature of bonding of 350~480 ° C; the temperature of the Si wafer after bonding increases 100~200 ° C, the upper layer of the matrix material is injected hydrogen at breaking, the excess upper material base part peeled off, retention of 100~200nm Si material, and a chemical mechanical polishing (CMP) on the fracture surface, forming an SOI substrate; a third step, the bipolar device active lithography region, a doping concentration of the epitaxial growth layer 1 X 1016~1 X 10 17cm 3 的Si层,厚度为100〜200nm,作为集电区; 第四步、利用化学汽相淀积(CVD)方法,在600〜800°C,在衬底表面淀积一层Si02,光刻隔离区,利用干法刻蚀工艺,在隔离区刻蚀出深度为2.5〜3.5 μπι的深槽,利用化学汽相淀积(CVD)方法,在600〜800°C,在衬底表面淀积一层Si02和一层SiN,将深槽内表面全部覆盖,最后淀积Si02将深槽内填满,形成深槽隔离; 第五步、光刻集电区接触区,对集电区进行N型杂质的注入,并在800〜950°C,退火.30〜90min激活杂质,形成掺杂浓度为1 X 1019〜1 X 10 20cm-3的重掺杂集电极;第六步、在衬底表面热氧化一S1jl,光刻基区,对基区进行p型杂质的注入,并在.800〜950°C,退火30〜90min激活杂质,形成掺杂浓度为1 X 1018~ 5X10 18cm 3的基区;第七步、在衬底表面热氧化一S1jl,光刻发射区,对衬底进行N型杂质的注入,并在.800〜950°C,退火30〜90min激 Si layer, having a thickness of 100~200nm, a collector region; a fourth step, using a chemical vapor deposition (CVD) method, at 600~800 ° C, a layer of Si02 is deposited on the substrate surface, the photolithography spacer region, using a dry etching process, the etching depth of the isolation region 2.5~3.5 μπι deep groove, by chemical vapor deposition (CVD) method, at 600~800 ° C, a deposition surface of the substrate Si02 layer, and a layer of SiN, a deep groove to cover the entirety of the surface of the last deposited Si02 fills deep trench, forming deep trench isolation; a fifth step, photolithography collector region contact region of N-type collector region impurities are injected, and at 800~950 ° C, annealing .30~90min activating the impurity, is formed a doping concentration of 1 X 1019~1 X 10 20cm-3 highly doped collector; a sixth step, the surface of the substrate a thermal oxidation S1jl, base photolithography, implanting a base region of p-type impurities, and the impurities are activated at 30~90min .800~950 ° C, annealing, forming a doping concentration of 1 X 1018 ~ 5X10 18cm 3-yl region; seventh step, the surface of the substrate in a thermal oxidation S1jl, photolithography emitting region, the substrate is implanted N-type impurities, and the shock 30~90min .800~950 ° C, annealing 活杂质,形成掺杂浓度为5X 1019〜5X 10 20cm 3的重掺杂发射区,在衬底表面利用化学汽相淀积(CVD)的方法,在600〜800°C,淀积一S1jl ; 第八步、利用化学汽相淀积(CVD)方法,在600〜800°C,在衬底表面淀积一层Si02,光刻NM0S器件有源区,利用干法刻蚀工艺,在NM0S器件有源区,刻蚀出深度为1.7〜2.9 μm的深槽,将中间的氧化层刻透;利用化学汽相淀积(CVD)方法,在600〜750°C,在(100)晶面衬底的NM0S器件有源区上选择性外延生长四层材料:第一层是厚度为200〜400nm的P型Si缓冲层,掺杂浓度为1〜5X 1015cm 3;第二层是厚度为1.3〜2.lnm的P型SiGe渐变层,该层底部Ge组分是0%,顶部Ge组分是15〜25%,掺杂浓度为1〜5 X 1015cm 3;第三层是Ge组分为15〜25 %,厚度为200〜400nm的P型SiGe层,掺杂浓度为0.5〜5 X 1017cm 3,第四层是厚度为8〜20nm的P型应变Si层,掺杂浓度为0.5〜5X 1017cm 3,作为NM0S器件的 Live impurity, is formed heavily doped with a doping concentration of 5X 1019~5X 10 20cm 3 emitter region, the surface of the substrate by chemical vapor deposition (CVD) method, at 600~800 ° C, depositing a S1jl; an eighth step, using a chemical vapor deposition (CVD) method, at 600~800 ° C, a layer of Si02 is deposited on the substrate surface, the active device region NM0S photolithography, a dry etching process, the device NM0S active area, the etching depth of 1.7~2.9 μm deep groove, will be carved through the intermediate oxide layer; using a chemical vapor deposition (CVD) method, at 600~750 ° C, the (100) plane substrate selective epitaxial growth on the bottom of the device active region NM0S four materials: a first layer having a thickness of 200~400nm P-type Si buffer layer, the doping concentration of 1~5X 1015cm 3; a second layer having a thickness of 1.3~ 2.lnm P-type SiGe graded layer, the bottom layer is a Ge content of 0%, the top of the Ge content is 15~25%, a doping concentration of 1~5 X 1015cm 3; third component layer is a Ge 15 ~ 25%, the P-type SiGe layer having a thickness of 200~400nm, and a doping concentration of 0.5~5 X 1017cm 3, the fourth layer having a thickness of the strained Si layer 8~20nm P-type, the doping concentration 0.5~5X 1017cm 3, the device as NM0S 道;利用湿法腐蚀,刻蚀掉表面的层Si02; 第九步、利用化学汽相淀积(CVD)方法,在600〜800°C,在衬底表面淀积一层Si02,光刻PM0S器件有源区,利用化学汽相淀积(CVD)方法,在600〜750°C,在PM0S器件有源区上选择性外延生长三层材料:第一层是厚度为100〜200nm的N型Si缓冲层,掺杂浓度为.0.5〜5X 1017cm 3,第二层是厚度为8〜20nm的N型SiGe应变层,Ge组分是15〜25%,掺杂浓度为0.5〜5X 1017cm 3,作为PM0S器件的沟道;第三层是厚度为3〜5nm的本征弛豫Si帽层,形成PM0S器件有源区;利用湿法腐蚀,刻蚀掉表面的层Si02; 第十步、光刻场氧区,利用干法刻蚀工艺,在场氧区刻蚀出深度为0.3〜0.5 μπι的浅槽;再利用化学汽相淀积(CVD)方法,在600〜800°C,在浅槽内填充Si02;最后,用化学机械抛光(CMP)方法,除去多余的氧化层,形成浅槽隔离; 第十一步、在300〜400°C,在有源区上用原 Tao; by wet etching, etching away the surface layer of Si02; ninth step, by chemical vapor deposition (CVD) method, at 600~800 ° C, the surface of the substrate depositing a layer of Si02, photolithography PM0S device active region, by chemical vapor deposition (CVD) method, at 600~750 ° C, in the device active region PM0S selective epitaxial growth of three layers of material: a first N-type layer having a thickness of 100~200nm Si buffer layer, the doping concentration of .0.5~5X 1017cm 3, the second layer having a thickness of N-type SiGe strained layer of 8~20nm, Ge component is 15~25%, a doping concentration of 0.5~5X 1017cm 3, PM0S as a channel device; the third layer having a thickness of the intrinsic layer of relaxed Si cap 3~5nm formed PM0S active device region; using a wet etching, etching away the surface layer of Si02; tenth step, light engraved field oxide region, using a dry etching process, the field oxide regions etched depth is shallow groove 0.3~0.5 μπι; then using a chemical vapor deposition (CVD) method, at 600~800 ° C, the shallow grooves the packed Si02; Finally, chemical mechanical polishing (CMP) process to remove excess oxide layer, forming a shallow trench isolation; eleventh step, at 300~400 ° C, with the original on the active region 子层化学汽相淀积(ALCVD)的方法淀积HfOjl,厚度为6〜10nm,作为NM0S器件和PM0S器件的栅介质,再利用化学汽相淀积(CVD)方法,在600〜750°C,在栅介质层上淀积一层厚度为100〜500nm的本征Poly-SiGe作为栅电极,Ge组分为10〜30% ;光刻NM0S和PM0S器件栅介质与栅多晶,形成栅极; 第十二步、光刻NM0S器件有源区,对NM0S器件有源区进行N型离子注入,形成掺杂浓度为1〜5X 10lscm 3的N型轻掺杂源漏结构(N-LDD)区域;光刻PM0S器件有源区,对PM0S器件有源区进行P型离子注入,形成掺杂浓度为1〜5X 10lscm 3的P型轻掺杂源漏结构(P-LDD)区域; 第十三步、利用化学汽相淀积(CVD)方法,在600〜800°C,在整个衬底上淀积一厚度为.3〜5nm的S1jl,用干法刻蚀掉这层S1 2,形成NM0S器件和PM0S器件栅极侧墙; 第十四步、光刻NM0S器件有源区,在NM0S器件有源区进行N型离子注入,自对准生成NM0S器件的源区 Method sublayer chemical vapor deposition (ALCVD) deposited HfOjl, thickness 6~10nm, as the gate dielectric and device NM0S PM0S device, and then using a chemical vapor deposition (CVD) method, at 600~750 ° C , deposited to a thickness on the gate dielectric layer 100~500nm intrinsic Poly-SiGe gate electrode, Ge component 10~30%; NM0S lithography devices and PM0S gate dielectric and the gate poly, the gate ; twelfth step, photolithography NM0S device active region, the active region of the device NM0S N-type ion implantation to form N-type doping concentration of the lightly doped source 1~5X 10lscm 3 drain structures (N-LDD) region; PM0S lithographic device active region, the active region of the device PM0S P-type ion implantation, the doping concentration of the dopant forming source and drain structures (P-LDD) is a light 10lscm 3 1~5X P-type region; tenth three steps, using a chemical vapor deposition (CVD) method, at 600~800 ° C, is deposited over the entire substrate to a thickness of .3~5nm S1jl, which layer is etched away by a dry S1 2, is formed NM0S PM0S device and the device gate sidewall spacer; a fourteenth step, a lithographic NM0S device active region, N-type ion implantation NM0S device active region, self-aligned source region generating device NM0S 漏区和栅极;光刻PM0S器件有源区,在PM0S器件有源区进行N型离子注入,自对准生成PM0S器件的源区、漏区和栅极; 第十五步、在整个衬底上用化学汽相淀积(CVD)方法,在600〜800°C,淀积300〜.500nm厚的S1jg ;光刻出引线窗口,在整个衬底上派射一层金属钛(Ti),合金,自对准形成金属娃化物,清洗表面多余的金属,形成金属电极,构成M0S器件导电沟道为22〜45nm的混合晶面平面应变BiCMOS集成器件。 A drain region and a gate; PM0S lithography device active region in the device active region PM0S N-type ion implantation, a self-aligned source region PM0S generating device, a drain region and a gate; step 15, the entire liner on the bottom by chemical vapor deposition (CVD) method, at 600~800 ° C, the deposition thickness 300~.500nm S1jg; photolithography window leads, over the entire substrate layer of metal shot sent titanium (Ti) , alloy, forming self-aligned metal compound baby, to clean the surface excess metal, a metal electrode constituting the conductive channel device M0S strain BiCMOS integrated device is of the mixed crystal planes 22~45nm.
2.根据权利要求1所述的制备方法,其特征在于,NM0S和PM0S器件的沟道长度取22〜.45nm The production method according to claim 1, wherein the channel length of the device taken NM0S and PM0S 22~.45nm
3.一种混合晶面平面应变BiCMOS集成电路的制备方法,其特征在于,包括如下步骤: 步骤1,SOI衬底材料制备的实现方法为: (la)选取N型掺杂浓度为lX1015cm3的Si片,晶面为(110),对其表面进行氧化,氧化层厚度为0.5 μ m,作为上层的基体材料,并在该基体材料中注入氢; (lb)选取P型掺杂浓度为lX1015cm3的Si片,晶面为(100),对其表面进行氧化,氧化层厚度为0.5 μ m,作为下层的基体材料; (lc)采用化学机械抛光(CMP)工艺,分别对下层和注入氢后的上层基体材料表面进行抛光处理; (Id)将抛光处理后的下层和上层基体材料表面S1jg对紧贴,置于超高真空环境中在.350°C温度下实现键合; (le)将键合后的基片温度升高200°C,使上层基体材料在注入的氢处断裂,对上层基体材料多余的部分进行剥离,保留100nm的Si材料,并在该断裂表面进行化学机械抛光(CMP),形成SOI结构; A mixed crystal planes strain prepared BiCMOS integrated circuit, characterized by comprising the following steps: Step 1, to realize a method of preparing an SOI substrate material: (La) selected N-type doping concentration of Si lX1015cm3 sheet, crystal faces (110), oxidizing the surface thereof, the oxide layer having a thickness of 0.5 μ m, as an upper base material, and injecting the hydrogen in the matrix material; (LB) select P-type dopant concentration lX1015cm3 of Si wafer, crystal faces (100), oxidizing the surface thereof, the oxide layer having a thickness of 0.5 μ m, as the base material of the lower layer; (LC) using chemical mechanical polishing (CMP) process, respectively lower and hydrogen implantation after the upper surface of the base material is polished; (Id) the lower and upper surface of the base material after the polishing process for S1jg close, placed ultra-high vacuum environment to achieve bonding at a temperature of .350 ° C; (Le) the key substrate temperature after bonding increases 200 ° C, the upper layer base material in a hydrogen injected at the fracture of the material surplus upper base part peeled retained Si material 100nm and chemical mechanical polishing (CMP the fracture surface ), an SOI structure is formed; 骤2,隔离制备的实现方法为: (2a)光刻双极器件有源区,外延生长一层掺杂浓度为1 X 1016cm 3的Si层,厚度为.100nm,作为集电区; (2b)利用化学汽相淀积(CVD)方法,在600°C,在衬底表面淀积一层Si02; (2c)光刻隔离区,利用干法刻蚀工艺,在隔离区刻蚀出深度为2.5 μπι的深槽; (2d)利用化学汽相淀积(CVD)方法,在600°C,在深槽内表面淀积S1jl,将深槽内表面全部覆盖; (2e)利用化学汽相淀积(CVD)方法,在600°C,在深槽内S1jl上再淀积一层SiN层,将深槽内表面全部覆盖; (2f)利用化学汽相淀积(CVD)方法,在600°C,在深槽内填充Si02,利用化学机械抛光(CMP)方法,除去多余的氧化层,形成深槽隔离; 步骤3,双极器件制备的实现方法为: (3a)光刻集电区接触区,对集电区进行N型杂质的注入,并在800°C,退火90min激活杂质,形成掺杂浓度为1 X 1019cm 3的重掺杂集电极; (3b)在衬 Step 2, preparation method of isolation is achieved: (2a) an active device region of the bipolar lithography, epitaxial growth of a layer of a doping concentration of 1 X 1016cm 3 Si layer thickness .100nm, as a collector region; (2B ) by chemical vapor deposition (CVD) method at 600 ° C, the surface of the substrate depositing a layer of Si02; (2c) lithography isolation region by a dry etching process, the etching depth of the isolation region 2.5 μπι deep trench; (2D) using a chemical vapor deposition (CVD) method at 600 ° C, in the deep groove surface S1jl deposited, covering the entire surface of the deep trench; (2E) using a chemical vapor deposition product (CVD) method at 600 ° C, in a deep trench and then depositing a layer on S1jl SiN layer, covering the entire surface of the deep trench; (. 2F) by chemical vapor deposition (CVD) method at 600 ° C, filled in the deep trench Si02, using chemical mechanical polishing (CMP) process to remove excess oxide layer, forming deep trench isolation; step 3, methods of making bipolar device implemented as: a contact (3a) lithography collector region region, the collector region for implanting N-type impurities, and the impurities are activated 90min at 800 ° C, annealing, forming a doping concentration of the heavily doped collector 1 X 1019cm 3; (3B) in the substrate 底表面热氧化一S1jl,光刻基区,对基区进行P型杂质的注入,并在800°C,退火90min激活杂质,形成掺杂浓度为1 X 1018cm 3的基区; (3c)在衬底表面热氧化一S1jl,光刻发射区,对衬底进行N型杂质的注入,并在.800°C,退火90min激活杂质,成掺杂浓度为5 X 1019cm 3的重掺杂发射区,构成双极晶体管;(3d)在衬底表面利用化学汽相淀积(CVD)的方法,在600°C,淀积一S1jl ; 步骤4,NM0S器件区制备的实现方法为: (4a)利用化学汽相淀积(CVD)方法,在600°C,在衬底表面淀积一层Si02; (4b)光刻NMOS器件有源区,利用干法刻蚀工艺,在NM0S器件有源区,刻蚀出深度为.1.7 μ m的深槽,将氧化层刻透; (4c)利用化学汽相淀积(CVD)的方法,在600°C,在深槽内沿(100)晶面生长一层厚度为200nm的P型Si缓冲层,掺杂浓度为1 X 1015cm 3; (4d)利用化学汽相淀积(CVD)的方法,在600°C,P型缓冲层上生长一层厚度 A bottom surface of the thermal oxidation S1jl, the lithographic base, the base region implanting P-type impurities, and the impurities are activated 90min at 800 ° C, annealing, forming a doping concentration of 1 X 1018cm base region 3; (. 3C) in thermally oxidizing the surface of the substrate a S1jl, photolithography emitting region, the substrate is implanted N-type impurities, and the impurities are activated 90min at .800 ° C, annealing, to a doping concentration of the heavily doped emitter region of 5 X 1019cm 3 constituting a bipolar transistor; (3D) surface of the substrate in the process of using a chemical vapor deposition (CVD), and at 600 ° C, depositing a S1jl; step 4, implementation of the device region NM0S prepared: (4a) by chemical vapor deposition (CVD) method at 600 ° C, the surface of the substrate depositing a layer of Si02; (4b) lithography NMOS device active region by a dry etching process, the active device region NM0S , etched depth .1.7 μ m deep trench, the oxide layer is patterned transparent; (4C) using a chemical vapor deposition (CVD) method at 600 ° C, in a deep groove along the (100) crystal plane grown to a thickness of 200nm P-type Si buffer layer, a dopant concentration of 1 X 1015cm 3; (4d) using a chemical vapor deposition (CVD) method, on a 600 ° C, P-type buffer layer grown layer thickness 1.3 μπι的Ρ型Ge组分梯形分布的SiGe,底部Ge组分为0%,顶部为15%,掺杂浓度为1 X 1015cm 3; (4e)利用化学汽相淀积(CVD)的方法,在600°C,在Ge组分梯形分布的SiGe层上生长一层厚度为200nm的P型SiGe层,Ge组分为15%,掺杂浓度为5 X 1016cm 3; (4f)利用化学汽相淀积(CVD)方法,在600°C,在SiGe层上生长一层厚度为20nm的应变Si层,掺杂浓度为5X 1016cm 3,作为NM0S器件的沟道; (4g)利用湿法腐蚀,刻蚀掉表面的层Si02; 步骤5,PM0S器件区制备的实现方法为: (5a)利用化学汽相淀积(CVD)方法,在600°C,在衬底表面淀积一层Si02; (5b)光刻PM0S器件有源区,利用化学汽相淀积(CVD)的方法,在600°C,在PM0S器件有源区沿(110)晶面生长一层厚度为200nm的N型Si缓冲层,掺杂浓度为5 X 1016cm 3; (5c)利用化学汽相淀积(CVD)的方法,在600°C,在Si缓冲层上生长一层厚度为20nm的P型SiGe层,Ge组分为15%,掺杂浓度为 SiGe 1.3 μπι Ρ the trapezoidal distribution component type Ge, Ge bottom component is 0%, the top 15%, a doping concentration of 1 X 1015cm 3; (4e) The method using a chemical vapor deposition (CVD), and at 600 ° C, grown on the Ge content SiGe layer having a thickness of trapezoidal profile P of 200nm-type SiGe layer, Ge component of 15%, a doping concentration 5 X 1016cm 3; (4f) by chemical vapor deposition (CVD) method at 600 ° C, SiGe layer grown on the strained Si layer to a thickness of 20nm, the doping concentration of 5X 1016cm 3, as the device channel NM0S; (4G) by wet etching, etching away the surface layer of Si02; step 5, prepared by implementation of the device region PM0S: (5a) using a chemical vapor deposition (CVD) method at 600 ° C, a layer of Si02 is deposited on the substrate surface; ( 5b) PM0S lithographic device active region, by chemical vapor deposition (CVD) method at 600 ° C, in the active device region along PM0S (110) crystal plane grown to a thickness of 200nm N-type Si buffer layer, a doping concentration 5 X 1016cm 3; (5c) using a chemical vapor deposition (CVD) method at 600 ° C, grown to a thickness of 20nm P-type Si layer on the SiGe buffer layer, Ge group A 15% doping concentration 5X 1016cm 3; (5d)利用化学汽相淀积(CVD)的方法,在600°C,在应变SiGe层上生长一层厚度为5nm的本征弛豫Si帽层,形成PM0S器件有源区; (5e)利用湿法腐蚀,刻蚀掉表面的层Si02; 步骤6,浅槽隔离制备的实现方法为: (6a)光刻场氧区,利用干法刻蚀工艺,在隔离区刻蚀出深度为0.3 μπι的浅槽; (6b)利用化学汽相淀积(CVD)方法,在600°C,在浅槽内填充Si02; (6c)用化学机械抛光(CMP)方法,除去多余的氧化层,形成浅槽隔离; 步骤7,MOS器件栅极与轻掺杂源漏(LDD)制备的实现方法为: (7a)在300°C,在有源区上用原子层化学汽相淀积(ALCVD)的方法淀积HfOjl,厚度为6nm,作为NM0S器件和PM0S器件的栅介质; (7b)利用化学汽相淀积(CVD)方法,在600°C,在栅介质层上淀积一层本征的Poly-SiGe,厚度为lOOnm,Ge 组分为10% ; (7c)光刻MOS器件栅介质与栅多晶,形成栅极; (7d)光刻NM0S器件有源区,对N 5X 1016cm 3; (5d) method using a chemical vapor deposition (CVD), and at 600 ° C, a thickness of the strain grown on the relaxed SiGe layer is intrinsic Si cap layer is 5nm, device active region formed PM0S ; (5E) by wet etching, etching away the surface layer of Si02; step 6, to achieve shallow trench isolation process for the preparation of: (6a) lithography field oxide region, using a dry etching process, etching the isolation region the depth of the shallow groove is 0.3 μπι; (6B) by chemical vapor deposition (CVD) method at 600 ° C, filling the shallow grooves Si02; (6c) by chemical mechanical polishing (CMP) method, removing excess oxide layer, forming shallow trench isolation; step 7, MOS device gate implementation lightly doped source and drain (LDD) was prepared: (7a) at 300 ° C, by atomic layer chemical vapor deposition on the active region the method of product (ALCVD) deposited HfOjl, a thickness of 6 nm, as the gate dielectric and device NM0S PM0S device; (7B) by chemical vapor deposition (CVD) method at 600 ° C, is deposited on the gate dielectric layer intrinsic layer of Poly-SiGe, the thickness of lOOnm, Ge component 10%; (7c) lithography MOS device gate dielectric and the gate poly, the gate is formed; (7D) lithography NM0S active device region, for N M0S器件有源区进行N型离子注入,形成掺杂浓度为.1 X 1018cm 3的N型轻掺杂源漏结构(N-LDD)区域; (7e)光刻PM0S器件有源区,对PM0S器件有源区进行P型离子注入,形成掺杂浓度为.1 X 1018cm 3的P型轻掺杂源漏结构(P-LDD)区域; 步骤8,M0S器件形成的实现方法为: (8a)利用化学汽相淀积(CVD)方法,在600°C,在整个衬底上淀积一厚度为3nm的Si02层; (8b)利用干法刻蚀工艺,蚀掉这层Si02,保留NM0S器件和PM0S器件栅极侧墙; (8c)光刻NM0S器件有源区,在NM0S器件有源区进行N型离子注入,自对准生成NM0S器件的源、漏区和栅极; (8d)光刻PM0S器件有源区,在PM0S器件有源区进行N型离子注入,自对准生成PM0S器件的源、漏区和栅极; 步骤9,构成BiCMOS集成电路的实现方法为: (9a)用化学汽相淀积(CVD)方法,在600°C,在整个衬底上淀积300nm厚的S1jl ;(9b)光刻引线窗口,在整个衬底上派射一层金属 M0S active device region N-type ion implantation, forming a doping concentration of .1 X 1018cm 3 lightly doped N-type source and drain structures (N-LDD) region; (7E) PM0S lithographic device active region, for PM0S device active region of the P-type ion implantation to form a dopant concentration of P-type lightly doped .1 X 1018cm 3 of the source and drain structures (P-LDD) regions; step 8, the device-implemented method M0S formed is: (8a) by chemical vapor deposition (CVD) method at 600 ° C, a thickness of a Si02 layer deposited over the entire substrate 3nm; (8B) by a dry etching process, etching away this layer of Si02, retention device NM0S and PM0S device gate sidewall spacer; (8C) NM0S lithographic device active region in the device active region NM0S N-type ion implantation, a self-aligned device generates NM0S source and drain regions and a gate; (8D) of light engraved PM0S device active region in the device active region PM0S N-type ion implantation, a self-aligned source generates PM0S device, a drain region and a gate; step 9, an integrated circuit constituting the BiCMOS implementation of: (9a) with chemical vapor deposition (CVD) method at 600 ° C, a 300nm-thick is deposited over the entire substrate S1jl; (9B) leads photolithography window, over the entire substrate layer of metal shot sent (Ti),合金,自对准形成金属娃化物,清洗表面多余的金属,形成金属接触; (9c)溅射金属,光刻引线,分别形成NM0S器件的源电极、栅电极、漏电极和PM0S器件的漏电极、源电极、栅电极,以及双极晶体管发射极、基极金属引、集电极金属引线,最终M0S器件构成导电沟道为22nm的混合晶面平面应变BiCMOS集成器件及电路。 (Ti), alloys, forming self-aligned metal compound baby, to clean the surface of excess metal to form a metal contact; (9C) sputtered metal, lead photolithography, forming a source electrode NM0S device, the gate electrode, the drain electrode and PM0S the drain electrode of the device, a source electrode, a gate electrode, a bipolar transistor, and an emitter, a base metal lead, a collector metal wire, constituting the conductive channel device M0S final mixed crystal planes 22nm strain and BiCMOS integrated circuit devices.
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