CN101207101A - 用于干刻蚀的图案屏蔽结构及其方法 - Google Patents

用于干刻蚀的图案屏蔽结构及其方法 Download PDF

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CN101207101A
CN101207101A CNA2007101609958A CN200710160995A CN101207101A CN 101207101 A CN101207101 A CN 101207101A CN A2007101609958 A CNA2007101609958 A CN A2007101609958A CN 200710160995 A CN200710160995 A CN 200710160995A CN 101207101 A CN101207101 A CN 101207101A
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telecommunication
building brick
aforementioned
electronic building
package structure
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CN101207101B (zh
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游明志
邱建嘉
江国宁
杨文焜
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Yupei Science & Technology Co Ltd
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Abstract

本发明提出一种用于干刻蚀的图案屏蔽结构及其方法，所述的图案屏蔽结构包括一种强化接地特性与内埋天线型的立体堆栈封装单元，此封装单元可通过位于上下两侧的电讯接点达到多芯片堆栈的目的。该封装单元于电子组件基材背面具有单或复数层接地层，提供半导体组件便利的接地途径，并且比封装单元适用于晶片级封装制造方式，故可降低单一封装单元体的制作成本。前述接地层也为本发明的封装结构中电子组件信号传递的途径，配合位于电子组件层周围的单或复数个导通孔，可使该封装结构上下两侧的电讯进行沟通，提高封装单元的应用性。又该接地层中可具有环型围绕型态的电讯沟道，形成内埋天线型立体堆栈封装结构。

Description

用于干刻蚀的图案屏蔽结构及其方法
技术领域
本发明是有关一种电子封装结构，特别是一种强化接地特性与内埋天线型的立体堆栈封装单元，此封装单元中，于电子组件基材背面具有单或复数层接地层，同时可通过封装单元两侧的电讯接点达到多芯片堆栈的目的。
背景技术
现今电子产品多以符合小型化、高性能、高精度、高信赖度、及高反应度等为目标，使电路组件的分布密度过高、电路的体积大幅缩小，然而电子产品的电路愈精巧，则将有愈多组件形成于微小空间中，故使彼此间电讯干扰机会上升，影响电子产品信号的稳定；其中又以电磁干扰(ElectromagneticInterference，EMI)及噪声为最常出现的问题。EMI的抑制主要分为辐射性(Radiated)与传导性(Conducted)电磁干扰，辐射性EMI为直接经由开放空间传递，不须要经由任何传输介质，故一般仅能以遮蔽(Shielding)、接地(Grounding)等方式来解决；本发明所提出的强化接地特性的立体堆栈封装单元，于电子组件基材背面具有单或复数层接地层用以加强可堆栈式封装单元的电气特性，降低电磁干扰对高密度电子组件可靠度的影响。
现有的堆栈型集成电路芯片封装如美国专利第6,387,728号所揭示，请参阅图1，该封装100是于一基板102的顶面设有一第一集成电路芯片103并于该第一集成电路芯片103上进行打线作业，形成复数焊线104并电性连接该第一集成电路芯片103与该基板102接着，于该第一集成电路芯片103顶面涂布一层黏着层105，可将一第二集成电路芯片106黏附于其顶面，同样利用打线作业形成复数焊线107连接该第二集成电路芯片106与该基板102的后，再利用一封装胶108布设于该基板102上且将各组件全部包覆其中，即完成一堆栈型集成电路芯片的封装程序。堆栈型集成电路封装将二个或二个以上的芯片堆栈在一起并共享一基板，在增加芯片个数的同时可有效地节省空间；然而因芯片内部信号的传递须通过焊线连接基板后方可进行，易产生信号延迟现象，同时由于此种封装结构电讯传递路径过长，若庭、用于高频电子组件则易产生噪声，影响电子组件的电讯可靠度。
美国专利字号6,236,115中，揭示一种高密度集成电路芯片封装结构，请参阅图2；该封装结构仍采用芯片堆栈方式形成，然为了降低如前述利用焊线作为传递芯片问信号时所可能产生的信号延迟现象，第一集成电路芯片201、第二集成电路芯片202与第三集成电路芯片203间并不以打线作业形成电连通路。该专利主要利用复数个导通孔206形成于芯片中，同时于孔壁布上金属化线路204，并配合具导电特性的固着结构205，故可有效缩短芯片间电讯传递路径，减少信号产生噪声的情形；该封装结构虽可缩短芯片间传递路径，然而因集成电路芯片的分布密度上升，不同种类芯片彼此间电讯干扰机会上升，将影响电子产品信号的稳定。
鉴于具系统整合的多微电子组件堆栈电子封装将成为微电子、高频通讯或致动传感器等电子结构模块的趋势，并且为减低堆栈封装的技术成本，与达成封装体积微小化的目的，如何发展出一种高密度、高结构与电性可靠度，同时设计、组装可依据应用需求功能作适当弹性调整的多微电子组件封装结构，实为当前急需解决的问题。
发明内容
鉴于前述技术的缺失及其系统整合的多微电子组件堆栈电子封装将成为微电子、高频通讯或致动传感器等电子结构模块的趋势，本发明具有以下的目的：
本发明提出一种电子封装结构，其目的在于提供一种具多重微电子组件的晶片级封装单元体，其上下表面具连接电路图案可依应用环境与功能的需求，弹性地进行单或复数个堆栈组装微小化封装结构，以减少电讯传递路径与时间而提升此堆栈封装模块的工作频率与效能。
本发明的另一目的在于提供一种电子封装结构，其封装单元体可于晶片或基材上批次制作完成，故可降低单一封装单元体的制作成本。
本发明的另一目的在于提供一种电子封装结构，该封装结构中，于电子组件基材背面具有单或复数层接地层用以加强其电气特性，故可降低电磁干扰对高密度电子组件可靠度的影响。
为达成前述目的，本发明所提出的电子封装结构，包含有：单或复数层用以形成电子组件的基材。单或复数个电子组件，形成于前述电子组件的基材，且该电子组件的总表面积小于或等于前述电子组件基材的表面积。单或复数个接触垫，布于前述电子组件的表面。单或复数个缓冲区域，该缓冲区域分布于前述电子组件的四周。单或复数层接地层，形成于前述电子组件基材的背面O单或复数个导通孔，形成于前述缓冲区域，且于该导通孔内或孔壁填充具导电特性的材料，使前述缓冲区域的上表面与前述接地层间具有电讯连通的特性。单或复数个电讯沟道，形成于前述电子封装结构的单侧或双侧。单或复数个电讯接点，形成于前述电讯沟道的末端，且分布于前述电子封装结构的单侧或双侧。
附图说明
本发明的较佳实施例将于下述说明中辅以下列图形做更详细的阐述：
图1为现有堆栈型集成电路芯片封装结构的示意图。
图2为现有以晶片钻孔方式形成的高密度集成电路芯片封装结构的示意图。
图3A为本发明的第一实施例，为封装单元的截面图(图3B中的A-A′截面)。
图3B为对应于图3A，本发明第一实施例的可能底视图。
图4A为本发明的第一实施例于电子组件基材上的可能分布方式放大图。
图4B为对应图4A的放大区域，本发明第一实施例于电子组件基材上的可能截面图。
图5A为晶片堆栈示意图。
图5B为对应图5A，晶片堆栈后进行切割程序的侧视图。
图6为本发明的第二实施例，为利用本发明的封装单元进行第一形式堆栈封装的截面示意图。
图7为本发明的第三实施例，为利用本发明的封装单元进行第二形式堆栈封装的截面示意图。
图8为本发明的第四实施例，为利用本发明的封装单元进行第三形式堆栈封装的截面示意图。
100  堆栈型集成电路芯片封装    102  基板
103  第一集成电路芯片          104  焊线
105  黏着层                    106  第二集成电路芯片
107  焊线                      108  封装胶
201  第一集成电路芯片          202  第二集成电路芯片
203  第三集成电路芯片          204  金属化线路
205  固着结构                  206  导通孔
300  第一封装单元              301  具电讯传递的固着结构
302  第一电讯接点              303  第一电路保护层
304  第一覆盖层                305  第二覆盖层
306  第二接触垫                307  第一内导线层
308  第一导通孔                309  第一接触垫
310  第二导通孔                311  电子组件接地层
312  第二电路保护层            313  第一电子组件层
314  第二电讯接点              315  第三电讯接点
316  第四电讯接点              317  第二内导线层
318  电子组件基材                321  第一电讯沟道
322  第三导通孔                  323  第五电讯接点(测试接点)
324  无线信号接收天线            325  第二电讯沟道
326  第三电讯沟道                327  第四电讯沟道
400  晶片                        401  第一接触垫
402  第二导通孔                  403  晶片切割道
404  第一内导线层                405  具电讯传递的固着结构
406  第一电讯接点                407  电子组件基材
408  缓冲区域                    409  第二接触垫
430  放大区域                    450  第一电子组件层
460  第二电子组件层              470  第三电子组件层
480  第四电子组件层              501  第一晶片
502  第二晶片                    505  第一具电讯传递的固着结构
506  第二具电讯传递的固着结构    507  晶片切割道
550  第一电子组件层              560  第二电子组件层
570  第三电子组件层              580  第四电子组件层
601  基板                        602  电讯接点
603  第一具电讯传递的固着结构    604  第二具电讯传递的固着结构
605  第一电子组件层              606  第二电子组件层
610  第一封装单元体              620  第二封装单元体
701  基板                        702  电讯接点
703  第一具电讯传递的固着结构    704  第二具电讯传递的固着结构
705  接合材料                    706  具电讯传递的接合材料
707  第三具电讯传递的固着结构    708  第三聚电讯传递的固着结构
709  第一电讯沟道                710  第一封装单元体
720  第二封装单元体              730  第三封装单元体
801  基板                        802  电讯接点
803  第一具电讯传递的固着结构    804  第二具电讯传递的固着结构
805  具电讯传递的接合材料        810  第一封装单元体
820  第二封装单元体              830  第三封装单元体
具体实施方式
本发明的前述与其它目的、特征、以及优点，将通过下文中参照图示的较佳实施例的详细说明得以更明确。
本发明揭示一种电子封装结构。详言之，本发明提出一种强化接地特性的立体堆栈封装单元，此封装单元可通过两侧的电讯接点达到多芯片堆栈的目的。该发明的实施例详细说明如下，唯所述的较佳实施例只做一说明，并非用以限定本发明。
图3A为本发明的第一封装单元体300的截面图，也为三B图中的A-A’截面。图中电子组件基材318其材料组成元素可为硅、锗、锡、碳，或以上元素与他种具半导体特性元素的组合，利用现有的半导体制程技术，将第一电子组件层313形成于电子组件基材318上，该电子组件可为主动电子组件、被动电子组件、感测组件、测试组件、微机电芯片或以上电子组件的组合；于电子组件基材318中，未包含第一电子组件层313的部分为一缓冲区域(图3中未特别标明)，该位置因不具有电子线路于其中，故于本发明中利用此位置作为第二导通孔310的加工位置，并于内部或孔壁填充具导电特性的材料，使电子组件基材318的上、下表面形成电连通路；第二导通孔310可利用如机械钻孔、激光钻孔、干湿法刻蚀或其它适合的方式形成，同时内部充填的导电金属可为锡、银、金、铝、铍、铜、镍、铑、钨或以上金属材料合金或他种具导电性的材料的组合。
第一电子组件层313上方布有第一接触垫309与第二接触垫306，为该组件内部电路与外界信号传递的途径，位于第一电子组件层313上的第一内导线层307，以溅射、电镀或其它适合的方式形成，并将位于第一、二接触垫(309、306)的电路信号重新分布；第一覆盖层304与第二覆盖层305可合而为一层覆盖层，除可提高封装单元表面的平坦性，并可于其间进行图案化制程，形成第二内导线层317、第一导通孔308，强化前述的电路信号重布，增加第一封装单元体300于进行堆栈时的应用性。
电子组件接地层311形成于第一封装单元体300的下表面，该接地层的材料可为铜、镍、铁、铝、钴、金、或以上金属材料合金或他种具导电性的材料的组合，该金属层除作为电子组件的接地层，同时为一热的良导体，具有导热的特性，可帮助驱散由第一电子组件层313所产生的热能；该电子组件接地层311可利用如机械加工、干湿法刻蚀、激光钻孔或其它适合的方式形成电讯沟道，图3A中的接地层即为经过图案化程序后的侧视图。第一电路保护层303与第二电路保护层312形成于第一封装单元体300的上下两侧，提供保护第一内导线层307、第二内导线层317与电子组件接地层311的功用；同时于该保护层定义第一电讯接点302、第二电讯接点314、第三电讯接点315、第四电讯接点316的位置，并可于该电讯接点上利用网版印刷、模板印刷、滚筒式涂布、喷墨涂布、光刻技术或其它适合的方式形成电讯接点保护层(图3中未特别标明)。具电讯传递的固着结构301形成于前述的电讯接点保护层上，用以连接第一封装单元体300与其它电子设备间的电路信号。
如图3A中所示，第一电子组件层313内的电路信号，其传递路径可为：(1)第二接触垫306→第一内导线层307→第二导通孔310→电子组件接地层311→第三电讯接点315(第一封装单元体300的下表面)；(2)第一接触垫309→第二内导线层317→第一电讯接点302→具电讯传递的固着结构301(第一封装单元体300的上表面)。位于第一电子组件层313中的电讯可如前述传递至第一封装单元体300的上下表面，使于3D堆栈式封装的进行；前述的较佳实施例结构只做一说明，并非用以限定本发明。
图3B为对应于图3A，本发明第一实施例的可能底视图，为便于说明，此图中忽略图3A中的第二电路保护层312。电子组件接地层311经图案化制程后，形成第一电讯沟道321、第二电讯沟道325、第三电讯沟道326与第四电讯沟道327；图3B中无法显示第一封装单元体300上表面的第一电子组件层313，故利用虚线部份表示。第一电子组件层313内的接地信号可经由第三导通孔322传递至电子组件接地层311，完成电子组件的接地。第二导通孔310分布于第一封装单元体300的周围，可利用第三电讯沟道326与第二电讯接点314相连接，达到配置电讯接点位置的目的。电子组件接地层311经图案化制程后也可形成如第五电讯接点323的测试专用接点，并与封装结构内部电子组件的测试信号相连通，形成一具测试功能的电子封装结构；另，该图案化制程可形成无线信号接收天线324，利用比具有环型围绕型态的电讯沟道，可使第一封装单元体300具有可与外界进行无线信号传递的特性；然前述的较佳实施例结构只做一说明，并非用以限定本发明。
图4A为本发明的第一实施例于电子组件基材上的可能分布方式放大图。该上视图中，晶片400上布有复数个本发明的强化接地特性立体堆栈封装单元，放大区域430中包含有第一电子组件层450、第二电子组件层460、第三电子组件层470与第四电子组件480，电子组件层间的缓冲区域408可利用如机械钻孔、激光钻孔、干湿法刻蚀或其它适合的方式，形成单或复数个第二导通孔402；第一电子组件层450内部的电讯可由第一接触垫401，循第一内导线层404至第二导通孔402，将信号传递至封装单元下表面的电子组件接地层，并利用图案化该接地层的方式，进行封装单元下表面电讯接点的配置。同时，第二电子组件层460内部的电讯可由第二接触垫409，利用如图3A第一实施例中的叙述方式，于封装单元上表面进行电讯接点配置。前述的封装单元体皆于晶片或基材上批次制作完成，故可降低单一封装单元体的制作成本，晶片切割道403用以分割晶片400，完成本发明的强化接地特性立体堆栈封装单元。
图4B为对应图4A的放大区域，本发明第一实施例于电子组件基材上的可能截面圆。电子组件基材407上有第一电子组件层450、第二电子组件层460，该电子组件层周围其缓街区域408；第一电子组件层450上方有第一电讯接点406及具电讯传递的固着结构405；本发明的强化接地特性立体堆栈封装单元即利用此缓冲区域中，扣除第二导通孔402位置后的部份进行晶片切割，如图中的晶片切割道403所示；前述的较佳实施例结构只做一说明，并非用以限定本发明。
图5A为晶片堆栈示意图，第一晶片501与第二晶片502上皆布有复数个本发明的强化接地特性立体堆栈封装单元，该晶片的分割也可于晶片间完成堆栈程序后进行；如图5B所示，此图为对应图5A，晶片堆栈后进行切割程序的侧视图；第一电子组件层550、第二电子组件层560位于第二晶片502上，第三电子组件层570、第四电子组件层580位于第一晶片501上；第一电子组件层550与第三电子组件层570间的电路信号可通过第一具电讯传递的固着结构505做传递，同时第二电子组件层560与第四电子组件层580间的电路信号可通过第二具电讯传递的固着结构506进行传递，晶片切割道507用以分割晶片并形成本发明的强化接地特性立体堆栈封装结构，如图6中所示。
图6为本发明的第二实施例，为利用本发明的封装单元进行第一形式堆栈封装的截面示意图。第一封装单元体610中具有第一电子组件层605，第二封装单元体620中具有第二电子组件层606，位于两电子组件层中的电路信号可通过第二具电讯传递的固着结构604进行传递；基板601上具有电讯接点602，利用第一具电讯传递的固着结构603，可使第一封装单元体610，第二封装单元体620与基板601形成电讯导通，进而达成堆栈封装的目的；前述的较佳实施例结构只做一说明，并非用以限定本发明。
图7为本发明的第三实施例，为利用本发明的封装单元进行第二形式堆栈封装的截面示意图。第一封装单元体710、第二封装单元体720与第三封装单元体730于上下两侧相对应位置皆具有电讯接点，其中第一封装单元体710与第二封装单元体720间的电路信号可通过第二其电讯传递的固着结构进行传递，另第二封装单元体720与第三封装单元体730间的电路信号，可以具电讯传递的接合材料706进行传递。本发明的强化接地特性的立体堆栈封装单元，因其封装结构下表面具有可进行图案化的金属层(接地层)，故可形成电讯沟道于该层；第一封装单元体710上利用接地层所形成的第一电讯沟道709，可提供第三具电讯传递的固着结构707与第四具电讯传递的固着结构708间信号的连通。基板701上具有电讯接点702，利用第一具电讯传递的固着结构703与第二其电讯传递的固着结构704，可使第一封装单元体710、第二封装单元体720、第三封装单元体730与基板701形成电讯导通，进而达成堆栈封装的目的，同时为提高封装结构整体的可靠度，接合材料705可施加于具电讯传递的固着结构703周围，用以增加固着结构的强度；前述的较佳实施例结构只做一说明，并非用以限定本发明。
图8为本发明的第四实施例，为利用本发明的封装单元进行第三形式堆栈封装的截面示意图。第一封装单元体810上具有不同尺寸的第二封装单元体820与第三封装单元体830；第一封装单元体810与第二封装单元体820间利用其电讯传递的接合材料805进行信号传递，同时第一封装单元体810与第三封装单元体830间利用第二具电讯传递的固着结构804进行信号传递。基板801上具有电讯接点802，利用第一具电讯传递的固着结构803，可使第一封装单元体810，第二封装单元体820、第三封装单元体830与基板801形成电讯导通，进而达成堆栈封装的目的。
本发明较佳实施例说明如上，而熟悉此领域技艺，在不脱离本发明的精神范围内，当可做些许更动润饰，其专利保护范围更当视的权利要求及其等同领域而定。

Claims (10)

1.一种电子封装结构，其特征在于，该电子封装结构至少包含：
单或复数层用以形成电子组件的基材；
单或复数个电子组件，形成于前述电子组件的基材，且该电子组件的总表面积小于或等于前述电子组件基材的表面积；
单或复数个接触垫，布于前述电子组件的表面；
单或复数个缓冲区域，该缓冲区域分布于前述电子组件的四周；
单或复数层接地层，形成于前述电子组件基材的背面；
单或复数个导通孔，形成于前述缓冲区域，且于该导通孔内或孔壁填充其导电特性的材料，使前述缓街区域的上表面与前述接地层间具有电讯连通的特性；
单或复数个电讯沟道，形成于前述电子封装结构的单侧或双侧；
单或复数个电讯接点，形成于前述电讯沟道的末端，且分布于前述电子封装结构的单侧或双侧。
2.如权利要求1所述的电子封装结构，其特征在于，其中所述位于电子封装结构两侧的电讯沟道，可利用前述的导通孔进行电讯传递，使位于该电子封装结构两侧的电讯沟道形成通路。
3.如权利要求1所述的电子封装结构，其特征在于，其中所述用以形成电子组件的基材，其材料组成元素可为硅、锗、锡、碳，或以上元素的混合或与他种具半导体特性元素的组合；其中该缓冲区域材料与该电子组件基材相同，且该缓冲区域内的电子组件基材不用以形成该电子组件。
4.如权利要求1所述的电子封装结构，其特征在于，其中所述的接地层，可为铜、镍、铁、铝、钴、金、或以上金属材料合金或他种具导电性的材料的组合；其中该电子封装结构，其中该导通孔，其内部所充填的导电金属可为锡、银、金、铝、铍、铜、镍、铑、钨或以上金属材料合金或他种其导电性的材料的组合。
5.如权利要求1所述的电子封装结构，其特征在于，还包含一防护层，形成于该电讯接点上，其中该防护层可利用网版印刷、模板印刷、滚筒式涂布、喷墨涂布、光刻技术或其它适合的方式形成。
6.一种具复数个封装单元体的立体堆栈电子封装结构，其特征在于，该电子封装结构至少包含：
复数层用以形成电子组件的基材；
复数个电子组件，形成于前述电子组件的基材，且该电子组件的总表面积小于或等于前述电子组件基材的表面积；
复数个接触垫，布于前述电子组件的表面；
复数个缓冲区域，该缓冲区域分布于前述电子组件的四周；
复数层接地层，形成于前述电子组件基材的背面；
复数个导通孔，形成于前述缓冲区域，且于该导通孔内或孔壁填充具导电特性的材料，使前述缓冲区域的上表面与前述接地层间具有电讯连通的特性；
复数个电讯沟道，形成于前述电子封装结构的单侧或双侧；
复数个电讯接点，形成于前述电讯沟道的末端，且分布于前述电子封装结构的单侧或双侧；
复数个固着结构，形成于前述的电讯接点。
7.如权利要求6所述的具复数个封装单元体的立体堆栈电子封装结构，其特征在于，其中所述位于电子封装结构两侧的电讯沟道，可利用前述的导通孔进行电讯传递，使位于该电子封装结构两侧的电讯沟道形成通路。
8.如权利要求6所述的具复数个封装单元体的立体堆栈电子封装结构，其特征在于，其中所述用以形成电子组件的基材，其材料组成元素可为硅、锗、锡、碳，或以上元素的混合或与他种具半导体特性元素的组合；其中该缓冲区域材料与该电子组件基材相同，且该缓冲区域内的电子组件基材不用以形成该电子组件。
9.如权利要求6所述的具复数个封装单元体的立体堆栈电子封装结构，其特征在于，其中所述的接地层，可为铜、镍、铁、铝、钴、金、或以上金属材料合金或他种具导电性的材料的组合；其中该电子封装结构，其中该导通孔，其内部所充填的导电金属可为锡、银、金、铝、铍、铜、镍、铑、钨或以上金属材料合金或他种其导电性的材料的组合。
10.如权利要求6所述的具复数个封装单元体的立体堆栈电子封装结构，其特征在于，还包含一防护层，形成于该电讯接点上，其中该防护层可利用网版印刷、模板印刷、滚筒式涂布、喷墨涂布、光刻技术或其它适合的方式形成。
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